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authorChristudasan Devadasan <Christudasan.Devadasan@amd.com>2024-07-03 03:26:29 +0000
committerChristudasan Devadasan <Christudasan.Devadasan@amd.com>2024-07-03 03:56:33 +0000
commit95cd3f1c75cdce1b6488bfa623f8d3339b84b4ea (patch)
tree052ee4547fd17c4652ce6579b16c4281d85fdf87
parentc954705eca57144a5a1a1e57513501b5195bfe5e (diff)
downloadllvm-users/cdevadas/constrained-sload-insns.zip
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handle the pseudo instruction defs inside a multiclass.users/cdevadas/constrained-sload-insns
-rw-r--r--llvm/lib/Target/AMDGPU/SMInstructions.td35
1 files changed, 17 insertions, 18 deletions
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 137acd3..de8f0f9 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -161,26 +161,25 @@ class SM_Discard_Pseudo <string opName, OffsetMode offsets>
let has_soffset = offsets.HasSOffset;
}
-multiclass SM_Pseudo_Loads<RegisterClass baseClass,
- RegisterClass dstClass> {
- defvar opName = !tolower(NAME);
- def _IMM : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
- def _SGPR : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
- def _SGPR_IMM : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
+multiclass SM_Load_Pseudos<string op, RegisterClass baseClass,
+ RegisterClass dstClass, OffsetMode offsets> {
+ defvar opName = !tolower(op);
+ def "" : SM_Load_Pseudo <opName, baseClass, dstClass, offsets>;
// The constrained multi-dword load equivalents with early clobber flag at
- // the dst operand. They are needed only for codegen and there is no need for
- // their real opcodes.
- if !gt(dstClass.RegTypes[0].Size, 32) then {
- let SubtargetPredicate = isGFX8Plus, Constraints = "@earlyclobber $sdst" in {
- let PseudoInstr = NAME # !cast<OffsetMode>(IMM_Offset).Variant in
- def _IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, IMM_Offset>;
- let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_Offset).Variant in
- def _SGPR_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_Offset>;
- let PseudoInstr = NAME # !cast<OffsetMode>(SGPR_IMM_Offset).Variant in
- def _SGPR_IMM_ec : SM_Load_Pseudo <opName, baseClass, dstClass, SGPR_IMM_Offset>;
- }
- }
+ // the dst operands. They are needed only for codegen and there is no need
+ // for their real opcodes.
+ if !gt(dstClass.RegTypes[0].Size, 32) then
+ let Constraints = "@earlyclobber $sdst",
+ PseudoInstr = op # offsets.Variant in
+ def "" # _ec : SM_Load_Pseudo <opName, baseClass, dstClass, offsets>;
+}
+
+multiclass SM_Pseudo_Loads<RegisterClass baseClass,
+ RegisterClass dstClass> {
+ defm _IMM : SM_Load_Pseudos <NAME, baseClass, dstClass, IMM_Offset>;
+ defm _SGPR : SM_Load_Pseudos <NAME, baseClass, dstClass, SGPR_Offset>;
+ defm _SGPR_IMM : SM_Load_Pseudos <NAME, baseClass, dstClass, SGPR_IMM_Offset>;
}
multiclass SM_Pseudo_Stores<RegisterClass baseClass,