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| author | Thorsten Schütt <schuett@gmail.com> | 2024-04-12 21:10:19 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-04-12 21:10:19 +0200 |
| commit | c777c011a709dffd4fa5e79cad7947b7c3405d02 (patch) | |
| tree | bd00dbce7b134865d9fbdd195b8c82243dfe67f9 | |
| parent | b074f25329501487e312b59e463a2d5f743090f8 (diff) | |
| download | llvm-c777c011a709dffd4fa5e79cad7947b7c3405d02.zip llvm-c777c011a709dffd4fa5e79cad7947b7c3405d02.tar.gz llvm-c777c011a709dffd4fa5e79cad7947b7c3405d02.tar.bz2 | |
[GlobalIsel] Import vscale (#88240)
https://github.com/llvm/llvm-project/pull/84542
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll | 52 |
2 files changed, 56 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 312e564..9b4575f 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -2550,6 +2550,10 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, MIRBuilder.buildInstr(TargetOpcode::G_RESET_FPMODE, {}, {}); return true; } + case Intrinsic::vscale: { + MIRBuilder.buildVScale(getOrCreateVReg(CI), 1); + return true; + } case Intrinsic::prefetch: { Value *Addr = CI.getOperand(0); unsigned RW = cast<ConstantInt>(CI.getOperand(1))->getZExtValue(); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll new file mode 100644 index 0000000..d06e2c6 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vscale.ll @@ -0,0 +1,52 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s + +define i64 @call_vscale_i64() { + ; CHECK-LABEL: name: call_vscale_i64 + ; CHECK: bb.1.entry: + ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s64) = G_VSCALE i64 1 + ; CHECK-NEXT: $x0 = COPY [[VSCALE]](s64) + ; CHECK-NEXT: RET_ReallyLR implicit $x0 +entry: + %vscale = call i64 @llvm.vscale.64() + ret i64 %vscale +} + +define i64 @call_vscale_i32() { + ; CHECK-LABEL: name: call_vscale_i32 + ; CHECK: bb.1.entry: + ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s32) = G_VSCALE i32 1 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s32) + ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64) + ; CHECK-NEXT: RET_ReallyLR implicit $x0 +entry: + %vscale = call i32 @llvm.vscale.32() + %zext = zext i32 %vscale to i64 + ret i64 %zext +} + +define i64 @call_vscale_i16() { + ; CHECK-LABEL: name: call_vscale_i16 + ; CHECK: bb.1.entry: + ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s16) = G_VSCALE i16 1 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s16) + ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64) + ; CHECK-NEXT: RET_ReallyLR implicit $x0 +entry: + %vscale = call i16 @llvm.vscale.16() + %zext = zext i16 %vscale to i64 + ret i64 %zext +} + +define i64 @call_vscale_i8() { + ; CHECK-LABEL: name: call_vscale_i8 + ; CHECK: bb.1.entry: + ; CHECK-NEXT: [[VSCALE:%[0-9]+]]:_(s8) = G_VSCALE i8 1 + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VSCALE]](s8) + ; CHECK-NEXT: $x0 = COPY [[ZEXT]](s64) + ; CHECK-NEXT: RET_ReallyLR implicit $x0 +entry: + %vscale = call i8 @llvm.vscale.8() + %zext = zext i8 %vscale to i64 + ret i64 %zext +} |