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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2024-03-28 19:21:35 +0000 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2024-03-28 19:39:17 +0000 |
commit | 5b06de7f99ef86c484f5fea5542c1868e798ac08 (patch) | |
tree | 57904c9c208625515b02d80e7b6958cd8a48e687 | |
parent | 346f49927f32f72148882100410f78b83f2733a8 (diff) | |
download | llvm-5b06de7f99ef86c484f5fea5542c1868e798ac08.zip llvm-5b06de7f99ef86c484f5fea5542c1868e798ac08.tar.gz llvm-5b06de7f99ef86c484f5fea5542c1868e798ac08.tar.bz2 |
[X86] Add isLogicOp helper to match ISD::AND/OR/XOR and X86ISD::ANDNP
We could easily support the X86ISD 'float' variants of the logic ops as well, but we don't have good test coverage at the moment (they're mainly for SSE1 targets).
-rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 9d98d31..312e448 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2631,6 +2631,11 @@ bool X86::mayFoldIntoZeroExtend(SDValue Op) { return false; } +static bool isLogicOp(unsigned Opcode) { + // TODO: Add support for X86ISD::FAND/FOR/FXOR/FANDN with test coverage. + return ISD::isBitwiseLogicOp(Opcode) || X86ISD::ANDNP == Opcode; +} + static bool isTargetShuffle(unsigned Opcode) { switch(Opcode) { default: return false; @@ -39975,8 +39980,7 @@ static SDValue canonicalizeShuffleWithOp(SDValue N, SelectionDAG &DAG, auto IsSafeToMoveShuffle = [ShuffleVT](SDValue Op, unsigned BinOp) { // Ensure we only shuffle whole vector src elements, unless its a logical // binops where we can more aggressively move shuffles from dst to src. - return BinOp == ISD::AND || BinOp == ISD::OR || BinOp == ISD::XOR || - BinOp == X86ISD::ANDNP || + return isLogicOp(BinOp) || (Op.getScalarValueSizeInBits() <= ShuffleVT.getScalarSizeInBits()); }; |