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| author | Philip Reames <preames@rivosinc.com> | 2024-03-28 12:32:17 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-28 12:32:17 -0700 |
| commit | 346f49927f32f72148882100410f78b83f2733a8 (patch) | |
| tree | 267ee32b6476cfdd2e42e4ffa07acce4ddb59595 | |
| parent | 6f10dccbab4630604f8a6073ac4b9fb61bf8fc9e (diff) | |
| download | llvm-346f49927f32f72148882100410f78b83f2733a8.zip llvm-346f49927f32f72148882100410f78b83f2733a8.tar.gz llvm-346f49927f32f72148882100410f78b83f2733a8.tar.bz2 | |
[RISCV] Add add_like PatFrags to reduce number of required patterns [nfc] (#86983)
This is an NFC prep patch for an upcoming change which is going to
support or_is_add in a bunch more cases. Posting separately because
tblgen is not particularly my strong suit.
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 12 |
2 files changed, 7 insertions, 9 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 966cdc4..fd8777f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1259,6 +1259,10 @@ def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ }]>; def : PatGprSimm12<or_is_add, ADDI>; +def add_like : PatFrags<(ops node:$lhs, node:$rhs), + [(or_is_add node:$lhs, node:$rhs), + (add node:$lhs, node:$rhs)]>; + // negate of low bit can be done via two (compressible) shifts. The negate // is never compressible since rs1 and rd can't be the same register. def : Pat<(XLenVT (sub 0, (and_oneuse GPR:$rs, 1))), diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td index a882b20..549bc039 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -255,7 +255,7 @@ class binop_with_non_imm12<SDPatternOperator binop> }]; } def add_non_imm12 : binop_with_non_imm12<add>; -def or_is_add_non_imm12 : binop_with_non_imm12<or_is_add>; +def add_like_non_imm12 : binop_with_non_imm12<add_like>; def Shifted32OnesMask : IntImmLeaf<XLenVT, [{ if (!Imm.isShiftedMask()) @@ -756,13 +756,10 @@ def : Pat<(i64 (shl (and GPR:$rs1, 0xFFFFFFFF), uimm5:$shamt)), def : Pat<(i64 (and GPR:$rs1, Shifted32OnesMask:$mask)), (SLLI_UW (XLenVT (SRLI GPR:$rs1, Shifted32OnesMask:$mask)), Shifted32OnesMask:$mask)>; -def : Pat<(i64 (add_non_imm12 (and GPR:$rs1, 0xFFFFFFFF), GPR:$rs2)), +def : Pat<(i64 (add_like_non_imm12 (and GPR:$rs1, 0xFFFFFFFF), GPR:$rs2)), (ADD_UW GPR:$rs1, GPR:$rs2)>; def : Pat<(i64 (and GPR:$rs, 0xFFFFFFFF)), (ADD_UW GPR:$rs, (XLenVT X0))>; -def : Pat<(i64 (or_is_add_non_imm12 (and GPR:$rs1, 0xFFFFFFFF), GPR:$rs2)), - (ADD_UW GPR:$rs1, GPR:$rs2)>; - foreach i = {1,2,3} in { defvar shxadd_uw = !cast<Instruction>("SH"#i#"ADD_UW"); def : Pat<(i64 (add_non_imm12 (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 i)), (XLenVT GPR:$rs2))), @@ -876,13 +873,10 @@ let Predicates = [HasStdExtZba, IsRV64] in { def : Pat<(shl (i64 (zext i32:$rs1)), uimm5:$shamt), (SLLI_UW GPR:$rs1, uimm5:$shamt)>; -def : Pat<(i64 (add_non_imm12 (zext GPR:$rs1), GPR:$rs2)), +def : Pat<(i64 (add_like_non_imm12 (zext GPR:$rs1), GPR:$rs2)), (ADD_UW GPR:$rs1, GPR:$rs2)>; def : Pat<(zext GPR:$src), (ADD_UW GPR:$src, (XLenVT X0))>; -def : Pat<(i64 (or_is_add_non_imm12 (zext GPR:$rs1), GPR:$rs2)), - (ADD_UW GPR:$rs1, GPR:$rs2)>; - foreach i = {1,2,3} in { defvar shxadd = !cast<Instruction>("SH"#i#"ADD"); def : Pat<(i32 (add_non_imm12 (shl GPR:$rs1, (i64 i)), GPR:$rs2)), |