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| author | Brandon Wu <brandon.wu@sifive.com> | 2024-03-06 09:12:14 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-06 09:12:14 +0800 |
| commit | 6c39e3fa113d2956cb5b5f6769d2ad9a266377e5 (patch) | |
| tree | 7ef6ce08e6e2a6059bf3dc1035c9904b7001203b | |
| parent | 0207270494cda484f80abd3b654c871dc4cf8099 (diff) | |
| download | llvm-6c39e3fa113d2956cb5b5f6769d2ad9a266377e5.zip llvm-6c39e3fa113d2956cb5b5f6769d2ad9a266377e5.tar.gz llvm-6c39e3fa113d2956cb5b5f6769d2ad9a266377e5.tar.bz2 | |
[clang][RISCV] Reorder sema check for RVV type (#83553)
Currently using the command `clang -cc1 -triple riscv64` to compile the
code below:
```
#include <riscv_vector.h>
void foo() {
vfloat64m1_t f64m1;
}
```
would get the error message "RISC-V type 'vfloat64m1_t' ... requires the
'zve64x' extension"
which is supposed to be "RISC-V type 'vfloat64m1_t' ... requires the
'zve64d' extension".
| -rw-r--r-- | clang/lib/Sema/SemaChecking.cpp | 11 | ||||
| -rw-r--r-- | clang/test/Sema/riscv-vector-float64-check.c | 3 |
2 files changed, 7 insertions, 7 deletions
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 9a2aa21..561764e 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -6391,10 +6391,14 @@ void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) { unsigned EltSize = Context.getTypeSize(Info.ElementType); unsigned MinElts = Info.EC.getKnownMinValue(); + if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) && + !TI.hasFeature("zve64d")) + Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d"; // (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at // least zve64x - if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts == 1) && - !TI.hasFeature("zve64x")) + else if (((EltSize == 64 && Info.ElementType->isIntegerType()) || + MinElts == 1) && + !TI.hasFeature("zve64x")) Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x"; else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") && !TI.hasFeature("zvfhmin")) @@ -6406,9 +6410,6 @@ void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) { else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) && !TI.hasFeature("zve32f")) Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f"; - else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) && - !TI.hasFeature("zve64d")) - Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d"; // Given that caller already checked isRVVType() before calling this function, // if we don't have at least zve32x supported, then we need to emit error. else if (!TI.hasFeature("zve32x")) diff --git a/clang/test/Sema/riscv-vector-float64-check.c b/clang/test/Sema/riscv-vector-float64-check.c index ee7db32..f21ae5c 100644 --- a/clang/test/Sema/riscv-vector-float64-check.c +++ b/clang/test/Sema/riscv-vector-float64-check.c @@ -1,5 +1,4 @@ -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +zve64f -target-feature +zfh \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +zve32x \ // RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify // REQUIRES: riscv-registered-target #include <riscv_vector.h> |