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| author | Alexey Bataev <a.bataev@outlook.com> | 2024-03-27 14:25:30 -0700 |
|---|---|---|
| committer | Alexey Bataev <a.bataev@outlook.com> | 2024-03-27 14:26:05 -0700 |
| commit | 552c8eb731a1fabef4d81e2a69911506adf39e22 (patch) | |
| tree | 1f3a93aeb3bbdb64dc4ad1c8832ff970bbeea722 | |
| parent | b9cd48f96acdd07c627ccafbf4386a1f3dcd6c51 (diff) | |
| download | llvm-552c8eb731a1fabef4d81e2a69911506adf39e22.zip llvm-552c8eb731a1fabef4d81e2a69911506adf39e22.tar.gz llvm-552c8eb731a1fabef4d81e2a69911506adf39e22.tar.bz2 | |
[SLP][NFC]Add a test with the wrong result extension after reduction,
NFC.
| -rw-r--r-- | llvm/test/Transforms/SLPVectorizer/RISCV/reduction-extension-after-bitwidth.ll | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/reduction-extension-after-bitwidth.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/reduction-extension-after-bitwidth.ll new file mode 100644 index 0000000..611003a --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/RISCV/reduction-extension-after-bitwidth.ll @@ -0,0 +1,33 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S -mtriple=riscv64-unknown-linux-gnu -mattr="+v" --passes=slp-vectorizer < %s | FileCheck %s + +define i32 @test(ptr %0, ptr %1) { +; CHECK-LABEL: define i32 @test( +; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[LOAD_5:%.*]] = load i32, ptr [[TMP1]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> <i1 true, i1 true, i1 true, i1 true>) +; CHECK-NEXT: [[TMP3:%.*]] = sext i1 [[TMP2]] to i32 +; CHECK-NEXT: [[OP_RDX:%.*]] = and i32 [[TMP3]], [[LOAD_5]] +; CHECK-NEXT: ret i32 [[OP_RDX]] +; +entry: + %zext.0 = zext i8 1 to i32 + %zext.1 = zext i8 1 to i32 + %zext.2 = zext i8 1 to i32 + %zext.3 = zext i8 1 to i32 + %select.zext.0 = select i1 false, i32 -1, i32 %zext.0 + %select.zext.1 = select i1 false, i32 0, i32 %zext.1 + %select.zext.2 = select i1 false, i32 0, i32 %zext.2 + %select.zext.3 = select i1 false, i32 0, i32 %zext.3 + + %load.5 = load i32, ptr %1, align 4 + + %and.0 = and i32 %load.5, %select.zext.0 + %and.1 = and i32 %and.0, %select.zext.1 + %and.2 = and i32 %and.1, %select.zext.2 + %and.3 = and i32 %and.2, %select.zext.3 + + ret i32 %and.3 +} + |