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| author | Shilei Tian <i@tianshilei.me> | 2024-02-23 21:14:38 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-23 21:14:38 -0500 |
| commit | bfcf7a0707592ccc7fd9e805aeb36c4da3f315a6 (patch) | |
| tree | 85b933b2150a097977119130042b6a98db84a695 | |
| parent | de3b2c293b8bf336f8e1380148cf16b54a794c0c (diff) | |
| download | llvm-bfcf7a0707592ccc7fd9e805aeb36c4da3f315a6.zip llvm-bfcf7a0707592ccc7fd9e805aeb36c4da3f315a6.tar.gz llvm-bfcf7a0707592ccc7fd9e805aeb36c4da3f315a6.tar.bz2 | |
[AMDGPU] Remove `hasAtomicFaddRtnForTy` as it is not used anywhere (#82841)
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 12 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.h | 1 |
4 files changed, 0 insertions, 24 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp index 60b7813..a98d448 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp @@ -69,12 +69,3 @@ AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg, return std::pair(Reg, 0); } - -bool AMDGPU::hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, - const LLT &Ty) { - if (Ty == LLT::scalar(32)) - return Subtarget.hasAtomicFaddRtnInsts(); - if (Ty == LLT::fixed_vector(2, 16) || Ty == LLT::scalar(64)) - return Subtarget.hasGFX90AInsts(); - return false; -} diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h index 5ee888d..5972552 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h @@ -26,8 +26,6 @@ std::pair<Register, unsigned> getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg, GISelKnownBits *KnownBits = nullptr, bool CheckNUW = false); - -bool hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget, const LLT &Ty); } } diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index d8f528d8..84ef967 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5310,18 +5310,6 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter( } } -bool SITargetLowering::hasAtomicFaddRtnForTy(SDValue &Op) const { - switch (Op.getValue(0).getSimpleValueType().SimpleTy) { - case MVT::f32: - return Subtarget->hasAtomicFaddRtnInsts(); - case MVT::v2f16: - case MVT::f64: - return Subtarget->hasGFX90AInsts(); - default: - return false; - } -} - bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const { // This currently forces unfolding various combinations of fsub into fma with // free fneg'd operands. As long as we have fast FMA (controlled by diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index e436c23..f6e1d19 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -436,7 +436,6 @@ public: EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override; - bool hasAtomicFaddRtnForTy(SDValue &Op) const; bool enableAggressiveFMAFusion(EVT VT) const override; bool enableAggressiveFMAFusion(LLT Ty) const override; EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, |