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author | Tom Stellard <tstellar@redhat.com> | 2018-05-17 19:18:08 +0000 |
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committer | Tom Stellard <tstellar@redhat.com> | 2018-05-17 19:18:08 +0000 |
commit | 8af7f5b6e31e0cf2879dfa03798440b1b5798508 (patch) | |
tree | a192e2065e93cc1abbd3b73ff6cd5adddd1579f0 | |
parent | 489394b255be8808ff731e1608e1b7534dd6f1bd (diff) | |
download | llvm-8af7f5b6e31e0cf2879dfa03798440b1b5798508.zip llvm-8af7f5b6e31e0cf2879dfa03798440b1b5798508.tar.gz llvm-8af7f5b6e31e0cf2879dfa03798440b1b5798508.tar.bz2 |
Merging r323816:
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r323816 | evandro | 2018-01-30 13:14:11 -0800 (Tue, 30 Jan 2018) | 5 lines
[AArch64] Expand testing of zero cycle zeroing
Make sure that r321824 doesn't change zeroing.
Differential revision: https://reviews.llvm.org/D42089
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llvm-svn: 332651
-rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll | 63 |
1 files changed, 29 insertions, 34 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll index 2fb9d3b..3acb189 100644 --- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll +++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll @@ -1,27 +1,30 @@ -; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s -check-prefix=CYCLONE --check-prefix=ALL -; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=kryo < %s | FileCheck %s -check-prefix=KRYO --check-prefix=ALL -; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=falkor < %s | FileCheck %s -check-prefix=FALKOR --check-prefix=ALL +; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s -check-prefixes=ALL,CYCLONE +; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m1 < %s | FileCheck %s -check-prefixes=ALL,OTHERS +; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m3 < %s | FileCheck %s -check-prefixes=ALL,OTHERS +; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=kryo < %s | FileCheck %s -check-prefixes=ALL,OTHERS +; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=falkor < %s | FileCheck %s -check-prefixes=ALL,OTHERS ; rdar://11481771 ; rdar://13713797 +declare void @bar(half, float, double, <2 x double>) +declare void @bari(i32, i32) +declare void @barl(i64, i64) +declare void @barf(float, float) + define void @t1() nounwind ssp { entry: ; ALL-LABEL: t1: ; ALL-NOT: fmov -; CYCLONE: fmov d0, xzr -; CYCLONE: fmov d1, xzr +; CYCLONE: fmov h0, wzr +; CYCLONE: fmov s1, wzr ; CYCLONE: fmov d2, xzr -; CYCLONE: fmov d3, xzr -; KRYO: movi v0.2d, #0000000000000000 -; KRYO: movi v1.2d, #0000000000000000 -; KRYO: movi v2.2d, #0000000000000000 -; KRYO: movi v3.2d, #0000000000000000 -; FALKOR: movi v0.2d, #0000000000000000 -; FALKOR: movi v1.2d, #0000000000000000 -; FALKOR: movi v2.2d, #0000000000000000 -; FALKOR: movi v3.2d, #0000000000000000 - tail call void @bar(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00) nounwind +; CYCLONE: movi.16b v3, #0 +; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000 +; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000 +; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000 +; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000 + tail call void @bar(half 0.000000e+00, float 0.000000e+00, double 0.000000e+00, <2 x double> <double 0.000000e+00, double 0.000000e+00>) nounwind ret void } @@ -29,8 +32,8 @@ define void @t2() nounwind ssp { entry: ; ALL-LABEL: t2: ; ALL-NOT: mov w0, wzr -; ALL: mov w0, #0 -; ALL: mov w1, #0 +; ALL: mov w{{[0-3]+}}, #0 +; ALL: mov w{{[0-3]+}}, #0 tail call void @bari(i32 0, i32 0) nounwind ret void } @@ -39,8 +42,8 @@ define void @t3() nounwind ssp { entry: ; ALL-LABEL: t3: ; ALL-NOT: mov x0, xzr -; ALL: mov x0, #0 -; ALL: mov x1, #0 +; ALL: mov x{{[0-3]+}}, #0 +; ALL: mov x{{[0-3]+}}, #0 tail call void @barl(i64 0, i64 0) nounwind ret void } @@ -48,26 +51,19 @@ entry: define void @t4() nounwind ssp { ; ALL-LABEL: t4: ; ALL-NOT: fmov -; CYCLONE: fmov s0, wzr -; CYCLONE: fmov s1, wzr -; KRYO: movi v0.2d, #0000000000000000 -; KRYO: movi v1.2d, #0000000000000000 -; FALKOR: movi v0.2d, #0000000000000000 -; FALKOR: movi v1.2d, #0000000000000000 +; CYCLONE: fmov s{{[0-3]+}}, wzr +; CYCLONE: fmov s{{[0-3]+}}, wzr +; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000 +; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000 tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind ret void } -declare void @bar(double, double, double, double) -declare void @bari(i32, i32) -declare void @barl(i64, i64) -declare void @barf(float, float) - ; We used to produce spills+reloads for a Q register with zero cycle zeroing ; enabled. ; ALL-LABEL: foo: -; ALL-NOT: str {{q[0-9]+}} -; ALL-NOT: ldr {{q[0-9]+}} +; ALL-NOT: str q{{[0-9]+}} +; ALL-NOT: ldr q{{[0-9]+}} define double @foo(i32 %n) { entry: br label %for.body @@ -90,8 +86,7 @@ for.end: define <2 x i64> @t6() { ; ALL-LABEL: t6: ; CYCLONE: movi.16b v0, #0 -; KRYO: movi v0.2d, #0000000000000000 -; FALKOR: movi v0.2d, #0000000000000000 +; OTHERS: movi v0.2d, #0000000000000000 ret <2 x i64> zeroinitializer } |