diff options
author | Chandler Carruth <chandlerc@gmail.com> | 2018-05-22 03:03:11 +0000 |
---|---|---|
committer | Chandler Carruth <chandlerc@gmail.com> | 2018-05-22 03:03:11 +0000 |
commit | 7f374dc9a2ac5153733110ab78f1dbad6b6e5a47 (patch) | |
tree | 8aa489c727d1edba359eae4a0980cd3536836005 | |
parent | b0af7ced0f27e55e82524b508fe20193031fe9ec (diff) | |
download | llvm-7f374dc9a2ac5153733110ab78f1dbad6b6e5a47.zip llvm-7f374dc9a2ac5153733110ab78f1dbad6b6e5a47.tar.gz llvm-7f374dc9a2ac5153733110ab78f1dbad6b6e5a47.tar.bz2 |
Merge r330269 to fix egregiously bad codegeneration in the new EFLAGS lowering
that was defferred to a follow-up commit by me not understanding how part of
the x86 backend worked.
llvm-svn: 332939
-rw-r--r-- | llvm/lib/Target/X86/X86FlagsCopyLowering.cpp | 2 | ||||
-rw-r--r-- | llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll | 12 | ||||
-rw-r--r-- | llvm/test/CodeGen/X86/copy-eflags.ll | 16 | ||||
-rw-r--r-- | llvm/test/CodeGen/X86/flags-copy-lowering.mir | 20 | ||||
-rw-r--r-- | llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll | 10 | ||||
-rw-r--r-- | llvm/test/CodeGen/X86/win64_frame.ll | 2 | ||||
-rw-r--r-- | llvm/test/CodeGen/X86/x86-repmov-copy-eflags.ll | 2 |
7 files changed, 32 insertions, 32 deletions
diff --git a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp index 1fd1c70..9821eae 100644 --- a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp +++ b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp @@ -636,7 +636,7 @@ void X86FlagsCopyLoweringPass::insertTest(MachineBasicBlock &MBB, // also allow us to select a shorter encoding of `testb %reg, %reg` when that // would be equivalent. auto TestI = - BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8ri)).addReg(Reg).addImm(-1); + BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8rr)).addReg(Reg).addReg(Reg); (void)TestI; DEBUG(dbgs() << " test cond: "; TestI->dump()); ++NumTestsInserted; diff --git a/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll b/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll index 7786fb5..827aba7 100644 --- a/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll +++ b/llvm/test/CodeGen/X86/cmpxchg-clobber-flags.ll @@ -41,7 +41,7 @@ define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) nounwind { ; 32-GOOD-RA-NEXT: pushl %eax ; 32-GOOD-RA-NEXT: calll bar ; 32-GOOD-RA-NEXT: addl $16, %esp -; 32-GOOD-RA-NEXT: testb $-1, %bl +; 32-GOOD-RA-NEXT: testb %bl, %bl ; 32-GOOD-RA-NEXT: jne .LBB0_3 ; 32-GOOD-RA-NEXT: # %bb.1: # %t ; 32-GOOD-RA-NEXT: movl $42, %eax @@ -72,7 +72,7 @@ define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) nounwind { ; 32-FAST-RA-NEXT: pushl %eax ; 32-FAST-RA-NEXT: calll bar ; 32-FAST-RA-NEXT: addl $16, %esp -; 32-FAST-RA-NEXT: testb $-1, %bl +; 32-FAST-RA-NEXT: testb %bl, %bl ; 32-FAST-RA-NEXT: jne .LBB0_3 ; 32-FAST-RA-NEXT: # %bb.1: # %t ; 32-FAST-RA-NEXT: movl $42, %eax @@ -94,7 +94,7 @@ define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) nounwind { ; 64-ALL-NEXT: setne %bl ; 64-ALL-NEXT: movq %rax, %rdi ; 64-ALL-NEXT: callq bar -; 64-ALL-NEXT: testb $-1, %bl +; 64-ALL-NEXT: testb %bl, %bl ; 64-ALL-NEXT: jne .LBB0_2 ; 64-ALL-NEXT: # %bb.1: # %t ; 64-ALL-NEXT: movl $42, %eax @@ -219,7 +219,7 @@ define i32 @test_feed_cmov(i32* %addr, i32 %desired, i32 %new) nounwind { ; 32-GOOD-RA-NEXT: lock cmpxchgl %esi, (%ecx) ; 32-GOOD-RA-NEXT: sete %bl ; 32-GOOD-RA-NEXT: calll foo -; 32-GOOD-RA-NEXT: testb $-1, %bl +; 32-GOOD-RA-NEXT: testb %bl, %bl ; 32-GOOD-RA-NEXT: jne .LBB2_2 ; 32-GOOD-RA-NEXT: # %bb.1: # %entry ; 32-GOOD-RA-NEXT: movl %eax, %esi @@ -241,7 +241,7 @@ define i32 @test_feed_cmov(i32* %addr, i32 %desired, i32 %new) nounwind { ; 32-FAST-RA-NEXT: lock cmpxchgl %esi, (%ecx) ; 32-FAST-RA-NEXT: sete %bl ; 32-FAST-RA-NEXT: calll foo -; 32-FAST-RA-NEXT: testb $-1, %bl +; 32-FAST-RA-NEXT: testb %bl, %bl ; 32-FAST-RA-NEXT: jne .LBB2_2 ; 32-FAST-RA-NEXT: # %bb.1: # %entry ; 32-FAST-RA-NEXT: movl %eax, %esi @@ -262,7 +262,7 @@ define i32 @test_feed_cmov(i32* %addr, i32 %desired, i32 %new) nounwind { ; 64-ALL-NEXT: lock cmpxchgl %ebx, (%rdi) ; 64-ALL-NEXT: sete %bpl ; 64-ALL-NEXT: callq foo -; 64-ALL-NEXT: testb $-1, %bpl +; 64-ALL-NEXT: testb %bpl, %bpl ; 64-ALL-NEXT: cmovnel %ebx, %eax ; 64-ALL-NEXT: addq $8, %rsp ; 64-ALL-NEXT: popq %rbx diff --git a/llvm/test/CodeGen/X86/copy-eflags.ll b/llvm/test/CodeGen/X86/copy-eflags.ll index 9844799..bc601d1 100644 --- a/llvm/test/CodeGen/X86/copy-eflags.ll +++ b/llvm/test/CodeGen/X86/copy-eflags.ll @@ -30,7 +30,7 @@ define i32 @test1() nounwind { ; X32-NEXT: cmpb %cl, %ah ; X32-NEXT: sete d ; X32-NEXT: movb %ch, a -; X32-NEXT: testb $-1, %dl +; X32-NEXT: testb %dl, %dl ; X32-NEXT: jne .LBB0_2 ; X32-NEXT: # %bb.1: # %if.then ; X32-NEXT: movsbl %al, %eax @@ -55,7 +55,7 @@ define i32 @test1() nounwind { ; X64-NEXT: cmpb %dil, %cl ; X64-NEXT: sete {{.*}}(%rip) ; X64-NEXT: movb %dl, {{.*}}(%rip) -; X64-NEXT: testb $-1, %sil +; X64-NEXT: testb %sil, %sil ; X64-NEXT: jne .LBB0_2 ; X64-NEXT: # %bb.1: # %if.then ; X64-NEXT: pushq %rax @@ -101,7 +101,7 @@ define i32 @test2(i32* %ptr) nounwind { ; X32-NEXT: pushl $42 ; X32-NEXT: calll external ; X32-NEXT: addl $4, %esp -; X32-NEXT: testb $-1, %bl +; X32-NEXT: testb %bl, %bl ; X32-NEXT: je .LBB1_1 ; X32-NEXT: # %bb.2: # %else ; X32-NEXT: xorl %eax, %eax @@ -119,7 +119,7 @@ define i32 @test2(i32* %ptr) nounwind { ; X64-NEXT: setne %bl ; X64-NEXT: movl $42, %edi ; X64-NEXT: callq external -; X64-NEXT: testb $-1, %bl +; X64-NEXT: testb %bl, %bl ; X64-NEXT: je .LBB1_1 ; X64-NEXT: # %bb.2: # %else ; X64-NEXT: xorl %eax, %eax @@ -160,7 +160,7 @@ define void @test_tail_call(i32* %ptr) nounwind optsize { ; X32-NEXT: setne %al ; X32-NEXT: incb a ; X32-NEXT: sete d -; X32-NEXT: testb $-1, %al +; X32-NEXT: testb %al, %al ; X32-NEXT: jne external_b # TAILCALL ; X32-NEXT: # %bb.1: # %then ; X32-NEXT: jmp external_a # TAILCALL @@ -171,7 +171,7 @@ define void @test_tail_call(i32* %ptr) nounwind optsize { ; X64-NEXT: setne %al ; X64-NEXT: incb {{.*}}(%rip) ; X64-NEXT: sete {{.*}}(%rip) -; X64-NEXT: testb $-1, %al +; X64-NEXT: testb %al, %al ; X64-NEXT: jne external_b # TAILCALL ; X64-NEXT: # %bb.1: # %then ; X64-NEXT: jmp external_a # TAILCALL @@ -239,7 +239,7 @@ define void @PR37100(i8 %arg1, i16 %arg2, i64 %arg3, i8 %arg4, i8* %ptr1, i32* % ; X32-NEXT: setl %dl ; X32-NEXT: movzbl %dl, %ebp ; X32-NEXT: negl %ebp -; X32-NEXT: testb $-1, %al +; X32-NEXT: testb %al, %al ; X32-NEXT: jne .LBB3_3 ; X32-NEXT: # %bb.2: # %bb1 ; X32-NEXT: # in Loop: Header=BB3_1 Depth=1 @@ -248,7 +248,7 @@ define void @PR37100(i8 %arg1, i16 %arg2, i64 %arg3, i8 %arg4, i8* %ptr1, i32* % ; X32-NEXT: # in Loop: Header=BB3_1 Depth=1 ; X32-NEXT: movb %cl, (%ebx) ; X32-NEXT: movl (%edi), %edx -; X32-NEXT: testb $-1, %al +; X32-NEXT: testb %al, %al ; X32-NEXT: jne .LBB3_5 ; X32-NEXT: # %bb.4: # %bb1 ; X32-NEXT: # in Loop: Header=BB3_1 Depth=1 diff --git a/llvm/test/CodeGen/X86/flags-copy-lowering.mir b/llvm/test/CodeGen/X86/flags-copy-lowering.mir index d7fe0a8..f2834a1 100644 --- a/llvm/test/CodeGen/X86/flags-copy-lowering.mir +++ b/llvm/test/CodeGen/X86/flags-copy-lowering.mir @@ -97,13 +97,13 @@ body: | JMP_1 %bb.3 ; CHECK-NOT: %eflags = ; - ; CHECK: TEST8ri %[[A_REG]], -1, implicit-def %eflags + ; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def %eflags ; CHECK-NEXT: JNE_1 %bb.1, implicit killed %eflags ; CHECK-SAME: {{$[[:space:]]}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: {{.*$}} ; CHECK-SAME: {{$[[:space:]]}} - ; CHECK-NEXT: TEST8ri %[[B_REG]], -1, implicit-def %eflags + ; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def %eflags ; CHECK-NEXT: JNE_1 %bb.2, implicit killed %eflags ; CHECK-NEXT: JMP_1 %bb.3 @@ -152,13 +152,13 @@ body: | JB_1 %bb.3, implicit %eflags ; CHECK-NOT: %eflags = ; - ; CHECK: TEST8ri %[[A_REG]], -1, implicit-def %eflags + ; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def %eflags ; CHECK-NEXT: JNE_1 %bb.2, implicit killed %eflags ; CHECK-SAME: {{$[[:space:]]}} ; CHECK-NEXT: bb.4: ; CHECK-NEXT: successors: {{.*$}} ; CHECK-SAME: {{$[[:space:]]}} - ; CHECK-NEXT: TEST8ri %[[B_REG]], -1, implicit-def %eflags + ; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def %eflags ; CHECK-NEXT: JNE_1 %bb.3, implicit killed %eflags ; CHECK-SAME: {{$[[:space:]]}} ; CHECK-NEXT: bb.1: @@ -252,13 +252,13 @@ body: | %5:gr64 = CMOVE64rr %0, %1, implicit %eflags %6:gr64 = CMOVNE64rr %0, %1, implicit killed %eflags ; CHECK-NOT: %eflags = - ; CHECK: TEST8ri %[[A_REG]], -1, implicit-def %eflags + ; CHECK: TEST8rr %[[A_REG]], %[[A_REG]], implicit-def %eflags ; CHECK-NEXT: %3:gr64 = CMOVNE64rr %0, %1, implicit killed %eflags - ; CHECK-NEXT: TEST8ri %[[B_REG]], -1, implicit-def %eflags + ; CHECK-NEXT: TEST8rr %[[B_REG]], %[[B_REG]], implicit-def %eflags ; CHECK-NEXT: %4:gr64 = CMOVNE64rr %0, %1, implicit killed %eflags - ; CHECK-NEXT: TEST8ri %[[E_REG]], -1, implicit-def %eflags + ; CHECK-NEXT: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def %eflags ; CHECK-NEXT: %5:gr64 = CMOVNE64rr %0, %1, implicit killed %eflags - ; CHECK-NEXT: TEST8ri %[[E_REG]], -1, implicit-def %eflags + ; CHECK-NEXT: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def %eflags ; CHECK-NEXT: %6:gr64 = CMOVE64rr %0, %1, implicit killed %eflags MOV64mr %rsp, 1, %noreg, -16, %noreg, killed %3 MOV64mr %rsp, 1, %noreg, -16, %noreg, killed %4 @@ -364,7 +364,7 @@ body: | %5:gr64 = MOV64ri32 42 %6:gr64 = ADCX64rr %2, %5, implicit-def %eflags, implicit %eflags ; CHECK-NOT: %eflags = - ; CHECK: TEST8ri %[[E_REG]], -1, implicit-def %eflags + ; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def %eflags ; CHECK-NEXT: %4:gr64 = CMOVNE64rr %0, %1, implicit killed %eflags ; CHECK-NEXT: %5:gr64 = MOV64ri32 42 ; CHECK-NEXT: dead %{{[^:]*}}:gr8 = ADD8ri %[[CF_REG]], 255, implicit-def %eflags @@ -403,7 +403,7 @@ body: | %5:gr64 = MOV64ri32 42 %6:gr64 = ADOX64rr %2, %5, implicit-def %eflags, implicit %eflags ; CHECK-NOT: %eflags = - ; CHECK: TEST8ri %[[E_REG]], -1, implicit-def %eflags + ; CHECK: TEST8rr %[[E_REG]], %[[E_REG]], implicit-def %eflags ; CHECK-NEXT: %4:gr64 = CMOVNE64rr %0, %1, implicit killed %eflags ; CHECK-NEXT: %5:gr64 = MOV64ri32 42 ; CHECK-NEXT: dead %{{[^:]*}}:gr8 = ADD8ri %[[OF_REG]], 127, implicit-def %eflags diff --git a/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll b/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll index d011916..023de04 100644 --- a/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll +++ b/llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll @@ -221,7 +221,7 @@ define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) nounwind { ; CHECK32-NEXT: pushl %eax ; CHECK32-NEXT: calll bar ; CHECK32-NEXT: addl $16, %esp -; CHECK32-NEXT: testb $-1, %bl +; CHECK32-NEXT: testb %bl, %bl ; CHECK32-NEXT: jne .LBB4_3 ; CHECK32-NEXT: # %bb.1: # %t ; CHECK32-NEXT: movl $42, %eax @@ -243,7 +243,7 @@ define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) nounwind { ; CHECK64-NEXT: setne %bl ; CHECK64-NEXT: movq %rax, %rdi ; CHECK64-NEXT: callq bar -; CHECK64-NEXT: testb $-1, %bl +; CHECK64-NEXT: testb %bl, %bl ; CHECK64-NEXT: jne .LBB4_2 ; CHECK64-NEXT: # %bb.1: # %t ; CHECK64-NEXT: movl $42, %eax @@ -284,7 +284,7 @@ define i64 @test_two_live_flags(i64* %foo0, i64 %bar0, i64 %baz0, i64* %foo1, i6 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK32-NEXT: lock cmpxchg8b (%esi) -; CHECK32-NEXT: setne {{[0-9]+}}(%esp) # 1-byte Folded Spill +; CHECK32-NEXT: setne {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Spill ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK32-NEXT: movl %edi, %edx ; CHECK32-NEXT: movl %ebp, %ecx @@ -292,7 +292,7 @@ define i64 @test_two_live_flags(i64* %foo0, i64 %bar0, i64 %baz0, i64* %foo1, i6 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK32-NEXT: lock cmpxchg8b (%esi) ; CHECK32-NEXT: sete %al -; CHECK32-NEXT: testb $-1, {{[0-9]+}}(%esp) # 1-byte Folded Reload +; CHECK32-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload ; CHECK32-NEXT: jne .LBB5_4 ; CHECK32-NEXT: # %bb.1: # %entry ; CHECK32-NEXT: testb %al, %al @@ -319,7 +319,7 @@ define i64 @test_two_live_flags(i64* %foo0, i64 %bar0, i64 %baz0, i64* %foo1, i6 ; CHECK64-NEXT: movq %r8, %rax ; CHECK64-NEXT: lock cmpxchgq %r9, (%rcx) ; CHECK64-NEXT: sete %al -; CHECK64-NEXT: testb $-1, %dl +; CHECK64-NEXT: testb %dl, %dl ; CHECK64-NEXT: jne .LBB5_3 ; CHECK64-NEXT: # %bb.1: # %entry ; CHECK64-NEXT: testb %al, %al diff --git a/llvm/test/CodeGen/X86/win64_frame.ll b/llvm/test/CodeGen/X86/win64_frame.ll index 516bff3..c011b4d 100644 --- a/llvm/test/CodeGen/X86/win64_frame.ll +++ b/llvm/test/CodeGen/X86/win64_frame.ll @@ -239,7 +239,7 @@ define i64 @f10(i64* %foo, i64 %bar, i64 %baz) { ; ALL-NEXT: lock cmpxchgq %r8, (%rcx) ; ALL-NEXT: sete %bl ; ALL-NEXT: callq dummy -; ALL-NEXT: testb $-1, %bl +; ALL-NEXT: testb %bl, %bl ; ALL-NEXT: cmoveq %rsi, %rax ; ALL-NEXT: addq $40, %rsp ; ALL-NEXT: popq %rbx diff --git a/llvm/test/CodeGen/X86/x86-repmov-copy-eflags.ll b/llvm/test/CodeGen/X86/x86-repmov-copy-eflags.ll index a51f09e..1c168e8 100644 --- a/llvm/test/CodeGen/X86/x86-repmov-copy-eflags.ll +++ b/llvm/test/CodeGen/X86/x86-repmov-copy-eflags.ll @@ -43,7 +43,7 @@ declare void @g(%struct.T*) ; CHECK: pushl %esi ; CHECK: calll _g ; CHECK: addl $4, %esp -; CHECK: testb $-1, %[[NE_REG]] +; CHECK: testb %[[NE_REG]], %[[NE_REG]] ; CHECK: jne attributes #0 = { nounwind optsize } |