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| author | Tom Stellard <tstellar@redhat.com> | 2018-05-17 02:15:24 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2018-05-17 02:15:24 +0000 |
| commit | 2894a80397bbf9a024b9dec61ab116068635d96a (patch) | |
| tree | e0ffea509816e47372b7df9c31e38d71da2a66c6 | |
| parent | e473641e87c26d3675d23cd9afde1fa33a2334a6 (diff) | |
| download | llvm-2894a80397bbf9a024b9dec61ab116068635d96a.zip llvm-2894a80397bbf9a024b9dec61ab116068635d96a.tar.gz llvm-2894a80397bbf9a024b9dec61ab116068635d96a.tar.bz2 | |
Merging r329414:
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r329414 | ctopper | 2018-04-06 09:16:43 -0700 (Fri, 06 Apr 2018) | 3 lines
[X86] Merge itineraries for CLC, CMC, and STC.
These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation.
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llvm-svn: 332565
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86Schedule.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleAtom.td | 4 |
3 files changed, 5 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index a657b19..3a74a71 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -2119,13 +2119,13 @@ def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst), // Flag instructions let SchedRW = [WriteALU] in { -def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>; -def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>; +def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC_CMC_STC>; +def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_CLC_CMC_STC>; def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>; def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>; def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>; def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>; -def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>; +def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CLC_CMC_STC>; def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB; } diff --git a/llvm/lib/Target/X86/X86Schedule.td b/llvm/lib/Target/X86/X86Schedule.td index 2e21a97..078d459 100644 --- a/llvm/lib/Target/X86/X86Schedule.td +++ b/llvm/lib/Target/X86/X86Schedule.td @@ -608,12 +608,10 @@ def IIC_CMPXCHG_8B : InstrItinClass; def IIC_CMPXCHG_16B : InstrItinClass; def IIC_LODS : InstrItinClass; def IIC_OUTS : InstrItinClass; -def IIC_CLC : InstrItinClass; +def IIC_CLC_CMC_STC : InstrItinClass; def IIC_CLD : InstrItinClass; def IIC_CLI : InstrItinClass; -def IIC_CMC : InstrItinClass; def IIC_CLTS : InstrItinClass; -def IIC_STC : InstrItinClass; def IIC_STI : InstrItinClass; def IIC_STD : InstrItinClass; def IIC_XLAT : InstrItinClass; diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td index e052ad9..460b982 100644 --- a/llvm/lib/Target/X86/X86ScheduleAtom.td +++ b/llvm/lib/Target/X86/X86ScheduleAtom.td @@ -514,12 +514,10 @@ def AtomItineraries : ProcessorItineraries< InstrItinData<IIC_CMPXCHG_16B, [InstrStage<22, [Port0, Port1]>] >, InstrItinData<IIC_LODS, [InstrStage<2, [Port0, Port1]>] >, InstrItinData<IIC_OUTS, [InstrStage<74, [Port0, Port1]>] >, - InstrItinData<IIC_CLC, [InstrStage<1, [Port0, Port1]>] >, + InstrItinData<IIC_CLC_CMC_STC, [InstrStage<1, [Port0, Port1]>] >, InstrItinData<IIC_CLD, [InstrStage<3, [Port0, Port1]>] >, InstrItinData<IIC_CLI, [InstrStage<14, [Port0, Port1]>] >, - InstrItinData<IIC_CMC, [InstrStage<1, [Port0, Port1]>] >, InstrItinData<IIC_CLTS, [InstrStage<33, [Port0, Port1]>] >, - InstrItinData<IIC_STC, [InstrStage<1, [Port0, Port1]>] >, InstrItinData<IIC_STI, [InstrStage<17, [Port0, Port1]>] >, InstrItinData<IIC_STD, [InstrStage<21, [Port0, Port1]>] >, InstrItinData<IIC_XLAT, [InstrStage<6, [Port0, Port1]>] >, |