diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2016-06-03 20:48:40 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-06-03 20:48:40 +0000 |
| commit | 94b2adcf9082dedf9332b29ac94929c6bd3a0ce4 (patch) | |
| tree | 39ed0c796d536608270f444ce6e36bd8a39fad86 | |
| parent | 6b46e17b615d32daf7f1e1ea7a02f76690614679 (diff) | |
| download | llvm-94b2adcf9082dedf9332b29ac94929c6bd3a0ce4.zip llvm-94b2adcf9082dedf9332b29ac94929c6bd3a0ce4.tar.gz llvm-94b2adcf9082dedf9332b29ac94929c6bd3a0ce4.tar.bz2 | |
Merging r266152:
------------------------------------------------------------------------
r266152 | thomas.stellard | 2016-04-12 16:57:30 -0700 (Tue, 12 Apr 2016) | 13 lines
AMDGPU/SI: Fix spilling of 96-bit registers
Summary:
It seems like this was broken in r252327. I thought we had test cases
for this, but it's really hard to tirgger spills of this exact register
size since they aren't used very much.
Reviewers: arsenm, nhaehnle
Subscribers: nhaehnle, arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D19021
------------------------------------------------------------------------
llvm-svn: 271735
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 828dd72..b531f91 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -525,6 +525,8 @@ static unsigned getVGPRSpillSaveOpcode(unsigned Size) { return AMDGPU::SI_SPILL_V32_SAVE; case 8: return AMDGPU::SI_SPILL_V64_SAVE; + case 12: + return AMDGPU::SI_SPILL_V96_SAVE; case 16: return AMDGPU::SI_SPILL_V128_SAVE; case 32: @@ -616,6 +618,8 @@ static unsigned getVGPRSpillRestoreOpcode(unsigned Size) { return AMDGPU::SI_SPILL_V32_RESTORE; case 8: return AMDGPU::SI_SPILL_V64_RESTORE; + case 12: + return AMDGPU::SI_SPILL_V96_RESTORE; case 16: return AMDGPU::SI_SPILL_V128_RESTORE; case 32: |