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| author | John Criswell <criswell@uiuc.edu> | 2005-11-02 19:38:00 +0000 |
|---|---|---|
| committer | John Criswell <criswell@uiuc.edu> | 2005-11-02 19:38:00 +0000 |
| commit | 072467d8a9b0300017327fec9e65d8adf049fe0b (patch) | |
| tree | e3834460194382c90de2b04522e70b68517257c2 | |
| parent | 39a12ac598c9b44d9e5c99b8f1e54a2d7c97371f (diff) | |
| download | llvm-072467d8a9b0300017327fec9e65d8adf049fe0b.zip llvm-072467d8a9b0300017327fec9e65d8adf049fe0b.tar.gz llvm-072467d8a9b0300017327fec9e65d8adf049fe0b.tar.bz2 | |
Merged in revision 1.60.
llvm-svn: 24160
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 048737f..a58d9ce 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -963,14 +963,14 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { DAG.getConstant(N1C->getValue()&N01C->getValue(), VT)); } // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) - if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { + if (N1C && N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { unsigned ExtendBits = MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT()); - if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0) + if (ExtendBits == 64 || (N1C->getValue() & (~0ULL << ExtendBits) == 0)) return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1); } // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF - if (N0.getOpcode() == ISD::OR && N1C) + if (N1C && N0.getOpcode() == ISD::OR) if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) return N1; @@ -1031,7 +1031,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); } // fold (and (sra)) -> (and (srl)) when possible. - if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) + if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) { if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { // If the RHS of the AND has zeros where the sign bits of the SRA will // land, turn the SRA into an SRL. @@ -1043,7 +1043,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { return SDOperand(); } } - + } // fold (zext_inreg (extload x)) -> (zextload x) if (N0.getOpcode() == ISD::EXTLOAD) { MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); |