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| author | Yingwei Zheng <dtcxzyw2333@gmail.com> | 2024-02-06 01:29:38 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-06 01:29:38 +0800 |
| commit | cb8d83a77c25e529f58eba17bb1ec76069a04e90 (patch) | |
| tree | 4d0adcffd94f829d70b75114de29dd1aa3acacbf | |
| parent | 8f4d8945536e9fc45db0e349b91c2f4b3a9cae29 (diff) | |
| download | llvm-cb8d83a77c25e529f58eba17bb1ec76069a04e90.zip llvm-cb8d83a77c25e529f58eba17bb1ec76069a04e90.tar.gz llvm-cb8d83a77c25e529f58eba17bb1ec76069a04e90.tar.bz2 | |
[InstCombine] Fix assertion failure in issue80597 (#80614)
The assertion in #80597 failed when we were trying to compute known bits
of a value in an unreachable BB.
https://github.com/llvm/llvm-project/blob/859b09da08c2a47026ba0a7d2f21b7dca705864d/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp#L749-L810
In this case, `SignBits` is 30 (deduced from instr info), but `Known` is
`10000101010111010011110101000?0?00000000000000000000000000000000`
(deduced from dom cond). Setting high bits of `lshr Known, 1` will lead
to conflict.
This patch masks out high bits of `Known.Zero` to address this problem.
Fixes #80597.
| -rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp | 3 | ||||
| -rw-r--r-- | llvm/test/Transforms/InstCombine/pr80597.ll | 33 |
2 files changed, 36 insertions, 0 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index a8a5f98..79873a9 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -802,6 +802,9 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, return InsertNewInstWith(LShr, I->getIterator()); } else if (Known.One[BitWidth-ShiftAmt-1]) { // New bits are known one. Known.One |= HighBits; + // SignBits may be out-of-sync with Known.countMinSignBits(). Mask out + // high bits of Known.Zero to avoid conflicts. + Known.Zero &= ~HighBits; } } else { computeKnownBits(I, Known, Depth, CxtI); diff --git a/llvm/test/Transforms/InstCombine/pr80597.ll b/llvm/test/Transforms/InstCombine/pr80597.ll new file mode 100644 index 0000000..5feae4a --- /dev/null +++ b/llvm/test/Transforms/InstCombine/pr80597.ll @@ -0,0 +1,33 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S -passes=instcombine < %s | FileCheck %s + +define i64 @pr80597(i1 %cond) { +; CHECK-LABEL: define i64 @pr80597( +; CHECK-SAME: i1 [[COND:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ADD:%.*]] = select i1 [[COND]], i64 0, i64 -12884901888 +; CHECK-NEXT: [[SEXT1:%.*]] = add nsw i64 [[ADD]], 8836839514384105472 +; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[SEXT1]], -34359738368 +; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]] +; CHECK: if.else: +; CHECK-NEXT: [[SEXT2:%.*]] = ashr exact i64 [[ADD]], 1 +; CHECK-NEXT: [[ASHR:%.*]] = or i64 [[SEXT2]], 4418419761487020032 +; CHECK-NEXT: ret i64 [[ASHR]] +; CHECK: if.then: +; CHECK-NEXT: ret i64 0 +; +entry: + %add = select i1 %cond, i64 0, i64 4294967293 + %add8 = shl i64 %add, 32 + %sext1 = add i64 %add8, 8836839514384105472 + %cmp = icmp ult i64 %sext1, -34359738368 + br i1 %cmp, label %if.then, label %if.else + +if.else: + %sext2 = or i64 %add8, 8836839522974040064 + %ashr = ashr i64 %sext2, 1 + ret i64 %ashr + +if.then: + ret i64 0 +} |