[RISCV] Add IMinMax sched resources to P600SchedModel

CI checks were passing in #84962 (c48d8182f172ac24244d5fb038b7ab983f67def4) but
that commit caused failures once merged due to ships passing since the
PR was not rebased on #85131. This commit fixes this problem by adding
sched resources for integer min max instructions from Zbb in P600 model.

1 files changed, 2 insertions, 0 deletions

diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index 5222a885..5401695 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -161,6 +161,7 @@ def : WriteRes<WriteCTZ, [SiFiveP600IntArith]>;
 def : WriteRes<WriteCTZ32, [SiFiveP600IntArith]>;
 
 def : WriteRes<WriteORCB, [SiFiveP600IntArith]>;
+def : WriteRes<WriteIMinMax, [SiFiveP600IntArith]>;
 
 def : WriteRes<WriteREV8, [SiFiveP600IntArith]>;
 
@@ -832,6 +833,7 @@ def : ReadAdvance<ReadCTZ32, 0>;
 def : ReadAdvance<ReadCPOP, 0>;
 def : ReadAdvance<ReadCPOP32, 0>;
 def : ReadAdvance<ReadORCB, 0>;
+def : ReadAdvance<ReadIMinMax, 0>;
 def : ReadAdvance<ReadREV8, 0>;
 def : ReadAdvance<ReadSHXADD, 0>;
 def : ReadAdvance<ReadSHXADD32, 0>;