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authorKai Nacke <kai@redstar.de>2022-06-05 16:21:52 -0400
committerKai Nacke <kai@redstar.de>2022-11-13 11:07:24 -0500
commitd5016d370d3b04860f8236f3c5f04d37bdc2c182 (patch)
treebba7e87de0d242af26b8db0ed15213c5fab49fa4
parent668db0e865814879824201b0345b9bafed386e81 (diff)
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[m88k] Fixes for register pairs.
- Copy cost is now 2, because 2 instruction are required. - Printing a register pair as operand now uses the hi register.
-rw-r--r--llvm/lib/Target/M88k/M88kAsmPrinter.cpp3
-rw-r--r--llvm/lib/Target/M88k/M88kMCInstLower.cpp20
-rw-r--r--llvm/lib/Target/M88k/M88kMCInstLower.h5
-rw-r--r--llvm/lib/Target/M88k/M88kRegisterInfo.td5
4 files changed, 24 insertions, 9 deletions
diff --git a/llvm/lib/Target/M88k/M88kAsmPrinter.cpp b/llvm/lib/Target/M88k/M88kAsmPrinter.cpp
index c8772f1..c3a57d0 100644
--- a/llvm/lib/Target/M88k/M88kAsmPrinter.cpp
+++ b/llvm/lib/Target/M88k/M88kAsmPrinter.cpp
@@ -67,7 +67,8 @@ bool M88kAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
if (ExtraCode)
return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
M88kMCInstLower Lower(MF->getContext(), *this);
- MCOperand MO(Lower.lowerOperand(MI->getOperand(OpNo)));
+ MCOperand MO(Lower.lowerOperand(MI->getOperand(OpNo),
+ MF->getSubtarget().getRegisterInfo()));
M88kInstPrinter::printOperand(MO, MAI, OS);
return false;
}
diff --git a/llvm/lib/Target/M88k/M88kMCInstLower.cpp b/llvm/lib/Target/M88k/M88kMCInstLower.cpp
index b4e5fa0d..e9b1bcef 100644
--- a/llvm/lib/Target/M88k/M88kMCInstLower.cpp
+++ b/llvm/lib/Target/M88k/M88kMCInstLower.cpp
@@ -7,11 +7,14 @@
//===----------------------------------------------------------------------===//
#include "M88kMCInstLower.h"
+#include "M88kRegisterInfo.h"
#include "MCTargetDesc/M88kBaseInfo.h"
#include "MCTargetDesc/M88kMCExpr.h"
+#include "MCTargetDesc/M88kMCTargetDesc.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Mangler.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
@@ -83,10 +86,17 @@ MCOperand M88kMCInstLower::lowerSymbolOperand(const MachineOperand &MO) const {
return MCOperand::createExpr(Expr);
}
-MCOperand M88kMCInstLower::lowerOperand(const MachineOperand &MO) const {
+MCOperand M88kMCInstLower::lowerOperand(const MachineOperand &MO, const TargetRegisterInfo *TRI) const {
switch (MO.getType()) {
- case MachineOperand::MO_Register:
- return MCOperand::createReg(MO.getReg());
+ case MachineOperand::MO_Register: {
+ // HACK: If a register pair is used then replace register with the hi part.
+ Register Reg = MO.getReg();
+ assert(Register::isPhysicalRegister(Reg));
+ assert(!MO.getSubReg() && "Subregs should be eliminated!");
+ if(M88k::GPR64RCRegClass.contains(Reg))
+ Reg = TRI->getSubReg(Reg, M88k::sub_hi);
+ return MCOperand::createReg(Reg);
+ }
case MachineOperand::MO_Immediate:
return MCOperand::createImm(MO.getImm());
@@ -105,11 +115,13 @@ MCOperand M88kMCInstLower::lowerOperand(const MachineOperand &MO) const {
}
void M88kMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
+ const MachineFunction &MF = *MI->getParent()->getParent();
+ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
OutMI.setOpcode(MI->getOpcode());
for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
const MachineOperand &MO = MI->getOperand(I);
// Ignore all implicit register operands, and register masks.
if ((!MO.isReg() || !MO.isImplicit()) && !MO.isRegMask())
- OutMI.addOperand(lowerOperand(MO));
+ OutMI.addOperand(lowerOperand(MO, TRI));
}
}
diff --git a/llvm/lib/Target/M88k/M88kMCInstLower.h b/llvm/lib/Target/M88k/M88kMCInstLower.h
index ab6fba2..048fb2f 100644
--- a/llvm/lib/Target/M88k/M88kMCInstLower.h
+++ b/llvm/lib/Target/M88k/M88kMCInstLower.h
@@ -19,7 +19,7 @@ class MCInst;
class MCOperand;
class MachineInstr;
class MachineOperand;
-class Mangler;
+class TargetRegisterInfo;
class LLVM_LIBRARY_VISIBILITY M88kMCInstLower {
MCContext &Ctx;
@@ -32,7 +32,8 @@ public:
void lower(const MachineInstr *MI, MCInst &OutMI) const;
// Return an MCOperand for MO.
- MCOperand lowerOperand(const MachineOperand &MO) const;
+ MCOperand lowerOperand(const MachineOperand &MO,
+ const TargetRegisterInfo *TRI) const;
private:
// Return an MCOperand for symbolic operand MO.
diff --git a/llvm/lib/Target/M88k/M88kRegisterInfo.td b/llvm/lib/Target/M88k/M88kRegisterInfo.td
index 1362a7d..4f37d54 100644
--- a/llvm/lib/Target/M88k/M88kRegisterInfo.td
+++ b/llvm/lib/Target/M88k/M88kRegisterInfo.td
@@ -25,10 +25,11 @@ class M88kRegWithSubregs<string n, list<Register> subregs>
// Multiclass to define RegisterClass and RegisterOperand together.
multiclass M88kRegisterClass<list<ValueType> types, int size, int alignment,
- dag regList, bit allocatable = 1> {
+ dag regList, bit allocatable = 1, int copycost = 1> {
let isAllocatable = allocatable in
def RC : RegisterClass<"M88k", types, alignment, regList> {
let Size = size;
+ let CopyCost = copycost;
}
def "" : RegisterOperand<!cast<RegisterClass>(NAME#"RC")> {
let DecoderMethod = "decode"#NAME#"RegisterClass";
@@ -64,7 +65,7 @@ def GRPair : RegisterTuples<[sub_hi, sub_lo],
[(add (sequence "R%u", 0, 30, 2)),
(add (sequence "R%u", 1, 31, 2))]>;
-defm GPR64 : M88kRegisterClass<[i64, f64], 64, 32, (add GRPair)>;
+defm GPR64 : M88kRegisterClass<[i64, f64], 64, 32, (add GRPair), 1, 2>;
//defm GPR64 : M88kRegisterClass<[i64, f64], 64, 32,
// (add R0_R1, R2_R3, R4_R5, R6_R7, R8_R9,