[m88k] Removed dead combiner code.

2 files changed, 0 insertions, 154 deletions

diff --git a/llvm/lib/Target/M88k/GISel/M88kPostLegalizerCombiner.cpp b/llvm/lib/Target/M88k/GISel/M88kPostLegalizerCombiner.cpp
index 8034513..adb63b19 100644
--- a/llvm/lib/Target/M88k/GISel/M88kPostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/M88k/GISel/M88kPostLegalizerCombiner.cpp
@@ -41,138 +41,6 @@
 using namespace llvm;
 using namespace MIPatternMatch;
 
-/*
-C Expressions to match:
-
-  a + (b == 0)
-  a + (b >= c) (unsigned)
-  a + (b <= c) (unsigned)
-  a - (b < c) (unsigned)
-  a - (b > c) (unsigned)
-  a - (b != 0)
-  a - (b >= 0) (signed)
-
-Match:
-
-    %2:gr(s32) = G_CONSTANT i32 0
-    %3:gr(s1) = G_ICMP intpred(eq), %0(s32), %2
-    %4:gr(s32) = G_ZEXT %3(s1)
-    %5:gr(s32) = nsw G_ADD %4, %1
-=>
-    %2:gr(s32) = G_CONSTANT i32 0
-               = G_USUBO %2, %0(s32)
-               = G_UADDE
-        subu.co  %r0,%r0,%r2
-        addu.ci  %r4,%r3,%r0
-
-    %2:gr(s32) = G_CONSTANT i32 0
-    %3:gr(s1) = G_ICMP intpred(ne), %1(s32), %2
-    %4:gr(s32) = G_SEXT %3(s1)
-    %5:gr(s32) = G_ADD %4, %0
-=>
-       subu.co  %r0,%r0,%r3
-        subu.ci  %r2,%r2,%r0
-*/
-
-// Match G_ADD ...
-bool matchAddCmpToSubAdd(MachineInstr &MI, MachineRegisterInfo &MRI,
-                         std::tuple<Register, Register, Register> &MatchInfo) {
-  assert(MI.getOpcode() == TargetOpcode::G_ADD);
-
-  Register SrcRegA;
-  Register SrcRegB;
-  Optional<ValueAndVReg> CstValReg;
-  CmpInst::Predicate Pred;
-  if (!mi_match(
-          MI, MRI,
-          m_GAdd(m_Reg(SrcRegA), m_GZExt(m_GICmp(m_Pred(Pred), m_Reg(SrcRegB),
-                                                 m_GCst(CstValReg))))))
-    return false;
-
-  if (Pred != CmpInst::ICMP_EQ || !CstValReg || CstValReg->Value != 0)
-    return false;
-
-  MatchInfo = std::make_tuple(SrcRegA, SrcRegB, CstValReg->VReg);
-
-  return true;
-}
-
-// Lower to ...
-bool applyAddCmpToSubAdd(MachineInstr &MI, MachineRegisterInfo &MRI,
-                         std::tuple<Register, Register, Register> &MatchInfo) {
-  assert(MI.getOpcode() == TargetOpcode::G_ADD);
-
-  Register DstReg = MI.getOperand(0).getReg();
-  Register SrcRegA;
-  Register SrcRegB;
-  Register ZeroReg;
-  std::tie(SrcRegA, SrcRegB, ZeroReg) = MatchInfo;
-
-  MachineIRBuilder B(MI);
-  Register Carry = MRI.createGenericVirtualRegister(LLT::scalar(1));
-  Register UnusedReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
-  Register UnusedCarry = MRI.createGenericVirtualRegister(LLT::scalar(1));
-
-  B.buildInstr(TargetOpcode::G_USUBO, {UnusedReg, Carry}, {ZeroReg, SrcRegB});
-  B.buildInstr(TargetOpcode::G_UADDE, {DstReg, UnusedCarry},
-               {SrcRegA, ZeroReg, Carry});
-  MI.eraseFromParent();
-  return true;
-}
-
-bool matchAddCmpToSubAdd2(MachineInstr &MI, MachineOperand &Src1,
-                          MachineOperand &Src2, MachineOperand &Src3,
-                          MachineOperand &CC, MachineRegisterInfo &MRI,
-                          BuildFnTy &MatchInfo) {
-  assert(MI.getOpcode() == TargetOpcode::G_ADD);
-  Register DstReg = MI.getOperand(0).getReg();
-  Register SrcRegA = Src1.getReg();
-  Register SrcRegB;
-  Register SrcRegC;
-  Register ZeroReg;
-  CmpInst::Predicate Pred = static_cast<CmpInst::Predicate>(CC.getPredicate());
-  switch (Pred) {
-  case CmpInst::ICMP_UGE:
-    SrcRegB = Src3.getReg();
-    SrcRegC = Src2.getReg();
-    ZeroReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
-    break;
-  case CmpInst::ICMP_ULE:
-    SrcRegB = Src2.getReg();
-    SrcRegC = Src3.getReg();
-    ZeroReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
-    break;
-  case CmpInst::ICMP_EQ: {
-    int64_t Cst;
-    if (mi_match(Src2.getReg(), MRI, m_ICst(Cst)) && Cst == 0) {
-      SrcRegB = ZeroReg = Src2.getReg();
-      SrcRegC = Src3.getReg();
-    } else if (mi_match(Src3.getReg(), MRI, m_ICst(Cst)) && Cst == 0) {
-      SrcRegB = ZeroReg = Src3.getReg();
-      SrcRegC = Src2.getReg();
-    } else
-      return false;
-    break;
-  }
-  default:
-    return false;
-  }
-
-  Register Carry = MRI.createGenericVirtualRegister(LLT::scalar(1));
-  Register UnusedReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
-  Register UnusedCarry = MRI.createGenericVirtualRegister(LLT::scalar(1));
-
-  MatchInfo = [=](MachineIRBuilder &B) {
-    if (Pred != CmpInst::ICMP_EQ)
-      B.buildConstant(ZeroReg, 0);
-    B.buildInstr(TargetOpcode::G_USUBO, {UnusedReg, Carry}, {SrcRegB, SrcRegC});
-    B.buildInstr(TargetOpcode::G_UADDE, {DstReg, UnusedCarry},
-                 {SrcRegA, ZeroReg, Carry});
-  };
-
-  return true;
-}
-
 // Match
 //  Dst = G_ADD SrcA, (G_ZEXT (G_ICMP Pred, SrcB, SrcC)
 // with:
diff --git a/llvm/lib/Target/M88k/M88kCombine.td b/llvm/lib/Target/M88k/M88kCombine.td
index 9453c3a..c2d4456 100644
--- a/llvm/lib/Target/M88k/M88kCombine.td
+++ b/llvm/lib/Target/M88k/M88kCombine.td
@@ -55,28 +55,6 @@ def M88kPreLegalizerCombinerHelper: GICombinerHelper<
 }
 
 // Combine
-//   G_ADD $dst, (G_ZEXT (G_ICMP eq, $src, 0))
-// into
-//   G_UADDE $dst, (G_USUBO 0, %src)
-// under certain restrictions.
-def subadd_from_icmpadd_matchdata : GIDefMatchData<"std::tuple<Register, Register, Register>">;
-def subadd_from_icmpadd1 : GICombineRule<
-  (defs root:$root, subadd_from_icmpadd_matchdata:$matchinfo),
-  (match (wip_match_opcode G_ADD):$root,
-         [{ return matchAddCmpToSubAdd(*${root}, MRI,
-                                                   ${matchinfo}); }]),
-  (apply [{ applyAddCmpToSubAdd(*${root}, MRI, ${matchinfo}); }])>;
-
-def subadd_from_icmpadd2 : GICombineRule<
-  (defs root:$dst, build_fn_matchinfo:$matchinfo),
-  (match (G_ICMP $icmp, $cc, $src2, $src3),
-         (G_ZEXT $zext, $icmp),
-         (G_ADD $dst, $zext, $src1):$mi,
-         [{ return matchAddCmpToSubAdd2(*${mi}, ${src1}, ${src2}, ${src3}, ${cc}, MRI,
-                                                   ${matchinfo}); }]),
-  (apply [{ Helper.applyBuildFn(*${mi}, ${matchinfo}); }])>;
-
-// Combine
 //  Dst = G_ADD SrcA, (G_ZEXT (G_ICMP Pred, SrcB, SrcC)
 // with:
 //  - Pred = unsigned >=