diff options
author | Kai Nacke <kai@redstar.de> | 2022-08-13 12:43:01 -0400 |
---|---|---|
committer | Kai Nacke <kai@redstar.de> | 2022-11-13 11:07:45 -0500 |
commit | b9172dc551bb65d92be71b392c33ef24c811ac7b (patch) | |
tree | a88eead72c3755ab5aa1eee150212792422f937f | |
parent | 23736b1ee0f52a24872693f64da6124fac6100eb (diff) | |
download | llvm-b9172dc551bb65d92be71b392c33ef24c811ac7b.zip llvm-b9172dc551bb65d92be71b392c33ef24c811ac7b.tar.gz llvm-b9172dc551bb65d92be71b392c33ef24c811ac7b.tar.bz2 |
[m88k] Split bitfield operand into width and offset
This solves issue #15.
-rw-r--r-- | llvm/lib/Target/M88k/AsmParser/M88kAsmParser.cpp | 84 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/Disassembler/M88kDisassembler.cpp | 15 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp | 38 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/GISel/M88kPostLegalizerLowering.cpp | 3 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/M88k.td | 1 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/M88kInstrFormats.td | 14 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/M88kInstrInfo.td | 63 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/MCTargetDesc/M88kBaseInfo.h | 1 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/MCTargetDesc/M88kInstPrinter.cpp | 23 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/MCTargetDesc/M88kInstPrinter.h | 4 |
10 files changed, 80 insertions, 166 deletions
diff --git a/llvm/lib/Target/M88k/AsmParser/M88kAsmParser.cpp b/llvm/lib/Target/M88k/AsmParser/M88kAsmParser.cpp index 4da75e9..5bdc931 100644 --- a/llvm/lib/Target/M88k/AsmParser/M88kAsmParser.cpp +++ b/llvm/lib/Target/M88k/AsmParser/M88kAsmParser.cpp @@ -157,11 +157,6 @@ public: addExpr(Inst, getImm()); } - void addBitFieldOperands(MCInst &Inst, unsigned N) const { - assert(N == 1 && "Invalid number of operands"); - addExpr(Inst, getImm()); - } - void addBFWidthOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands"); addExpr(Inst, getImm()); @@ -183,13 +178,10 @@ public: } bool isU5Imm() const { return isImm(0, 31); } - // TODO - bool isU5ImmO() const { return isImm(0, 31); } bool isU16Imm() const { return isImm(0, 65535); } bool isS16Imm() const { return isImm(-32768, 32767); } bool isVec9() const { return isImm(0, 511); } - bool isBitField() const { return isImm(0, 1023); } bool isBFWidth() const { return isImm(0, 31); } bool isBFOffset() const { return isImm(0, 31); } bool isPixelRot() const { return isImm(0, 60); } @@ -238,7 +230,6 @@ class M88kAsmParser : public MCTargetAsmParser { bool parseOperand(OperandVector &Operands, StringRef Mnemonic); bool parseScaledRegister(OperandVector &Operands); - OperandMatchResultTy parseBitField(OperandVector &Operands); OperandMatchResultTy parseBFWidth(OperandVector &Operands); OperandMatchResultTy parseBFOffset(OperandVector &Operands); OperandMatchResultTy parsePixelRot(OperandVector &Operands); @@ -373,8 +364,18 @@ bool M88kAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, // Read the third operand or a scaled register. if (getLexer().is(AsmToken::Comma)) { Parser.Lex(); + if (getLexer().is(AsmToken::Less) && Name == "rot") + Operands.push_back(M88kOperand::createToken("<", Parser.getTok().getLoc())); + if (parseOperand(Operands, Name)) { - return Error(getLexer().getLoc(), "expected operand"); + return Error(getLexer().getLoc(), "expected register or immediate"); + } + // Parse bitfield width + if (getLexer().is(AsmToken::Less)) { + Operands.push_back(M88kOperand::createToken("<", Parser.getTok().getLoc())); + if (parseOperand(Operands, Name)) { + return Error(getLexer().getLoc(), "expected bitfield offset"); + } } } else if (getLexer().is(AsmToken::LBrac)) { if (parseScaledRegister(Operands)) @@ -395,8 +396,9 @@ bool M88kAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { // Invoke a custom associated parser. OperandMatchResultTy Result = MatchOperandParserImpl(Operands, Mnemonic); - if (Result == MatchOperand_Success) + if (Result == MatchOperand_Success) { return Result; + } if (Result == MatchOperand_ParseFail) { Parser.eatToEndOfStatement(); return Result; @@ -427,63 +429,36 @@ bool M88kAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { return true; } -OperandMatchResultTy M88kAsmParser::parseBitField(OperandVector &Operands) { - // Parses operands like 5<6> and <7>. - MCContext &Ctx = getContext(); - SMLoc StartLoc = Parser.getTok().getLoc(); - Optional<AsmToken> WidthTok; - int64_t Width = 0, Offset; - if (Lexer.is(AsmToken::Integer)) { - WidthTok = Parser.getTok(); - Width = Parser.getTok().getIntVal(); - Parser.Lex(); - } - if (Lexer.isNot(AsmToken::Less)) { - if (WidthTok) - Lexer.UnLex(WidthTok.value()); - return MatchOperand_NoMatch; - } - Parser.Lex(); - if (Lexer.isNot(AsmToken::Integer)) - return MatchOperand_ParseFail; - Offset = Parser.getTok().getIntVal(); - Parser.Lex(); - if (Lexer.isNot(AsmToken::Greater)) - return MatchOperand_ParseFail; - Parser.Lex(); - - // TODO Check values. - int64_t Val = Width << 5 | Offset; - const MCExpr *Expr = MCConstantExpr::create(Val, Ctx); - SMLoc EndLoc = - SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - Operands.push_back(M88kOperand::createImm(Expr, StartLoc, EndLoc)); - - // Announce match. - return MatchOperand_Success; -} - OperandMatchResultTy M88kAsmParser::parseBFWidth(OperandVector &Operands) { - // Parses an immediate. Can be empty, but must be followed by <O>. + // Parses the width of a bitfield. If empty and followed by <O>, then it is 0. + // If not followed by <O>, then it is the offset, and the width is 0. MCContext &Ctx = getContext(); SMLoc StartLoc = Parser.getTok().getLoc(); Optional<AsmToken> WidthTok; int64_t Width = 0; + bool IsReallyOffset = false; if (Lexer.is(AsmToken::Integer)) { WidthTok = Parser.getTok(); Width = Parser.getTok().getIntVal(); Parser.Lex(); } if (Lexer.isNot(AsmToken::Less)) { - if (WidthTok) - Lexer.UnLex(WidthTok.value()); - return MatchOperand_NoMatch; + if (!WidthTok) + return MatchOperand_NoMatch; + IsReallyOffset = true; } const MCExpr *Expr = MCConstantExpr::create(Width, Ctx); SMLoc EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - Operands.push_back(M88kOperand::createImm(Expr, StartLoc, EndLoc)); + if (IsReallyOffset) { + Operands.push_back(M88kOperand::createImm(MCConstantExpr::create(0, Ctx), + StartLoc, EndLoc)); + Operands.push_back(M88kOperand::createToken("<", Parser.getTok().getLoc())); + Operands.push_back(M88kOperand::createImm(Expr, StartLoc, EndLoc)); + Operands.push_back(M88kOperand::createToken(">", Parser.getTok().getLoc())); + } else + Operands.push_back(M88kOperand::createImm(Expr, StartLoc, EndLoc)); // Announce match. return MatchOperand_Success; @@ -494,9 +469,6 @@ OperandMatchResultTy M88kAsmParser::parseBFOffset(OperandVector &Operands) { MCContext &Ctx = getContext(); SMLoc StartLoc = Parser.getTok().getLoc(); - if (Lexer.isNot(AsmToken::Less)) { - return MatchOperand_NoMatch; - } Parser.Lex(); if (Lexer.isNot(AsmToken::Integer)) return MatchOperand_ParseFail; @@ -510,6 +482,7 @@ OperandMatchResultTy M88kAsmParser::parseBFOffset(OperandVector &Operands) { SMLoc EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); Operands.push_back(M88kOperand::createImm(Expr, StartLoc, EndLoc)); + Operands.push_back(M88kOperand::createToken(">", Parser.getTok().getLoc())); // Announce match. return MatchOperand_Success; @@ -750,7 +723,6 @@ bool M88kAsmParser::MatchAndEmitInstruction(SMLoc IdLoc, unsigned &Opcode, } switch (MatchResult) { - case Match_InvalidBitfield: case Match_InvalidBitfieldWidth: case Match_InvalidBitfieldOffset: case Match_InvalidPixelRotationSize: { diff --git a/llvm/lib/Target/M88k/Disassembler/M88kDisassembler.cpp b/llvm/lib/Target/M88k/Disassembler/M88kDisassembler.cpp index 785df37..6ecc0ac 100644 --- a/llvm/lib/Target/M88k/Disassembler/M88kDisassembler.cpp +++ b/llvm/lib/Target/M88k/Disassembler/M88kDisassembler.cpp @@ -167,13 +167,6 @@ static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { return MCDisassembler::Success; } -#if 0 // Not yet used. -static DecodeStatus decodeU5ImmOOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, const void *Decoder) { - return decodeUImmOperand<5>(Inst, Imm); -} -#endif - static DecodeStatus decodeU5ImmOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand<5>(Inst, Imm); @@ -189,19 +182,11 @@ static DecodeStatus decodeVec9Operand(MCInst &Inst, uint64_t Imm, return decodeUImmOperand<9>(Inst, Imm); } -static DecodeStatus decodeBitFieldOperand(MCInst &Inst, uint64_t Imm, - uint64_t Address, - const void *Decoder) { - return decodeUImmOperand<10>(Inst, Imm); -} - -#if 0 // Not yet used. static DecodeStatus decodeBFWidthOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { return decodeUImmOperand<5>(Inst, Imm); } -#endif static DecodeStatus decodeBFOffsetOperand(MCInst &Inst, uint64_t Imm, uint64_t Address, diff --git a/llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp b/llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp index d7d18b7..2fc2f43 100644 --- a/llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp +++ b/llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp @@ -286,31 +286,33 @@ bool M88kInstructionSelector::selectUbfx(MachineInstr &I, const unsigned NewOpc = I.getOpcode() == TargetOpcode::G_UBFX ? M88k::EXTUrwo : M88k::EXTrwo; - int64_t WO; + uint64_t Width, Offset; if (I.getOpcode() == TargetOpcode::G_SEXT_INREG) { // For G_SEXT_INREG, the width is the immediate in operand 2. The offset is // always 0. - int64_t Width = I.getOperand(2).getImm() + 1; + Width = I.getOperand(2).getImm() + 1; assert(Width < 32 && "Can't sign-extend 32bit value"); - WO = Width << 5; + Offset = 0; } else { - auto Offset = + auto OffsetCst = getIConstantVRegValWithLookThrough(I.getOperand(2).getReg(), MRI, true); - if (!Offset) + if (!OffsetCst) return false; + Offset = OffsetCst->Value.getZExtValue(); - auto Width = + auto WidthCst = getIConstantVRegValWithLookThrough(I.getOperand(3).getReg(), MRI, true); - if (!Width) + if (!WidthCst) return false; - WO = Width->Value.getZExtValue() << 5 | Offset->Value.getZExtValue(); + Width = WidthCst->Value.getZExtValue(); } MachineInstr *MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) .add(I.getOperand(0)) .add(I.getOperand(1)) - .addImm(WO); + .addImm(Width) + .addImm(Offset); I.eraseFromParent(); return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); @@ -416,11 +418,11 @@ bool M88kInstructionSelector::selectICmp(MachineInstr &I, if (!constrainSelectedInstRegOperands(*MI, TII, TRI, RBI)) return false; - int64_t WO = 1 << 5 | int64_t(CCCode); MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::EXTUrwo)) .add(I.getOperand(0)) .addReg(Temp, RegState::Kill) - .addImm(WO); + .addImm(1) + .addImm(int64_t(CCCode)); I.eraseFromParent(); return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); @@ -678,7 +680,6 @@ bool M88kInstructionSelector::selectExt(MachineInstr &I, MachineBasicBlock &MBB, isInt<16>(SImm16)) { Register Temp = MRI.createVirtualRegister(&M88k::GPRRCRegClass); ICC CCCode = getCCforICMP(Pred); - int64_t WO = (1 << 5) | int64_t(CCCode); MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::CMPri)) .addReg(Temp, RegState::Define) .addReg(LHS) @@ -687,12 +688,12 @@ bool M88kInstructionSelector::selectExt(MachineInstr &I, MachineBasicBlock &MBB, return false; MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc), DstReg) .addReg(Temp, RegState::Kill) - .addImm(WO); + .addImm(1) + .addImm(int64_t(CCCode)); } else if (mi_match(SrcReg, MRI, m_GICmp(m_Pred(Pred), m_Reg(LHS), m_Reg(RHS)))) { Register Temp = MRI.createVirtualRegister(&M88k::GPRRCRegClass); ICC CCCode = getCCforICMP(Pred); - int64_t WO = (1 << 5) | int64_t(CCCode); MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::CMPrr)) .addReg(Temp, RegState::Define) .addReg(LHS) @@ -701,7 +702,8 @@ bool M88kInstructionSelector::selectExt(MachineInstr &I, MachineBasicBlock &MBB, return false; MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc), DstReg) .addReg(Temp, RegState::Kill) - .addImm(WO); + .addImm(1) + .addImm(int64_t(CCCode)); } else return false; @@ -982,7 +984,8 @@ bool M88kInstructionSelector::earlySelect(MachineInstr &I) { MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::SETrwo), I.getOperand(0).getReg()) .addReg(M88k::R0) - .addImm((16 << 5)|16 /*16<16>*/); + .addImm(16) + .addImm(16); else MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::SUBUri), I.getOperand(0).getReg()) @@ -1048,7 +1051,8 @@ bool M88kInstructionSelector::earlySelect(MachineInstr &I) { MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) .add(I.getOperand(0)) .addReg(SrcReg) - .addImm(((MaskWidth << 5) | MaskOffset) & 0x3ff); + .addImm(MaskWidth & 0x1f) + .addImm(MaskOffset); } I.eraseFromParent(); return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); diff --git a/llvm/lib/Target/M88k/GISel/M88kPostLegalizerLowering.cpp b/llvm/lib/Target/M88k/GISel/M88kPostLegalizerLowering.cpp index fc3432a..49b7c84 100644 --- a/llvm/lib/Target/M88k/GISel/M88kPostLegalizerLowering.cpp +++ b/llvm/lib/Target/M88k/GISel/M88kPostLegalizerLowering.cpp @@ -59,7 +59,8 @@ void replaceMI(unsigned Opc, MachineInstr &MI, MachineRegisterInfo &MRI, const auto *TII = Subtarget.getInstrInfo(); const auto *RBI = Subtarget.getRegBankInfo(); auto Inst = MIB.buildInstr(Opc, {MI.getOperand(0).getReg()}, {SrcReg}) - .addImm((Width << 5) | Offset); + .addImm(Width) + .addImm(Offset); constrainSelectedInstRegOperands(*Inst, *TII, *TRI, *RBI); MI.eraseFromParent(); } diff --git a/llvm/lib/Target/M88k/M88k.td b/llvm/lib/Target/M88k/M88k.td index 9688bec..487e533 100644 --- a/llvm/lib/Target/M88k/M88k.td +++ b/llvm/lib/Target/M88k/M88k.td @@ -55,6 +55,7 @@ def M88kInstrInfo : InstrInfo; def M88kAsmParser : AsmParser; def M88kAsmParserVariant : AsmParserVariant { let RegisterPrefix = "%"; + let TokenizingCharacters = "[]<>*!"; } def M88kAsmWriter : AsmWriter { diff --git a/llvm/lib/Target/M88k/M88kInstrFormats.td b/llvm/lib/Target/M88k/M88kInstrFormats.td index b84393e..945b2dd 100644 --- a/llvm/lib/Target/M88k/M88kInstrFormats.td +++ b/llvm/lib/Target/M88k/M88kInstrFormats.td @@ -131,18 +131,18 @@ class F_BF<bits<6> func, dag outs, dag ins, string asm, list<dag> pattern =[]> // Format: Bit-field with 10-bit width / offset. class F_BI<bits<6> func, dag outs, dag ins, string asm, list<dag> pattern = []> -// : F_B<func, outs, ins, asm, "$rd, $rs1, $w5$o5", pattern> { -// bits<5> w5; -// bits<5> o5; - : F_B<func, outs, ins, asm, "$rd, $rs1, $w5o5", pattern> { - bits<10> w5o5; + : F_B<func, outs, ins, asm, "$rd, $rs1, $w5<$o5>", pattern> { + bits<5> w5; + bits<5> o5; + let Inst{26} = 0b0; - let Inst{9-0} = w5o5; + let Inst{9-5} = w5; + let Inst{4-0} = o5; } // Format: Bit-field with 5-bit offset. class F_BIOFS<bits<6> func, dag outs, dag ins, string asm, list<dag> pattern = []> - : F_B<func, outs, ins, asm, "$rd, $rs1, $o5", pattern> { + : F_B<func, outs, ins, asm, "$rd, $rs1, <$o5>", pattern> { bits<5> o5; let Inst{26} = 0b0; let Inst{9-5} = 0b00000; diff --git a/llvm/lib/Target/M88k/M88kInstrInfo.td b/llvm/lib/Target/M88k/M88kInstrInfo.td index 6556164..531574d 100644 --- a/llvm/lib/Target/M88k/M88kInstrInfo.td +++ b/llvm/lib/Target/M88k/M88kInstrInfo.td @@ -87,31 +87,10 @@ class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> { // Signed and unsigned operands. def U5Imm : ImmediateAsmOperand<"U5Imm">; -def U5ImmO : ImmediateAsmOperand<"U5ImmO"> { - let ParserMethod = "parseBitField"; -} def S16Imm : ImmediateAsmOperand<"S16Imm">; def U16Imm : ImmediateAsmOperand<"U16Imm">; def Vec9 : ImmediateAsmOperand<"Vec9">, ImmediateOp<i32, "Vec9">; -// Bitfield operand. -// TODO Replace usage with BFWidth/BFOffset. -def BFImm : AsmOperandClass { - let Name = "BitField"; - let RenderMethod = "addBitFieldOperands"; - let ParserMethod = "parseBitField"; - let DiagnosticString = "operand must between 0 and 31"; - let DiagnosticType = "InvalidBitfield"; -} -def bfimm : ImmOpWithPattern<i32, "BFImm", [{ - return isUInt<10>(Imm.getZExtValue()); -}], NOOP_SDNodeXForm> { - let PrintMethod = "printBitFieldOperand"; - let DecoderMethod = "decodeBitFieldOperand"; - let OperandNamespace = "M88kOp"; - let OperandType = "OPERAND_BITFIELD"; -} - // Bitfield width operand. def BFWidth : AsmOperandClass { let Name = "BFWidth"; @@ -237,10 +216,6 @@ defm imm32zx16 : Immediate<i32, [{ return (Imm.getZExtValue() & ~0x00000000000000ffULL) == 0; }], NOOP_SDNodeXForm, "U16Imm">; -defm imm32zx5O : Immediate<i32, [{ - return (Imm.getZExtValue() & ~0x000000000000001fULL) == 0; -}], NOOP_SDNodeXForm, "U5ImmO">; - // Predicate: Arbitrary 32 bit value. def uimm32 : IntImmLeaf<i32, [{ uint64_t Val = Imm.getZExtValue(); @@ -343,7 +318,7 @@ multiclass Bitfield<bits<6> Func, string OpcStr> { def rr : F_BR<Func, OpcStr>; if !ne(OpcStr, "rot") then { def rwo : F_BI<Func, - (outs GPR:$rd), (ins GPR:$rs1, bfimm:$w5o5), + (outs GPR:$rd), (ins GPR:$rs1, bfwidth:$w5, bfoffset:$o5), OpcStr>; } else { def rwo : F_BIOFS<Func, @@ -364,9 +339,9 @@ def : Pat<(sra GPR:$rs1, GPR:$rs2), (EXTrr GPR:$rs1, GPR:$rs2)>; def : Pat<(srl GPR:$rs1, GPR:$rs2), (EXTUrr GPR:$rs1, GPR:$rs2)>; def : Pat<(shl GPR:$rs1, GPR:$rs2), (MAKrr GPR:$rs1, GPR:$rs2)>; def : Pat<(rotr GPR:$rs1, GPR:$rs2), (ROTrr GPR:$rs1, GPR:$rs2)>; -def : Pat<(sra GPR:$rs1, imm32zx5O:$o5), (EXTrwo GPR:$rs1, imm32zx5O:$o5)>; -def : Pat<(srl GPR:$rs1, imm32zx5O:$o5), (EXTUrwo GPR:$rs1, imm32zx5O:$o5)>; -def : Pat<(shl GPR:$rs1, imm32zx5O:$o5), (MAKrwo GPR:$rs1, imm32zx5O:$o5)>; +def : Pat<(sra GPR:$rs1, bfoffset:$o5), (EXTrwo GPR:$rs1, 0, bfoffset:$o5)>; +def : Pat<(srl GPR:$rs1, bfoffset:$o5), (EXTUrwo GPR:$rs1, 0, bfoffset:$o5)>; +def : Pat<(shl GPR:$rs1, bfoffset:$o5), (MAKrwo GPR:$rs1, 0, bfoffset:$o5)>; def : Pat<(rotr GPR:$rs1, bfoffset:$o5), (ROTrwo GPR:$rs1, bfoffset:$o5)>; class FindBF<bits<6> Func, string OpcStr> : @@ -434,23 +409,23 @@ defm : BinaryOpPat<"DIVS", sdiv>; //def : Pat<(umullohi GPR:$rs1, GPR:$rs2), (MULUrrd GPR:$rs1, GPR:$rs2)>; def : Pat<(ineg GPR:$rs2), (SUBUrr (i32 R0), GPR:$rs2)>; -multiclass SetCCPat<CondCode CC, bits<10> w5o5> { +multiclass SetCCPat<CondCode CC, bits<5> w5, bits<5> o5> { def : Pat<(setcc (i32 GPR:$lhs), (i32 GPR:$rhs), CC), - (EXTUrwo (CMPrr GPR:$lhs, GPR:$rhs), w5o5)>; + (EXTUrwo (CMPrr GPR:$lhs, GPR:$rhs), w5, o5)>; def : Pat<(setcc (i32 GPR:$lhs), imm32zx16:$rhs, CC), - (EXTUrwo (CMPrr GPR:$lhs, imm32zx16:$rhs), w5o5)>; -} - -defm : SetCCPat<SETEQ, 34>; -defm : SetCCPat<SETNE, 35>; -defm : SetCCPat<SETGT, 36>; -defm : SetCCPat<SETLE, 37>; -defm : SetCCPat<SETLT, 38>; -defm : SetCCPat<SETGE, 39>; -defm : SetCCPat<SETUGT, 40>; -defm : SetCCPat<SETULE, 41>; -defm : SetCCPat<SETULT, 42>; -defm : SetCCPat<SETUGE, 43>; + (EXTUrwo (CMPrr GPR:$lhs, imm32zx16:$rhs), w5, o5)>; +} + +defm : SetCCPat<SETEQ, 1, 2>; +defm : SetCCPat<SETNE, 1, 3>; +defm : SetCCPat<SETGT, 1, 4>; +defm : SetCCPat<SETLE, 1, 5>; +defm : SetCCPat<SETLT, 1, 6>; +defm : SetCCPat<SETGE, 1, 7>; +defm : SetCCPat<SETUGT, 1, 8>; +defm : SetCCPat<SETULE, 1, 8>; +defm : SetCCPat<SETULT, 1, 10>; +defm : SetCCPat<SETUGE, 1, 11>; /* Addressing modes: diff --git a/llvm/lib/Target/M88k/MCTargetDesc/M88kBaseInfo.h b/llvm/lib/Target/M88k/MCTargetDesc/M88kBaseInfo.h index 500440a8..83c4db8 100644 --- a/llvm/lib/Target/M88k/MCTargetDesc/M88kBaseInfo.h +++ b/llvm/lib/Target/M88k/MCTargetDesc/M88kBaseInfo.h @@ -41,7 +41,6 @@ enum OperandType : unsigned { OPERAND_UIMM16, OPERAND_SIMM16, OPERAND_CONDITION_CODE, - OPERAND_BITFIELD, OPERAND_BFWIDTH, OPERAND_BFOFFSET, OPERAND_PIXELROTATE, diff --git a/llvm/lib/Target/M88k/MCTargetDesc/M88kInstPrinter.cpp b/llvm/lib/Target/M88k/MCTargetDesc/M88kInstPrinter.cpp index 87e7bf4..29db396 100644 --- a/llvm/lib/Target/M88k/MCTargetDesc/M88kInstPrinter.cpp +++ b/llvm/lib/Target/M88k/MCTargetDesc/M88kInstPrinter.cpp @@ -63,14 +63,6 @@ void M88kInstPrinter::printU5ImmOperand(const MCInst *MI, int OpNum, O << Value; } -void M88kInstPrinter::printU5ImmOOperand(const MCInst *MI, int OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - int64_t Value = MI->getOperand(OpNum).getImm(); - // assert(isUInt<N>(Value) && "Invalid uimm argument"); - O << "<" << Value << ">"; -} - void M88kInstPrinter::printU16ImmOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { @@ -95,23 +87,12 @@ void M88kInstPrinter::printVec9Operand(const MCInst *MI, int OpNum, } } -void M88kInstPrinter::printBitFieldOperand(const MCInst *MI, int OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - int64_t Value = MI->getOperand(OpNum).getImm(); - assert(isUInt<10>(Value) && "Invalid bitfield argument"); - int64_t Width = (Value >> 5) & 0x1f; - int64_t Offset = Value & 0x1f; - O << Width << "<" << Offset << ">"; -} - void M88kInstPrinter::printBFWidthOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { int64_t Value = MI->getOperand(OpNum).getImm(); assert(isUInt<5>(Value) && "Invalid bitfield width argument"); - if (Value) - O << Value; + O << Value; } void M88kInstPrinter::printBFOffsetOperand(const MCInst *MI, int OpNum, @@ -119,7 +100,7 @@ void M88kInstPrinter::printBFOffsetOperand(const MCInst *MI, int OpNum, raw_ostream &O) { int64_t Value = MI->getOperand(OpNum).getImm(); assert(isUInt<5>(Value) && "Invalid bitfield offset argument"); - O << "<" << Value << ">"; + O << Value; } void M88kInstPrinter::printPixelRotOperand(const MCInst *MI, int OpNum, diff --git a/llvm/lib/Target/M88k/MCTargetDesc/M88kInstPrinter.h b/llvm/lib/Target/M88k/MCTargetDesc/M88kInstPrinter.h index ca43fa0..a9fee10 100644 --- a/llvm/lib/Target/M88k/MCTargetDesc/M88kInstPrinter.h +++ b/llvm/lib/Target/M88k/MCTargetDesc/M88kInstPrinter.h @@ -41,14 +41,10 @@ public: void printU5ImmOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI, raw_ostream &O); - void printU5ImmOOperand(const MCInst *MI, int OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); void printU16ImmOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI, raw_ostream &O); void printVec9Operand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI, raw_ostream &O); - void printBitFieldOperand(const MCInst *MI, int OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); void printBFWidthOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI, raw_ostream &O); void printBFOffsetOperand(const MCInst *MI, int OpNum, |