[m88k] Consistently use R0 for zero register value

Overloads constrainSelectedInstRegOperands() and iterate over operands.
If a register has value zero then replace it with R0.

2 files changed, 81 insertions, 44 deletions

diff --git a/llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp b/llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp
index fbf6394..97a4eb5 100644
--- a/llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp
+++ b/llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp
@@ -57,6 +57,12 @@ private:
 
   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
 
+  bool constrainSelectedInstRegOperands(MachineInstr &I,
+                                        const MachineRegisterInfo &MRI,
+                                        const TargetInstrInfo &TII,
+                                        const TargetRegisterInfo &TRI,
+                                        const RegisterBankInfo &RBI) const;
+
   void renderLO16(MachineInstrBuilder &MIB, const MachineInstr &I,
                   int OpIdx = -1) const;
   void renderHI16(MachineInstrBuilder &MIB, const MachineInstr &I,
@@ -149,6 +155,21 @@ M88kInstructionSelector::M88kInstructionSelector(
 {
 }
 
+// Check is the register Reg is zero. If yes then return the hardware zero
+// register, otherwise return Reg.
+static Register getRegOrZero(Register Reg, const MachineRegisterInfo &MRI) {
+  Optional<ValueAndVReg> Res =
+      getIConstantVRegValWithLookThrough(Reg, MRI, true);
+  if (Res && Res->Value.isZero())
+    return M88k::R0;
+  return Reg;
+}
+
+static Register getRegOrZero(MachineOperand &OP,
+                             const MachineRegisterInfo &MRI) {
+  return getRegOrZero(OP.getReg(), MRI);
+}
+
 // Like llvm::getSrcRegIgnoringCopies() but returns the register from argument
 // list instead of None.
 static Register getRegIgnoringCopies(Register Reg,
@@ -206,6 +227,24 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
   return true;
 }
 
+bool M88kInstructionSelector::constrainSelectedInstRegOperands(
+    MachineInstr &I, const MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
+    const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) const {
+  for (MachineOperand &OP : I.explicit_operands()) {
+    if (!OP.isReg())
+      continue;
+    Register Reg = OP.getReg();
+    if (Register::isPhysicalRegister(Reg))
+      continue;
+    Optional<ValueAndVReg> Res =
+        getIConstantVRegValWithLookThrough(Reg, MRI, true);
+    // TODO This needs an update when the XR register class is supported.
+    if (Res && Res->Value.isZero())
+      OP.setReg(M88k::R0);
+  }
+  return ::constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+}
+
 void M88kInstructionSelector::renderLO16(MachineInstrBuilder &MIB,
                                          const MachineInstr &I,
                                          int OpIdx) const {
@@ -236,8 +275,7 @@ bool M88kInstructionSelector::selectFrameIndex(MachineInstr &I,
                          .add(I.getOperand(1))
                          .addImm(0);
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
-  return false;
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectGlobalValue(
@@ -251,7 +289,7 @@ bool M88kInstructionSelector::selectGlobalValue(
                          .addReg(Temp, RegState::Define)
                          .addReg(M88k::R0)
                          .addGlobalAddress(GV, 0, M88kII::MO_ABS_HI);
-  if (!constrainSelectedInstRegOperands(*MI, TII, TRI, RBI))
+  if (!constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI))
     return false;
 
   MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::ORri))
@@ -260,7 +298,7 @@ bool M88kInstructionSelector::selectGlobalValue(
            .addGlobalAddress(GV, 0, M88kII::MO_ABS_LO);
 
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectFPtoSI(MachineInstr &I,
@@ -284,7 +322,7 @@ bool M88kInstructionSelector::selectFPtoSI(MachineInstr &I,
                I.getOperand(0).getReg())
            .addReg(I.getOperand(1).getReg());
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectUbfx(MachineInstr &I,
@@ -325,7 +363,7 @@ bool M88kInstructionSelector::selectUbfx(MachineInstr &I,
                          .addImm(Offset);
 
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 enum class ICC : unsigned {
@@ -425,7 +463,7 @@ bool M88kInstructionSelector::selectICmp(MachineInstr &I,
              .addReg(LHS)
              .add(I.getOperand(3));
   }
-  if (!constrainSelectedInstRegOperands(*MI, TII, TRI, RBI))
+  if (!constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI))
     return false;
 
   MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::EXTUrwo))
@@ -435,7 +473,7 @@ bool M88kInstructionSelector::selectICmp(MachineInstr &I,
            .addImm(int64_t(CCCode));
 
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectBrCond(MachineInstr &I,
@@ -468,7 +506,7 @@ bool M88kInstructionSelector::selectBrCond(MachineInstr &I,
                .addReg(Temp, RegState::Define)
                .addReg(LHS)
                .addImm(UImm16);
-      if (!constrainSelectedInstRegOperands(*MI, TII, TRI, RBI))
+      if (!constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI))
         return false;
       MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::BB1))
                .addImm(static_cast<int64_t>(CCCode))
@@ -482,7 +520,7 @@ bool M88kInstructionSelector::selectBrCond(MachineInstr &I,
              .addReg(Temp, RegState::Define)
              .addReg(LHS)
              .addReg(RHS);
-    if (!constrainSelectedInstRegOperands(*MI, TII, TRI, RBI))
+    if (!constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI))
       return false;
     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::BB1))
              .addImm(static_cast<int64_t>(CCCode))
@@ -512,7 +550,7 @@ bool M88kInstructionSelector::selectBrCond(MachineInstr &I,
   }
 
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectJumpTable(MachineInstr &I,
@@ -529,7 +567,7 @@ bool M88kInstructionSelector::selectJumpTable(MachineInstr &I,
            .addReg(Temp, RegState::Define)
            .addReg(M88k::R0)
            .addJumpTableIndex(JTIndex, M88kII::MO_ABS_HI);
-  if (!constrainSelectedInstRegOperands(*MI, TII, TRI, RBI))
+  if (!constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI))
     return false;
 
   MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::ORri))
@@ -537,7 +575,7 @@ bool M88kInstructionSelector::selectJumpTable(MachineInstr &I,
            .addReg(Temp, RegState::Kill)
            .addJumpTableIndex(JTIndex, M88kII::MO_ABS_LO);
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectBrJT(MachineInstr &I,
@@ -566,12 +604,12 @@ bool M88kInstructionSelector::selectBrJT(MachineInstr &I,
              .addReg(JTPtrReg)
              .addReg(JTIndexReg);
   }
-  if (!constrainSelectedInstRegOperands(*MI, TII, TRI, RBI))
+  if (!constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI))
     return false;
 
   MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::JMP)).addReg(DstReg);
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectBrIndirect(MachineInstr &I,
@@ -582,7 +620,7 @@ bool M88kInstructionSelector::selectBrIndirect(MachineInstr &I,
   MachineInstr *MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::JMP))
                          .addReg(I.getOperand(0).getReg());
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectPtrAdd(MachineInstr &I,
@@ -607,7 +645,7 @@ bool M88kInstructionSelector::selectPtrAdd(MachineInstr &I,
              .addReg(AddendReg);
   }
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectAddSubWithCarry(
@@ -654,7 +692,7 @@ bool M88kInstructionSelector::selectAddSubWithCarry(
   }
 
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MIB, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectMul(MachineInstr &I, MachineBasicBlock &MBB,
@@ -686,7 +724,7 @@ bool M88kInstructionSelector::selectMul(MachineInstr &I, MachineBasicBlock &MBB,
     return false;
 
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectUDiv(MachineInstr &I,
@@ -714,7 +752,7 @@ bool M88kInstructionSelector::selectUDiv(MachineInstr &I,
     return false;
 
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectExt(MachineInstr &I, MachineBasicBlock &MBB,
@@ -741,7 +779,7 @@ bool M88kInstructionSelector::selectExt(MachineInstr &I, MachineBasicBlock &MBB,
              .addReg(Temp, RegState::Define)
              .addReg(LHS)
              .addImm(SImm16);
-    if (!constrainSelectedInstRegOperands(*MI, TII, TRI, RBI))
+    if (!constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI))
       return false;
     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc), DstReg)
              .addReg(Temp, RegState::Kill)
@@ -755,7 +793,7 @@ bool M88kInstructionSelector::selectExt(MachineInstr &I, MachineBasicBlock &MBB,
              .addReg(Temp, RegState::Define)
              .addReg(LHS)
              .addReg(RHS);
-    if (!constrainSelectedInstRegOperands(*MI, TII, TRI, RBI))
+    if (!constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI))
       return false;
     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc), DstReg)
              .addReg(Temp, RegState::Kill)
@@ -765,7 +803,7 @@ bool M88kInstructionSelector::selectExt(MachineInstr &I, MachineBasicBlock &MBB,
     return false;
 
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 enum class LoadStore : unsigned {
@@ -858,7 +896,7 @@ bool M88kInstructionSelector::selectLoadStore(MachineInstr &I,
              .addReg(Temp, RegState::Define)
              .addReg(M88k::R0)
              .addGlobalAddress(GV, 0, M88kII::MO_ABS_HI);
-    if (!constrainSelectedInstRegOperands(*MI, TII, TRI, RBI))
+    if (!constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI))
       return false;
 
     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
@@ -917,7 +955,7 @@ bool M88kInstructionSelector::selectLoadStore(MachineInstr &I,
   }
 
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
 }
 
 bool M88kInstructionSelector::selectMergeUnmerge(
@@ -947,7 +985,6 @@ bool M88kInstructionSelector::selectMergeUnmerge(
              .addReg(SrcReg, 0, M88k::sub_lo);
     RBI.constrainGenericRegister(I.getOperand(0).getReg(), M88k::GPRRCRegClass,
                                  MRI);
-    constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
 
     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
                  I.getOperand(1).getReg())
@@ -956,7 +993,7 @@ bool M88kInstructionSelector::selectMergeUnmerge(
                                  MRI);
   }
   I.eraseFromParent();
-  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+  return true;
 }
 
 bool M88kInstructionSelector::selectIntrinsic(MachineInstr &I,
@@ -990,7 +1027,7 @@ bool M88kInstructionSelector::selectIntrinsic(MachineInstr &I,
                .addReg(MFReturnAddr);
 
       I.eraseFromParent();
-      return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+      return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
     }
 
     MFI.setFrameAddressIsTaken(true);
@@ -1001,7 +1038,7 @@ bool M88kInstructionSelector::selectIntrinsic(MachineInstr &I,
                .addUse(FrameAddr)
                .addImm(0);
 
-      constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+      constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
       FrameAddr = NextFrame;
     }
 
@@ -1017,7 +1054,7 @@ bool M88kInstructionSelector::selectIntrinsic(MachineInstr &I,
     }
 
     I.eraseFromParent();
-    return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+    return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
   }
   }
   return false;
@@ -1052,7 +1089,7 @@ bool M88kInstructionSelector::earlySelect(MachineInstr &I) {
                    .addReg(M88k::R0)
                    .addImm(-Cst);
         I.eraseFromParent();
-        return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+        return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
       }
     }
     return false;
@@ -1115,7 +1152,7 @@ bool M88kInstructionSelector::earlySelect(MachineInstr &I) {
                .addImm(MaskOffset);
     }
     I.eraseFromParent();
-    return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+    return constrainSelectedInstRegOperands(*MI, MRI, TII, TRI, RBI);
   }
   default:
     return false;
diff --git a/llvm/test/CodeGen/M88k/add.ll b/llvm/test/CodeGen/M88k/add.ll
index ad1950e..13aefa5 100644
--- a/llvm/test/CodeGen/M88k/add.ll
+++ b/llvm/test/CodeGen/M88k/add.ll
@@ -57,8 +57,8 @@ define i64 @f6(i64 %a, i64 %b) {
 ; Special case: return (a == 0) + b
 define i32 @f7(i32 %a, i32 %b) {
 ; CHECK-LABEL: f7:
-; CHECK:       subu.co %r2, %r4, %r2
-; CHECK-NEXT:  addu.ci %r2, %r3, %r4
+; CHECK:       subu.co %r2, %r0, %r2
+; CHECK-NEXT:  addu.ci %r2, %r3, %r0
 ; CHECK-NEXT:  jmp %r1
   %cmp = icmp eq i32 %a, 0
   %conv = zext i1 %cmp to i32
@@ -69,8 +69,8 @@ define i32 @f7(i32 %a, i32 %b) {
 ; Same, but using intrinsic
 define i32 @f8(i32 %a, i32 %b) {
 ; CHECK-LABEL: f8:
-; CHECK:       subu.co %r2, %r4, %r2
-; CHECK-NEXT:  addu.ci %r2, %r3, %r4
+; CHECK:       subu.co %r2, %r0, %r2
+; CHECK-NEXT:  addu.ci %r2, %r3, %r0
 ; CHECK-NEXT:  jmp %r1
   %res = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 0, i32 %a)
   %carrybit = extractvalue { i32, i1 } %res, 1
@@ -85,7 +85,7 @@ declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32)
 define i32 @f9(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: f9:
 ; CHECK:       subu.co %r2, %r2, %r3
-; CHECK-NEXT:  addu.ci %r2, %r4, %r5
+; CHECK-NEXT:  addu.ci %r2, %r4, %r0
 ; CHECK-NEXT:  jmp %r1
   %cmp = icmp uge i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -97,7 +97,7 @@ define i32 @f9(i32 %a, i32 %b, i32 %c) {
 define i32 @f10(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: f10:
 ; CHECK:       subu.co %r2, %r3, %r2
-; CHECK-NEXT:  addu.ci %r2, %r4, %r5
+; CHECK-NEXT:  addu.ci %r2, %r4, %r0
 ; CHECK-NEXT:  jmp %r1
   %cmp = icmp ule i32 %a, %b
   %conv = zext i1 %cmp to i32
@@ -109,7 +109,7 @@ define i32 @f10(i32 %a, i32 %b, i32 %c) {
 define i32 @f11(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: f11:
 ; CHECK:       subu.co %r3, %r3, %r4
-; CHECK-NEXT:  subu.ci %r2, %r2, %r5
+; CHECK-NEXT:  subu.ci %r2, %r2, %r0
 ; CHECK-NEXT:  jmp %r1
   %cmp = icmp ult i32 %b, %c
   %conv = zext i1 %cmp to i32
@@ -121,7 +121,7 @@ define i32 @f11(i32 %a, i32 %b, i32 %c) {
 define i32 @f12(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: f12:
 ; CHECK:       subu.co %r3, %r4, %r3
-; CHECK-NEXT:  subu.ci %r2, %r2, %r5
+; CHECK-NEXT:  subu.ci %r2, %r2, %r0
 ; CHECK-NEXT:  jmp %r1
   %cmp = icmp ugt i32 %b, %c
   %conv = zext i1 %cmp to i32
@@ -132,8 +132,8 @@ define i32 @f12(i32 %a, i32 %b, i32 %c) {
 ; Special case: return a - (b != 0)
 define i32 @f13(i32 %a, i32 %b) {
 ; CHECK-LABEL: f13:
-; CHECK:       subu.co %r3, %r4, %r3
-; CHECK-NEXT:  subu.ci %r2, %r2, %r4
+; CHECK:       subu.co %r3, %r0, %r3
+; CHECK-NEXT:  subu.ci %r2, %r2, %r0
 ; CHECK-NEXT:  jmp %r1
   %cmp = icmp ne i32 %b, 0
   %conv = zext i1 %cmp to i32
@@ -145,7 +145,7 @@ define i32 @f13(i32 %a, i32 %b) {
 define i32 @f14(i32 %a, i32 %b) {
 ; CHECK-LABEL: f14:
 ; CHECK:       addu.co %r3, %r3, %r3
-; CHECK-NEXT:  subu.ci %r2, %r2, %r4
+; CHECK-NEXT:  subu.ci %r2, %r2, %r0
 ; CHECK-NEXT:  jmp %r1
   %cmp = icmp sge i32 %b, 0
   %conv = zext i1 %cmp to i32
@@ -157,7 +157,7 @@ define i32 @f14(i32 %a, i32 %b) {
 define i32 @f15(i32 %a, i32 %b) {
 ; CHECK-LABEL: f15:
 ; CHECK:       addu.co %r3, %r3, %r3
-; CHECK-NEXT:  subu.ci %r2, %r2, %r4
+; CHECK-NEXT:  subu.ci %r2, %r2, %r0
 ; CHECK-NEXT:  jmp %r1
   %cmp = icmp sle i32 0, %b
   %conv = zext i1 %cmp to i32