[m88k] Generate lookup table for isns with delay slot

2 files changed, 42 insertions, 8 deletions

diff --git a/llvm/lib/Target/M88k/M88kInstrFormats.td b/llvm/lib/Target/M88k/M88kInstrFormats.td
index c92ac0d..8da36aa 100644
--- a/llvm/lib/Target/M88k/M88kInstrFormats.td
+++ b/llvm/lib/Target/M88k/M88kInstrFormats.td
@@ -18,10 +18,20 @@ class InstM88k<dag outs, dag ins, string asm, string operands,
 
   dag OutOperandList = outs;
   dag InOperandList = ins;
-  let AsmString = !if(!eq(operands, ""), asm, !strconcat(asm, " ", operands));
+  // Construct the assembler string from template parameters asm and operands.
+  // If the instruction has a delay slot, then append ".n" to the mnemonic.
+  let AsmString = !if(!eq(operands, ""),
+                     !if(hasDelaySlot, !strconcat(asm, ".n"), asm),
+                     !strconcat(!if(hasDelaySlot, !strconcat(asm, ".n"), asm), " ", operands));
   let Pattern = pattern;
 
   let DecoderNamespace = "M88k";
+
+  // Store the base opcode to enable grouping of instructions.
+  // For example, branch instructions with and without a delay slot have the
+  // same base opcode.
+  // TODO Works currently only for branches/jumps with and without a delay slot.
+  string Opcode = asm;
 }
 
 class Pseudo<dag outs, dag ins, list<dag> pattern>
@@ -31,7 +41,31 @@ class Pseudo<dag outs, dag ins, list<dag> pattern>
   let hasNoSchedulingInfo = 1;
 }
 
+//===----------------------------------------------------------------------===//
+// Mappings between instructions
+//===----------------------------------------------------------------------===//
+
+// Return the version of an instruction with delay slot.
+def getOpcodeWithDelaySlot : InstrMapping {
+  let FilterClass = "InstM88k";
+  let RowFields = ["Opcode"];
+  let ColFields = ["hasDelaySlot"];
+  let KeyCol = ["0"];
+  let ValueCols = [["1"]];
+}
+
+// Return the version of an instruction without delay slot.
+def getOpcodeWithoutDelaySlot : InstrMapping {
+  let FilterClass = "InstM88k";
+  let RowFields = ["Opcode"];
+  let ColFields = ["hasDelaySlot"];
+  let KeyCol = ["0"];
+  let ValueCols = [["1"]];
+}
+
+//===----------------------------------------------------------------------===//
 // The formats follow the categories specified in the User Manual.
+//===----------------------------------------------------------------------===//
 
 // Category: Logical.
 class F_L<dag outs, dag ins, string asm, string operands,
diff --git a/llvm/lib/Target/M88k/M88kInstrInfo.td b/llvm/lib/Target/M88k/M88kInstrInfo.td
index ec46524..49ceb74 100644
--- a/llvm/lib/Target/M88k/M88kInstrInfo.td
+++ b/llvm/lib/Target/M88k/M88kInstrInfo.td
@@ -812,17 +812,17 @@ def : Pat<(m88k_hi tglobaladdr:$dst), (ORriu (i32 R0), tglobaladdr:$dst)>;
 let isBarrier = 1, isBranch = 1, isTerminator = 1, isIndirectBranch = 1 in {
   def JMP : F_JMP<0b11000, (outs), (ins GPR:$rs2), "jmp", [(brind GPR:$rs2)]>;
   let hasDelaySlot = 1 in
-    def JMPn : F_JMP<0b11000, (outs), (ins GPR:$rs2), "jmp.n">;
+    def JMPn : F_JMP<0b11000, (outs), (ins GPR:$rs2), "jmp">;
 }
 
 let isCall = 1 in {
   def JSR : F_JMP<0b11001, (outs), (ins GPR:$rs2), "jsr">;
   let hasDelaySlot = 1 in
-    def JSRn : F_JMP<0b11001, (outs), (ins GPR:$rs2), "jsr.n">;
+    def JSRn : F_JMP<0b11001, (outs), (ins GPR:$rs2), "jsr">;
 
   def BSR : F_BRANCH<0b11001, (outs), (ins brtarget26:$d26), "bsr">;
   let hasDelaySlot = 1 in
-    def BSRn : F_BRANCH<0b11001, (outs), (ins brtarget26:$d26), "bsr.n">;
+    def BSRn : F_BRANCH<0b11001, (outs), (ins brtarget26:$d26), "bsr">;
 }
 
 let isReturn = 1, isTerminator = 1, isBarrier = 1, Uses = [R1] in {
@@ -833,7 +833,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
   def BR : F_BRANCH<0b11000, (outs), (ins brtarget26:$d26), "br",
                     [(br bb:$d26)]>;
   let hasDelaySlot = 1 in
-    def BRn : F_BRANCH<0b11000, (outs), (ins brtarget26:$d26), "br.n">;
+    def BRn : F_BRANCH<0b11000, (outs), (ins brtarget26:$d26), "br">;
 }
 
 let isBranch = 1, isTerminator = 1 in {
@@ -849,13 +849,13 @@ let isBranch = 1, isTerminator = 1 in {
   let hasDelaySlot = 1 in {
     def BB0n : F_BCOND<0b11010,
                        (outs), (ins imm32zx5:$m5, GPR:$rs1, brtarget16:$d16),
-                       "bb0.n">;
+                       "bb0">;
     def BB1n : F_BCOND<0b11011,
                       (outs), (ins imm32zx5:$m5, GPR:$rs1, brtarget16:$d16),
-                      "bb1.n">;
+                      "bb1">;
     def BCNDn : F_BCOND<0b11101,
                         (outs), (ins ccode:$m5, GPR:$rs1, brtarget16:$d16),
-                        "bcnd.n">;
+                        "bcnd">;
   }
 }