diff options
author | Kai Nacke <kai@redstar.de> | 2022-08-11 21:07:25 -0400 |
---|---|---|
committer | Kai Nacke <kai@redstar.de> | 2022-11-13 11:07:43 -0500 |
commit | 123f32241e725da2ba8e04ef28982ccc50e1a312 (patch) | |
tree | 483e1817c4567f72df3c4640243c03ec755377c6 | |
parent | ca81660d5691f93538fd8525ed1d08a5cba009fd (diff) | |
download | llvm-123f32241e725da2ba8e04ef28982ccc50e1a312.zip llvm-123f32241e725da2ba8e04ef28982ccc50e1a312.tar.gz llvm-123f32241e725da2ba8e04ef28982ccc50e1a312.tar.bz2 |
[m88k] Decode more ambigous instruction.
xmem [mc88100] and ld.x [mc88110] have the same encoding.
- Uses only one namespace for MC88110.
- Some changes to predicates.
- Updates valid instruction test case for MC88100.
-rw-r--r-- | llvm/lib/Target/M88k/Disassembler/M88kDisassembler.cpp | 4 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/M88k.td | 22 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/M88kInstrInfo.td | 63 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/M88kSchedule.td | 2 | ||||
-rw-r--r-- | llvm/lib/Target/M88k/M88kSubtarget.h | 11 | ||||
-rw-r--r-- | llvm/test/MC/M88k/valid.s | 19 |
6 files changed, 63 insertions, 58 deletions
diff --git a/llvm/lib/Target/M88k/Disassembler/M88kDisassembler.cpp b/llvm/lib/Target/M88k/Disassembler/M88kDisassembler.cpp index b8aa891..785df37 100644 --- a/llvm/lib/Target/M88k/Disassembler/M88kDisassembler.cpp +++ b/llvm/lib/Target/M88k/Disassembler/M88kDisassembler.cpp @@ -261,9 +261,7 @@ DecodeStatus M88kDisassembler::getInstruction(MCInst &MI, uint64_t &Size, if (STI.getFeatureBits()[M88k::Proc88110]) return decodeInstruction(DecoderTableMC8811032, MI, Inst, Address, this, STI); - else - return decodeInstruction(DecoderTableMC8810032, MI, Inst, Address, this, - STI); + return MCDisassembler::Fail; } return MCDisassembler::Success; } diff --git a/llvm/lib/Target/M88k/M88k.td b/llvm/lib/Target/M88k/M88k.td index 78cd6f4..9688bec 100644 --- a/llvm/lib/Target/M88k/M88k.td +++ b/llvm/lib/Target/M88k/M88k.td @@ -16,8 +16,17 @@ include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// -// M88k Subtarget features. -// +// M88k subtarget features. +//===----------------------------------------------------------------------===// + +def FeatureGraphics : SubtargetFeature<"graphics", "HasGraphics", "true", + "has graphics instructions", []>; + +def Proc88100 : SubtargetFeature<"mc88100", "M88kProc", "MC88100", + "Motorola 88100 processor", []>; +def Proc88110 : SubtargetFeature<"mc88110", "M88kProc", "MC88110", + "Motorola 88110 processor", + [FeatureGraphics]>; //===----------------------------------------------------------------------===// // Register File, Calling Conv, Instruction Descriptions @@ -32,15 +41,6 @@ include "M88kCombine.td" include "M88kSchedule.td" //===----------------------------------------------------------------------===// -// M88k subtarget features. -//===----------------------------------------------------------------------===// - -def Proc88100 : SubtargetFeature<"mc88100", "M88kProc", "MC88100", - "Motorola 88100 processor", []>; -def Proc88110 : SubtargetFeature<"mc88110", "M88kProc", "MC88110", - "Motorola 88110 processor", []>; - -//===----------------------------------------------------------------------===// // M88k processors supported. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/M88k/M88kInstrInfo.td b/llvm/lib/Target/M88k/M88kInstrInfo.td index ab15f39..ff5f6be 100644 --- a/llvm/lib/Target/M88k/M88kInstrInfo.td +++ b/llvm/lib/Target/M88k/M88kInstrInfo.td @@ -11,9 +11,11 @@ //===----------------------------------------------------------------------===// -def IsMC88100 : Predicate<"Subtarget->isMC88100()">; -def IsMC88110 : Predicate<"Subtarget->isMC88110()">; -class MC88110 { list<Predicate> Predicates = [IsMC88110]; } +def Graphics : Predicate<"Subtarget->hasGraphics()">; +def MC88110 : Predicate<"Subtarget->isMC88110()">, + AssemblerPredicate<(all_of Proc88110), "MC88110">; +def NotMC88110 : Predicate<"!Subtarget->isMC88110()">, + AssemblerPredicate<(all_of (not Proc88110)), "!MC88110">; // ---------------------------------------------------------------------------// // Selection DAG Nodes. @@ -428,7 +430,7 @@ defm DIVS : ArithTri<0b011110, "divs">; let isCompare = 1 in defm CMP : ArithTri<0b011111, "cmp">; -let Predicates = [IsMC88110] in { +let Predicates = [MC88110] in { def DIVUrrd : F_IRCD<0b011010, GPR64, GPR, "divu.d">; let isCommutable = 1 in def MULUrrd : F_IRCD<0b011011, GPR, GPR, "mulu.d">; @@ -510,7 +512,7 @@ multiclass StoreIndexImm { (outs), (ins GPR64:$rd, GPR:$rs1, imm32zx16:$si16), !strconcat(OpcStr, ".d"), [(store (i64 GPR64:$rd), (ADDRri (i32 GPR:$rs1), imm32zx16:$si16))]>; - let Predicates = [IsMC88110] in { + let Predicates = [MC88110] in { def xis : F_LS<0b0011, /*ty=*/ 0b01, (outs), (ins XR:$rd, GPR:$rs1, imm32zx16:$si16), OpcStr, @@ -587,7 +589,7 @@ multiclass LoadUnscaled<bits<4> Func, string OpcStr> { (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), !strconcat(OpcStr, ".h.usr")>; } - let regfile = 0, Predicates = [IsMC88110] in { + let regfile = 0, Predicates = [MC88110] in { def xxuw : F_LSINDUSC<Func, /*ty=*/ 0b01, /*user=*/ 0b0, (outs XR:$rd), (ins GPR:$rs1, GPR:$rs2), OpcStr>; @@ -636,7 +638,7 @@ multiclass LoadScaled<bits<4> Func, string OpcStr> { (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), !strconcat(OpcStr, ".h.usr")>; } - let regfile = 0, Predicates = [IsMC88110] in { + let regfile = 0, Predicates = [MC88110] in { def xxsw : F_LSINDSC<Func, /*ty=*/ 0b01, /*user=*/ 0b0, (outs XR:$rd), (ins GPR:$rs1, GPR:$rs2), OpcStr>; @@ -683,7 +685,7 @@ multiclass StoreUnscaled<bits<4> Func, string OpcStr> { !strconcat(OpcStr, ".h", Suffix)>; } } - let regfile = 0, Predicates = [IsMC88110] in { + let regfile = 0, Predicates = [MC88110] in { let through = T in { def xrus # s : F_LSINDUSC<Func, /*ty=*/ 0b01, /*user=*/ U, (outs XR:$rd), (ins GPR:$rs1, GPR:$rs2), @@ -725,7 +727,7 @@ multiclass StoreScaled<bits<4> Func, string OpcStr> { !strconcat(OpcStr, ".h", Suffix)>; } } - let regfile = 0, Predicates = [IsMC88110] in { + let regfile = 0, Predicates = [MC88110] in { let through = T in { def xrss # s : F_LSINDSC<Func, /*ty=*/ 0b01, /*user=*/ U, (outs XR:$rd), (ins GPR:$rs1, GPR:$rs2), @@ -749,24 +751,23 @@ multiclass LoadAddr { "lda">; def h : F_LADDR</*ty=*/ 0b10, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), "lda.h">; - let Predicates = [IsMC88100], DecoderNamespace = "MC88100" in + let Predicates = [NotMC88110] in def b : F_LADDR</*ty=*/ 0b11, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), "lda.b">; - let Predicates = [IsMC88110], DecoderNamespace = "MC88110" in + let Predicates = [MC88110], DecoderNamespace = "MC88110" in def x : F_LADDR</*ty=*/ 0b11, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), "lda.x">; } multiclass Xmem { -// TODO Same encoding as ld %x,%r,%i/ld.d %x,%r,%i -// let Predicates = [IsMC88100] in { -// def bi : F_XMEMIMM</*ty=*/ 0b00, -// (outs GPR:$rd), (ins GPR:$rs1, imm32zx16:$imm16), -// "xmem.bu">; -// def wi : F_XMEMIMM</*ty=*/ 0b01, -// (outs GPR:$rd), (ins GPR:$rs1, imm32zx16:$imm16), -// "xmem">; -// } + let Predicates = [NotMC88110] in { + def bi : F_XMEMIMM</*ty=*/ 0b00, + (outs GPR:$rd), (ins GPR:$rs1, imm32zx16:$imm16), + "xmem.bu">; + def wi : F_XMEMIMM</*ty=*/ 0b01, + (outs GPR:$rd), (ins GPR:$rs1, imm32zx16:$imm16), + "xmem">; + } foreach U = 0-1 in { defvar Suffix = !if(U, ".usr", ""); @@ -794,7 +795,7 @@ let mayLoad = 1 in { defm LDA : LoadAddr<>; // TODO Does inst touch memory? - let Predicates = [IsMC88110] in { + let Predicates = [MC88110], DecoderNamespace = "MC88110" in { def LDxri : LoadXR<0b000001, "ld", f32>; def LDxrid : LoadXR<0b000000, "ld.d", f64>; def LDxrix : LoadXR<0b001111, "ld.x", f80>; @@ -996,7 +997,7 @@ multiclass FArithX<bits<4> Func, string OpcStr> { foreach D = 0-2 in { foreach S1 = 0-2 in { foreach S2 = 0-2 in { - let regfile = 1, Predicates = [IsMC88110] in { + let regfile = 1, Predicates = [MC88110] in { defvar DPrec = getFT<D>.ret.prec; defvar S1Prec = getFT<S1>.ret.prec; defvar S2Prec = getFT<S2>.ret.prec; @@ -1029,7 +1030,7 @@ multiclass FArith2G<bits<4> Func, string OpcStr> { multiclass FArith2X<bits<4> Func, string OpcStr> { foreach S2 = 0-2 in { - let regfile = 1, Predicates = [IsMC88110] in { + let regfile = 1, Predicates = [MC88110] in { defvar S2Prec = getFT<S2>.ret.prec; def xs # S2Prec : F_SFU1D<Func, /*td=*/ 0b00, /*t1=*/ 0b00, /*t2=*/ S2, @@ -1068,7 +1069,7 @@ multiclass FUnaryX<bits<4> Func, string OpcStr, bit eq> { foreach S2 = 0-2 in { defvar IsLegal = !or(eq, !ne(D, S2)); if IsLegal then { - let regfile = 1, Predicates = [IsMC88110] in { + let regfile = 1, Predicates = [MC88110] in { defvar DPrec = getFT<D>.ret.prec; defvar S2Prec = getFT<S2>.ret.prec; def x # DPrec # S2Prec : @@ -1106,7 +1107,7 @@ multiclass FCmpG<bits<4> Func, bits<2> td, string OpcStr> { multiclass FCmpX<bits<4> Func, bits<2> td, string OpcStr> { foreach S1 = 0-2 in { foreach S2 = 0-2 in { - let regfile = 1, Predicates = [IsMC88110] in { + let regfile = 1, Predicates = [MC88110] in { defvar S1Prec = getFT<S1>.ret.prec; defvar S2Prec = getFT<S2>.ret.prec; def x # s # S1Prec # S2Prec : @@ -1165,7 +1166,7 @@ defm INT : FArith2<0b1001, "int">; defm NINT : FArith2<0b1010, "nint">; defm TRNC : FArith2<0b1011, "trnc">; -let Predicates = [IsMC88110] in { +let Predicates = [MC88110] in { defm FCVT : FUnary<0b0001, "fcvt", false>; defm FSQRT : FUnary<0b1111, "fsqrt", true>; @@ -1195,7 +1196,7 @@ def : Pat<(fpround (f64 GPR64:$rs1)), // Missing: fcmp, fcmpu defm FCMP : FCmp<0b0111, 0b00, "fcmp">; -let Predicates = [IsMC88110] in +let Predicates = [MC88110] in defm FCMPU : FCmp<0b0111, 0b01, "fcmpu">; let regfile = 0 in { @@ -1208,7 +1209,7 @@ def FLTgds : F_SFU1FLT</*td=*/ 0b01, "flt.ds", [(set (f64 GPR64:$rd), (sint_to_fp (i32 GPR:$rs2)))]>; } -let regfile = 1, Predicates = [IsMC88110] in { +let regfile = 1, Predicates = [MC88110] in { def FLTxss : F_SFU1FLT</*td=*/ 0b00, (outs XR:$rd), (ins GPR:$rs2), "flt.ss", @@ -1223,7 +1224,7 @@ def FLTxxs : F_SFU1FLT</*td=*/ 0b10, [(set (f80 XR:$rd), (sint_to_fp (i32 GPR:$rs2)))]>; } -let regfile = 1, isMoveReg = 1, Predicates = [IsMC88110] in { +let regfile = 1, isMoveReg = 1, Predicates = [MC88110] in { def MOVrxs : F_SFU1D<0b1000, /*td*/ 0b00, /*t1*/0b00, /*t2*/0b00, (outs GPR:$rd), (ins XR:$rs2), "mov.s", @@ -1238,7 +1239,7 @@ def MOVxx : F_SFU1D<0b1000, /*td*/ 0b00, /*t1*/0b01, /*t2*/0b11, // [(set XR:$rd, XR:$rs2)]>; } -let regfile = 0, isMoveReg = 1, Predicates = [IsMC88110] in { +let regfile = 0, isMoveReg = 1, Predicates = [MC88110] in { def MOVxrs : F_SFU1D<0b1000, /*td*/ 0b00, /*t1*/0b01, /*t2*/0b00, (outs XR:$rd), (ins GPR:$rs2), "mov.s", @@ -1344,7 +1345,7 @@ multiclass PPack { !strconcat(opc, ".8")>; } -let Predicates = [IsMC88110] in { +let Predicates = [Graphics] in { def PMUL : F_SFU2<0b00000, 0b00, 0b00, (outs GPR64:$rd), (ins GPR:$rs1, GPR64:$rs2), diff --git a/llvm/lib/Target/M88k/M88kSchedule.td b/llvm/lib/Target/M88k/M88kSchedule.td index fe20e6e..dc70c89 100644 --- a/llvm/lib/Target/M88k/M88kSchedule.td +++ b/llvm/lib/Target/M88k/M88kSchedule.td @@ -50,7 +50,7 @@ def M88110SchedModel : SchedMachineModel { // In-order CPU. let MicroOpBufferSize = 0; - list<Predicate> UnsupportedFeatures = [IsMC88110]; + list<Predicate> UnsupportedFeatures = [MC88110]; // Not finished yet. let CompleteModel = 0; diff --git a/llvm/lib/Target/M88k/M88kSubtarget.h b/llvm/lib/Target/M88k/M88kSubtarget.h index 146e01e..64cbebe 100644 --- a/llvm/lib/Target/M88k/M88kSubtarget.h +++ b/llvm/lib/Target/M88k/M88kSubtarget.h @@ -70,6 +70,14 @@ public: const std::string &TuneCPU, const std::string &FS, const TargetMachine &TM); +// Getters for SubtargetFeatures defined in tablegen +#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \ + bool GETTER() const { return ATTRIBUTE; } +#include "M88kGenSubtargetInfo.inc" + + bool isMC88100() const { return M88kProc == MC88100; } + bool isMC88110() const { return M88kProc == MC88110; } + // Automatically generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); @@ -78,9 +86,6 @@ public: Optional<unsigned> getCacheAssociativity(unsigned Level) const override; Optional<unsigned> getCacheLineSize(unsigned Level) const override; - bool isMC88100() const { return M88kProc == MC88100; } - bool isMC88110() const { return M88kProc == MC88110; } - const TargetFrameLowering *getFrameLowering() const override { return &FrameLowering; } diff --git a/llvm/test/MC/M88k/valid.s b/llvm/test/MC/M88k/valid.s index e1f1fcc..cff91cc 100644 --- a/llvm/test/MC/M88k/valid.s +++ b/llvm/test/MC/M88k/valid.s @@ -523,10 +523,11 @@ isns: # CHECK: ld.d.usr %r2, %r3[%r4] | encoding: [0xf4,0x43,0x13,0x04] # load address -# TODO ld.b %r0, %r1[%r2] + lda.b %r0, %r1[%r2] lda.h %r0, %r1[%r2] lda %r1, %r2[%r3] lda.d %r2, %r3[%r4] +# CHECK: lda.b %r0, %r1[%r2] | encoding: [0xf4,0x01,0x3e,0x02] # CHECK: lda.h %r0, %r1[%r2] | encoding: [0xf4,0x01,0x3a,0x02] # CHECK: lda %r1, %r2[%r3] | encoding: [0xf4,0x22,0x36,0x03] # CHECK: lda.d %r2, %r3[%r4] | encoding: [0xf4,0x43,0x32,0x04] @@ -732,10 +733,10 @@ isns: # CHECK: xcr %r0, %r3, %cr10 | encoding: [0x80,0x03,0xc1,0x43] # exchange register with memory -# xmem.bu %r0, %r1, 0 -# xmem.bu %r0, %r1, 10 -# xmem %r0, %r1, 0 -# xmem %r1, %r2, 4096 + xmem.bu %r0, %r1, 0 + xmem.bu %r0, %r1, 10 + xmem %r0, %r1, 0 + xmem %r1, %r2, 4096 xmem.bu %r0, %r1, %r2 xmem %r1, %r2, %r3 xmem.bu.usr %r4, %r5, %r6 @@ -744,10 +745,10 @@ isns: xmem %r3, %r4[%r5] xmem.bu.usr %r4, %r5[%r9] xmem.usr %r5, %r6[%r10] -# COM: CHECK: xmem.bu %r0, %r1, 0 | encoding: [0x] -# COM: CHECK: xmem.bu %r0, %r1, 10 | encoding: [0x] -# COM: CHECK: xmem %r0, %r1, 0 | encoding: [0x] -# COM: CHECK: xmem %r1, %r2, 4096 | encoding: [0x] +# CHECK: xmem.bu %r0, %r1, 0 | encoding: [0x00,0x01,0x00,0x00] +# CHECK: xmem.bu %r0, %r1, 10 | encoding: [0x00,0x01,0x00,0x0a] +# CHECK: xmem %r0, %r1, 0 | encoding: [0x04,0x01,0x00,0x00] +# CHECK: xmem %r1, %r2, 4096 | encoding: [0x04,0x22,0x10,0x00] # CHECK: xmem.bu %r0, %r1, %r2 | encoding: [0xf4,0x01,0x00,0x02] # CHECK: xmem %r1, %r2, %r3 | encoding: [0xf4,0x22,0x04,0x03] # CHECK: xmem.bu.usr %r4, %r5, %r6 | encoding: [0xf4,0x85,0x01,0x06] |