[m88k] Better legalization/selection for G_ZEXT

3 files changed, 67 insertions, 3 deletions

diff --git a/llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp b/llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp
index f2e510b..69f886d 100644
--- a/llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp
+++ b/llvm/lib/Target/M88k/GISel/M88kInstructionSelector.cpp
@@ -82,6 +82,8 @@ private:
                         MachineRegisterInfo &MRI) const;
   bool selectPtrAdd(MachineInstr &I, MachineBasicBlock &MBB,
                     MachineRegisterInfo &MRI) const;
+  bool selectExt(MachineInstr &I, MachineBasicBlock &MBB,
+                 MachineRegisterInfo &MRI) const;
   bool selectLoadStore(MachineInstr &I, MachineBasicBlock &MBB,
                        MachineRegisterInfo &MRI) const;
   bool selectMergeUnmerge(MachineInstr &I, MachineBasicBlock &MBB,
@@ -580,6 +582,57 @@ bool M88kInstructionSelector::selectPtrAdd(MachineInstr &I,
   return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
 }
 
+bool M88kInstructionSelector::selectExt(MachineInstr &I, MachineBasicBlock &MBB,
+                                        MachineRegisterInfo &MRI) const {
+  assert(I.getOpcode() == TargetOpcode::G_ZEXT ||
+         I.getOpcode() == TargetOpcode::G_ANYEXT ||
+         I.getOpcode() == TargetOpcode::G_SEXT && "Unexpected G code");
+
+  // Matches xEXT of ICMP.
+  MachineInstr *MI = nullptr;
+  Register DstReg = I.getOperand(0).getReg();
+  Register SrcReg = I.getOperand(1).getReg();
+  const unsigned NewOpc =
+      I.getOpcode() == TargetOpcode::G_SEXT ? M88k::EXTrwo : M88k::EXTUrwo;
+  CmpInst::Predicate Pred;
+  Register LHS, RHS;
+  int64_t SImm16;
+  if (mi_match(SrcReg, MRI,
+               m_GICmp(m_Pred(Pred), m_Reg(LHS), m_ICst(SImm16))) &&
+      isInt<16>(SImm16)) {
+    Register Temp = MRI.createVirtualRegister(&M88k::GPRRCRegClass);
+    ICC CCCode = getCCforICMP(Pred);
+    int64_t WO = (1 << 5) | int64_t(CCCode);
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::CMPri))
+             .addReg(Temp, RegState::Define)
+             .addReg(LHS)
+             .addImm(SImm16);
+    if (!constrainSelectedInstRegOperands(*MI, TII, TRI, RBI))
+      return false;
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc), DstReg)
+             .addReg(Temp, RegState::Kill)
+             .addImm(WO);
+  } else if (mi_match(SrcReg, MRI,
+                      m_GICmp(m_Pred(Pred), m_Reg(LHS), m_Reg(RHS)))) {
+    Register Temp = MRI.createVirtualRegister(&M88k::GPRRCRegClass);
+    ICC CCCode = getCCforICMP(Pred);
+    int64_t WO = (1 << 5) | int64_t(CCCode);
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(M88k::CMPrr))
+             .addReg(Temp, RegState::Define)
+             .addReg(LHS)
+             .addReg(RHS);
+    if (!constrainSelectedInstRegOperands(*MI, TII, TRI, RBI))
+      return false;
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc), DstReg)
+             .addReg(Temp, RegState::Kill)
+             .addImm(WO);
+  } else
+    return false;
+
+  I.eraseFromParent();
+  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
+}
+
 enum class LoadStore : unsigned {
   Imm = 0,
   RegUnscaled,
@@ -999,6 +1052,10 @@ bool M88kInstructionSelector::select(MachineInstr &I) {
     return selectBrJT(I, MBB, MRI);
   case TargetOpcode::G_BRINDIRECT:
     return selectBrIndirect(I, MBB, MRI);
+  case TargetOpcode::G_ZEXT:
+  case TargetOpcode::G_SEXT:
+  case TargetOpcode::G_ANYEXT: // TODO Can G_ANYEXT end up here?
+    return selectExt(I, MBB, MRI);
   case TargetOpcode::G_SEXTLOAD:
   case TargetOpcode::G_ZEXTLOAD:
   case TargetOpcode::G_LOAD:
diff --git a/llvm/lib/Target/M88k/GISel/M88kLegalizerInfo.cpp b/llvm/lib/Target/M88k/GISel/M88kLegalizerInfo.cpp
index 27a54b9..f64dc32 100644
--- a/llvm/lib/Target/M88k/GISel/M88kLegalizerInfo.cpp
+++ b/llvm/lib/Target/M88k/GISel/M88kLegalizerInfo.cpp
@@ -46,9 +46,11 @@ M88kLegalizerInfo::M88kLegalizerInfo(const M88kSubtarget &ST) {
   getActionDefinitionsBuilder(G_PTRTOINT)
       .legalFor({{S32, P0}})
       .minScalar(0, S32);
-  getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
-      .legalIf([](const LegalityQuery &Query) { return false; })
-      .maxScalar(0, S32);
+
+  getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
+      .legalFor({{S32, S16}, {S32, S8}, {S32, S1}})
+      .clampScalar(0, S32, S32)
+      .widenScalarToNextPow2(1, 32);
   getActionDefinitionsBuilder(G_SEXT_INREG).legalForTypeWithAnyImm({S32});
   getActionDefinitionsBuilder(G_TRUNC).alwaysLegal();
   getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
diff --git a/llvm/lib/Target/M88k/GISel/M88kRegisterBankInfo.cpp b/llvm/lib/Target/M88k/GISel/M88kRegisterBankInfo.cpp
index df79675..0d47d5c 100644
--- a/llvm/lib/Target/M88k/GISel/M88kRegisterBankInfo.cpp
+++ b/llvm/lib/Target/M88k/GISel/M88kRegisterBankInfo.cpp
@@ -201,6 +201,11 @@ M88kRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_TRUNC:
     OperandsMapping = getValueMapping(PMI_GR32);
     break;
+  case TargetOpcode::G_SEXT:
+  case TargetOpcode::G_ZEXT:
+  case TargetOpcode::G_ANYEXT:
+    OperandsMapping = getValueMapping(PMI_GR32);
+    break;
   case TargetOpcode::G_SEXT_INREG:
     OperandsMapping = getOperandsMapping(
         {getValueMapping(PMI_GR32), getValueMapping(PMI_GR32), nullptr});