[m88k] Legalize & select G_ROTR

The m88k architecture has a "rotate right" instruction.

- Legalize G_ROTR
- Lower G_ROTL, G_FSHL, G_FSHR
- Remove Legalizer info from PreLegalizerCombiner pass
- Extend PostLegalizerCombiner pass

The latter 2 bullets are neccessary to lower intrinsic llvm.fshl to
G_ROTR instruction, and create the right rotate amount.

5 files changed, 44 insertions, 8 deletions

diff --git a/llvm/lib/Target/M88k/GISel/M88kLegalizerInfo.cpp b/llvm/lib/Target/M88k/GISel/M88kLegalizerInfo.cpp
index b1d9b24..5cdee34 100644
--- a/llvm/lib/Target/M88k/GISel/M88kLegalizerInfo.cpp
+++ b/llvm/lib/Target/M88k/GISel/M88kLegalizerInfo.cpp
@@ -74,13 +74,13 @@ M88kLegalizerInfo::M88kLegalizerInfo(const M88kSubtarget &ST) {
       .clampScalar(0, S32, S32);
   getActionDefinitionsBuilder({G_SBFX, G_UBFX})
       .legalFor({{S32, S32}})
-      .clampScalar(2, S32, S32)
-      .clampScalar(1, S32, S32)
       .clampScalar(0, S32, S32);
   getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
       .legalFor({{S32, S32}})
       .clampScalar(0, S32, S32)
       .clampScalar(1, S32, S32);
+  getActionDefinitionsBuilder(G_ROTR).legalFor({{S32}, {S32}});
+  getActionDefinitionsBuilder({G_ROTL, G_FSHL, G_FSHR}).lower();
 
   getActionDefinitionsBuilder(G_ICMP)
       .legalForCartesianProduct({S1}, {S32, P0})
diff --git a/llvm/lib/Target/M88k/GISel/M88kPreLegalizerCombiner.cpp b/llvm/lib/Target/M88k/GISel/M88kPreLegalizerCombiner.cpp
index 23858ee..0eeaf59 100644
--- a/llvm/lib/Target/M88k/GISel/M88kPreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/M88k/GISel/M88kPreLegalizerCombiner.cpp
@@ -133,9 +133,7 @@ public:
 bool M88kPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
                                            MachineInstr &MI,
                                            MachineIRBuilder &B) const {
-  const auto *LI =
-      MI.getParent()->getParent()->getSubtarget().getLegalizerInfo();
-  CombinerHelper Helper(Observer, B, KB, MDT, LI);
+  CombinerHelper Helper(Observer, B, KB, MDT);
   M88kGenPreLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper);
 
   if (Generated.tryCombineAll(Observer, MI, B))
diff --git a/llvm/lib/Target/M88k/GISel/M88kRegisterBankInfo.cpp b/llvm/lib/Target/M88k/GISel/M88kRegisterBankInfo.cpp
index aa94900..2cf39e3 100644
--- a/llvm/lib/Target/M88k/GISel/M88kRegisterBankInfo.cpp
+++ b/llvm/lib/Target/M88k/GISel/M88kRegisterBankInfo.cpp
@@ -193,6 +193,11 @@ M88kRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
         {getValueMapping(PMI_GR32), getValueMapping(PMI_GR32),
          getValueMapping(PMI_GR32), getValueMapping(PMI_GR32)});
     break;
+  case TargetOpcode::G_ROTR:
+    OperandsMapping = getOperandsMapping({getValueMapping(PMI_GR32),
+                                          getValueMapping(PMI_GR32),
+                                          getValueMapping(PMI_GR32)});
+    break;
   case TargetOpcode::G_TRUNC:
     OperandsMapping = getValueMapping(PMI_GR32);
     break;
diff --git a/llvm/lib/Target/M88k/M88kCombine.td b/llvm/lib/Target/M88k/M88kCombine.td
index 91020f3..5dae3d8 100644
--- a/llvm/lib/Target/M88k/M88kCombine.td
+++ b/llvm/lib/Target/M88k/M88kCombine.td
@@ -36,7 +36,7 @@ def m88k_combines : GICombineGroup<[trivial_combines, combines_for_extload,
     unmerge_zext_to_zext, merge_unmerge, trunc_ext_fold, trunc_shl,
     const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
     shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine,
-    truncstore_merge, div_rem_to_divrem, funnel_shift_combines,
+    truncstore_merge, div_rem_to_divrem, funnel_shift_to_rotate, //funnel_shift_combines,
     form_bitfield_extract, constant_fold, fabs_fneg_fold,
     intdiv_combines, mulh_combines, redundant_neg_operands,
     and_or_disjoint_mask, bitfield_extract_from_and_ashr]>;
@@ -50,7 +50,10 @@ def M88kPreLegalizerCombinerHelper: GICombinerHelper<
 
 // Post-legalization combines which are primarily optimizations.
 def M88kPostLegalizerCombinerHelper: GICombinerHelper<
-  "M88kGenPostLegalizerCombinerHelper", []> {
+  "M88kGenPostLegalizerCombinerHelper", [
+  form_bitfield_extract, // Some rules require legalizer
+  rotate_out_of_range // Required for left rotates, which produce a negative constant
+  ]> {
   let DisableRuleOption = "m88kpostlegalizercombiner-disable-rule";
 //  let StateClass = "M88kPostLegalizerCombinerHelperState";
 //  let AdditionalArguments = [];
diff --git a/llvm/test/CodeGen/M88k/shift.ll b/llvm/test/CodeGen/M88k/shift.ll
index 421e204..914dd23 100644
--- a/llvm/test/CodeGen/M88k/shift.ll
+++ b/llvm/test/CodeGen/M88k/shift.ll
@@ -107,4 +107,34 @@ define i32 @f11(i32 %a) {
   %shl = shl i32 %a, 8
   %res = ashr i32 %shl, 16
   ret i32 %res
-}
\ No newline at end of file
+}
+
+; Check rotate right with constant.
+define i32 @f12(i32 %a) {
+; CHECK-LABEL: f12:
+; CHECK: jmp.n %r1
+; CHECK: rot %r2, %r2, <3>
+  %res = call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 3)
+  ret i32 %res
+}
+
+; Check rotate right with register operand.
+define i32 @f13(i32 %a, i32 %b) {
+; CHECK-LABEL: f13:
+; CHECK: jmp.n %r1
+; CHECK: rot %r2, %r2, %r3
+  %res = call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b)
+  ret i32 %res
+}
+
+; Check rotate left with constant.
+define i32 @f14(i32 %a) {
+; CHECK-LABEL: f14:
+; CHECK: jmp.n %r1
+; CHECK: rot %r2, %r2, <3>
+  %res = call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 29)
+  ret i32 %res
+}
+
+declare i32 @llvm.fshr.i32(i32, i32, i32)
+declare i32 @llvm.fshl.i32(i32, i32, i32)