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author | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-31 00:08:34 +0000 |
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committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-31 00:08:34 +0000 |
commit | bc405294f047be809dc58639ad4d4af692b8bfaa (patch) | |
tree | 1c77a1a9e06924b2e59bb622a0d69d917c30cb10 | |
parent | 34d2173abf14cf9712903af8273aef857ab30757 (diff) | |
download | llvm-bc405294f047be809dc58639ad4d4af692b8bfaa.zip llvm-bc405294f047be809dc58639ad4d4af692b8bfaa.tar.gz llvm-bc405294f047be809dc58639ad4d4af692b8bfaa.tar.bz2 |
[Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation.
llvm-svn: 225024
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 111 | ||||
-rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt | 10 | ||||
-rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt | 10 | ||||
-rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/xtype_mpy.txt | 4 |
4 files changed, 135 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index 6395485..07892ed 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -1637,6 +1637,117 @@ def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>; // XTYPE/ALU + //===----------------------------------------------------------------------===// +// Logical with-not instructions. +let validSubTargets = HasV4SubT, isCodeGenOnly = 0 in { + def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>; + def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>; +} + +let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in +def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), + "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> { + bits<5> Rd; + bits<5> Rs; + bits<5> Rt; + + let IClass = 0b1101; + let Inst{27-21} = 0b0101111; + let Inst{20-16} = Rs; + let Inst{12-8} = Rt; + let Inst{4-0} = Rd; +} +// Add and accumulate. +// Rd=add(Rs,add(Ru,#s6)) +let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6, + opExtendable = 3, isCodeGenOnly = 0 in +def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd), + (ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6), + "$Rd = add($Rs, add($Ru, #$s6))" , + [(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs), + (add (i32 IntRegs:$Ru), s6_16ExtPred:$s6)))], + "", ALU64_tc_2_SLOT23> { + bits<5> Rd; + bits<5> Rs; + bits<5> Ru; + bits<6> s6; + + let IClass = 0b1101; + + let Inst{27-23} = 0b10110; + let Inst{22-21} = s6{5-4}; + let Inst{20-16} = Rs; + let Inst{13} = s6{3}; + let Inst{12-8} = Rd; + let Inst{7-5} = s6{2-0}; + let Inst{4-0} = Ru; + } + +let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1, + opExtentBits = 6, opExtendable = 2, isCodeGenOnly = 0 in +def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd), + (ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru), + "$Rd = add($Rs, sub(#$s6, $Ru))", + [], "", ALU64_tc_2_SLOT23> { + bits<5> Rd; + bits<5> Rs; + bits<6> s6; + bits<5> Ru; + + let IClass = 0b1101; + + let Inst{27-23} = 0b10111; + let Inst{22-21} = s6{5-4}; + let Inst{20-16} = Rs; + let Inst{13} = s6{3}; + let Inst{12-8} = Rd; + let Inst{7-5} = s6{2-0}; + let Inst{4-0} = Ru; + } + +// Extract bitfield +// Rdd=extract(Rss,#u6,#U6) +// Rdd=extract(Rss,Rtt) +// Rd=extract(Rs,Rtt) +// Rd=extract(Rs,#u5,#U5) + +let isCodeGenOnly = 0 in { +def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>; +def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>; +} + +let hasNewValue = 1, isCodeGenOnly = 0 in { + def S4_extract_rp : T_S3op_extract<"extract", 0b01>; + def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>; +} + +let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF], isCodeGenOnly = 0 in { + def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>; + def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>; +} + +// Logical xor with xor accumulation. +// Rxx^=xor(Rss,Rtt) +let hasSideEffects = 0, isCodeGenOnly = 0 in +def M4_xor_xacc + : SInst <(outs DoubleRegs:$Rxx), + (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), + "$Rxx ^= xor($Rss, $Rtt)", + [(set (i64 DoubleRegs:$Rxx), + (xor (i64 DoubleRegs:$dst2), (xor (i64 DoubleRegs:$Rss), + (i64 DoubleRegs:$Rtt))))], + "$dst2 = $Rxx", S_3op_tc_1_SLOT23> { + bits<5> Rxx; + bits<5> Rss; + bits<5> Rtt; + + let IClass = 0b1100; + + let Inst{27-23} = 0b10101; + let Inst{20-16} = Rss; + let Inst{12-8} = Rtt; + let Inst{4-0} = Rxx; + } + // Add and accumulate. // Rd=add(Rs,add(Ru,#s6)) let isExtendable = 1, opExtendable = 3, isExtentSigned = 1, opExtentBits = 6, diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt index ea4b1812..ec9944bd 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt @@ -6,6 +6,10 @@ # CHECK: r17 = abs(r21) 0xb1 0xc0 0x95 0x8c # CHECK: r17 = abs(r21):sat +0xff 0xd1 0x35 0xdb +# CHECK: r17 = add(r21, add(r31, #23)) +0xff 0xd1 0xb5 0xdb +# CHECK: r17 = add(r21, sub(#23, r31)) 0xf1 0xc2 0x15 0xe2 # CHECK: r17 += add(r21, #23) 0xf1 0xc2 0x95 0xe2 @@ -52,8 +56,14 @@ # CHECK: r17:16 = add(r21:20, r31:30):raw:hi 0x10 0xde 0xf4 0xd3 # CHECK: r17:16 = and(r21:20, r31:30) +0x30 0xd4 0xfe 0xd3 +# CHECK: r17:16 = and(r21:20, ~r31:30) 0x50 0xde 0xf4 0xd3 # CHECK: r17:16 = or(r21:20, r31:30) +0x70 0xd4 0xfe 0xd3 +# CHECK: r17:16 = or(r21:20, ~r31:30) +0x10 0xde 0x94 0xca +# CHECK: r17:16 ^= xor(r21:20, r31:30) 0x71 0xdf 0x95 0xef # CHECK: r17 ^= xor(r21, r31) 0x11 0xdf 0xd5 0xd5 diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt index 7256c5d..601b3e1 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_bit.txt @@ -20,12 +20,20 @@ # CHECK: r17 = ct1(r21) 0xf0 0xdf 0x54 0x81 # CHECK: r17:16 = extractu(r21:20, #31, #23) +0xf0 0xdf 0x54 0x8a +# CHECK: r17:16 = extract(r21:20, #31, #23) 0xf1 0xdf 0x55 0x8d # CHECK: r17 = extractu(r21, #31, #23) +0xf1 0xdf 0xd5 0x8d +# CHECK: r17 = extract(r21, #31, #23) 0x10 0xde 0x14 0xc1 # CHECK: r17:16 = extractu(r21:20, r31:30) +0x90 0xde 0xd4 0xc1 +# CHECK: r17:16 = extract(r21:20, r31:30) 0x11 0xde 0x15 0xc9 # CHECK: r17 = extractu(r21, r31:30) +0x51 0xde 0x15 0xc9 +# CHECK: r17 = extract(r21, r31:30) 0xf0 0xdf 0x54 0x83 # CHECK: r17:16 = insert(r21:20, #31, #23) 0xf1 0xdf 0x55 0x8f @@ -42,6 +50,8 @@ # CHECK: r17:16 = lfs(r21:20, r31:30) 0x11 0xde 0x14 0xd0 # CHECK: r17 = parity(r21:20, r31:30) +0x11 0xdf 0xf5 0xd5 +# CHECK: r17 = parity(r21, r31) 0x11 0xdf 0xd5 0x8c # CHECK: r17 = setbit(r21, #31) 0x31 0xdf 0xd5 0x8c diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_mpy.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_mpy.txt index 774f958..f69e409 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_mpy.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_mpy.txt @@ -174,6 +174,10 @@ # CHECK: r17 = mpy(r21, r31.h):<<1:rnd:sat 0x91 0xdf 0xf5 0xed # CHECK: r17 = mpy(r21, r31.l):<<1:rnd:sat +0x11 0xdf 0x75 0xef +# CHECK: r17 += mpy(r21, r31):<<1:sat +0x31 0xdf 0x75 0xef +# CHECK: r17 -= mpy(r21, r31):<<1:sat 0x10 0xdf 0x15 0xe5 # CHECK: r17:16 = mpy(r21, r31) 0x10 0xdf 0x55 0xe5 |