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| author | Pawel Wodnicki <pawel@32bitmicro.com> | 2012-11-19 22:31:55 +0000 |
|---|---|---|
| committer | Pawel Wodnicki <pawel@32bitmicro.com> | 2012-11-19 22:31:55 +0000 |
| commit | 3eca4fe7cdfd3c9f29794161750e1097a507dd9f (patch) | |
| tree | 5e039fad22b1385bf0e69fecd4b3a6112274bb84 | |
| parent | 4041ed4075110d3366e767c41265cae59f436023 (diff) | |
| download | llvm-3eca4fe7cdfd3c9f29794161750e1097a507dd9f.zip llvm-3eca4fe7cdfd3c9f29794161750e1097a507dd9f.tar.gz llvm-3eca4fe7cdfd3c9f29794161750e1097a507dd9f.tar.bz2 | |
Merging r167718 into 3.2 release branch
Fix PR14314
- Fix operand order for atomic sub, where the minuend is the value
loaded from memory and the subtrahend is the parameter specified.
llvm-svn: 168336
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/pr14314.ll | 13 |
3 files changed, 19 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 1f729e3..b35fb51 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -12729,8 +12729,8 @@ X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI, case X86::ATOMSUB6432: { unsigned HiOpc; unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc); - BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg).addReg(LoReg); - BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg).addReg(HiReg); + BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(LoReg).addReg(SrcLoReg); + BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(HiReg).addReg(SrcHiReg); break; } case X86::ATOMNAND6432: { diff --git a/llvm/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll b/llvm/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll index 7d1cda3..3d058bc 100644 --- a/llvm/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll +++ b/llvm/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll @@ -10,10 +10,10 @@ entry: ; CHECK: movl ([[REG:%[a-z]+]]), %eax ; CHECK: movl 4([[REG]]), %edx ; CHECK: LBB0_1: -; CHECK: movl $1 -; CHECK: addl -; CHECK: movl $0 -; CHECK: adcl +; CHECK: movl %eax, %ebx +; CHECK: addl {{%[a-z]+}}, %ebx +; CHECK: movl %edx, %ecx +; CHECK: adcl {{%[a-z]+}}, %ecx ; CHECK: lock ; CHECK-NEXT: cmpxchg8b ([[REG]]) ; CHECK-NEXT: jne diff --git a/llvm/test/CodeGen/X86/pr14314.ll b/llvm/test/CodeGen/X86/pr14314.ll new file mode 100644 index 0000000..5388a4b --- /dev/null +++ b/llvm/test/CodeGen/X86/pr14314.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -mtriple=i386-pc-linux -mcpu=corei7 | FileCheck %s + +define i64 @atomicSub(i64* %a, i64 %b) nounwind { +entry: + %0 = atomicrmw sub i64* %a, i64 %b seq_cst + ret i64 %0 +; CHECK: atomicSub +; movl %eax, %ebx +; subl {{%[a-z]+}}, %ebx +; movl %edx, %ecx +; sbbl {{%[a-z]+}}, %ecx +; CHECK: ret +} |