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authorBill Wendling <isanbard@gmail.com>2010-09-29 23:07:19 +0000
committerBill Wendling <isanbard@gmail.com>2010-09-29 23:07:19 +0000
commit48545b3af641c79876650fcc6cf50e894f5b0587 (patch)
treeda6c77ed686fd78ac6337f2ac0648ec765bebf51
parent31ee1f90567735fbdb39d0ee60b41a35e4f8595c (diff)
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Merge in r114506.
llvm-svn: 115101
-rw-r--r--llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 3a8bebe..e4f10f9 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1389,7 +1389,8 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const {
// Check that CPSR isn't set between the comparison instruction and the one we
// want to change.
- MachineBasicBlock::const_iterator I = CmpInstr, E = MI;
+ MachineBasicBlock::const_iterator I = CmpInstr, E = MI,
+ B = MI->getParent()->begin();
--I;
for (; I != E; --I) {
const MachineInstr &Instr = *I;
@@ -1403,6 +1404,10 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const {
if (MO.getReg() == ARM::CPSR)
return false;
}
+
+ if (I == B)
+ // The 'and' is below the comparison instruction.
+ return false;
}
// Set the "zero" bit in CPSR.