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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2023-07-25 07:50:08 -0400 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2023-07-25 07:54:11 -0400 |
| commit | 395cd33ba850989209834a2e332d21b42168cfaf (patch) | |
| tree | 959ba8b80e7c20eed4903762c8ca63cbbce11763 | |
| parent | e3fd8f83a801b1918508c7c0a71cc31bc95ad4d2 (diff) | |
| download | llvm-395cd33ba850989209834a2e332d21b42168cfaf.zip llvm-395cd33ba850989209834a2e332d21b42168cfaf.tar.gz llvm-395cd33ba850989209834a2e332d21b42168cfaf.tar.bz2 | |
AMDGPU: Remove trailing whitespace from documentation
| -rw-r--r-- | llvm/docs/AMDGPUUsage.rst | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index d90c83f..0a7ae20 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -999,21 +999,21 @@ The AMDGPU backend implements the following LLVM IR intrinsics. marked with the :ref:`afn <fastmath_afn>` flag. llvm.amdgcn.wave.reduce.umin Performs an arithmetic unsigned min reduction on the unsigned values - provided by each lane in the wavefront. + provided by each lane in the wavefront. Intrinsic takes a hint for reduction strategy using second operand 0: Target default preference, 1: `Iterative strategy`, and - 2: `DPP`. + 2: `DPP`. If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. Intrinsic is currently only implemented for i32. - llvm.amdgcn.wave.reduce.umax Performs an arithmetic unsigned max reduction on the unsigned values + llvm.amdgcn.wave.reduce.umax Performs an arithmetic unsigned max reduction on the unsigned values provided by each lane in the wavefront. Intrinsic takes a hint for reduction strategy using second operand 0: Target default preference, 1: `Iterative strategy`, and - 2: `DPP`. + 2: `DPP`. If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. Intrinsic is currently only implemented for i32. |