[Analysis][LoongArch] Add sign extension for i32 parameters and returns

In LoongArch ABI spec, we can see that in the LP64D ABI, unsigned 32-bit
types, such as unsigned int, are stored in general-purpose registers as
proper sign extensions of their 32-bit values.

Reference:
https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html#_abi_lp64d

Reviewed By: SixWeining, xen0n

Differential Revision: https://reviews.llvm.org/D151794

(cherry picked from commit fe6716a49850be09291f0eded6fb8ffa9f5cc651)

4 files changed, 26 insertions, 9 deletions

diff --git a/llvm/include/llvm/Analysis/TargetLibraryInfo.h b/llvm/include/llvm/Analysis/TargetLibraryInfo.h
index 8fcfbdb..951945f 100644
--- a/llvm/include/llvm/Analysis/TargetLibraryInfo.h
+++ b/llvm/include/llvm/Analysis/TargetLibraryInfo.h
@@ -408,14 +408,14 @@ public:
       ShouldExtI32Param = true;
       ShouldExtI32Return = true;
     }
-    // Mips and riscv64, on the other hand, needs signext on i32 parameters
-    // corresponding to both signed and unsigned ints.
-    if (T.isMIPS() || T.isRISCV64()) {
+    // LoongArch, Mips, and riscv64, on the other hand, need signext on i32
+    // parameters corresponding to both signed and unsigned ints.
+    if (T.isLoongArch() || T.isMIPS() || T.isRISCV64()) {
       ShouldSignExtI32Param = true;
     }
-    // riscv64 needs signext on i32 returns corresponding to both signed and
-    // unsigned ints.
-    if (T.isRISCV64()) {
+    // LoongArch and riscv64 need signext on i32 returns corresponding to both
+    // signed and unsigned ints.
+    if (T.isLoongArch() || T.isRISCV64()) {
       ShouldSignExtI32Return = true;
     }
   }
diff --git a/llvm/test/Instrumentation/AddressSanitizer/experiment.ll b/llvm/test/Instrumentation/AddressSanitizer/experiment.ll
index 5d1c5a2..e18df61 100644
--- a/llvm/test/Instrumentation/AddressSanitizer/experiment.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/experiment.ll
@@ -3,7 +3,8 @@
 ; RUN: opt < %s -passes=asan -asan-force-experiment=42 -S | FileCheck %s
 ; RUN: opt < %s -passes=asan -asan-force-experiment=42 -S -mtriple=s390x-unknown-linux | FileCheck %s --check-prefix=EXT
 ; RUN: opt < %s -passes=asan -asan-force-experiment=42 -S -mtriple=mips-linux-gnu | FileCheck %s --check-prefix=MIPS_EXT
-; REQUIRES: x86-registered-target, systemz-registered-target, mips-registered-target
+; RUN: opt < %s -passes=asan -asan-force-experiment=42 -S -mtriple=loongarch64-unknown-linux-gnu | FileCheck %s --check-prefix=LA_EXT
+; REQUIRES: x86-registered-target, systemz-registered-target, mips-registered-target, loongarch-registered-target
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-unknown-linux-gnu"
@@ -119,15 +120,19 @@ entry:
 ; CHECK:    declare void @__asan_report_exp_load_n(i64, i64, i32)
 ; EXT:      declare void @__asan_report_exp_load_n(i64, i64, i32 zeroext)
 ; MIPS_EXT: declare void @__asan_report_exp_load_n(i64, i64, i32 signext)
+; LA_EXT:   declare void @__asan_report_exp_load_n(i64, i64, i32 signext)
 
 ; CHECK:    declare void @__asan_exp_loadN(i64, i64, i32)
 ; EXT:      declare void @__asan_exp_loadN(i64, i64, i32 zeroext)
 ; MIPS_EXT: declare void @__asan_exp_loadN(i64, i64, i32 signext)
+; LA_EXT:   declare void @__asan_exp_loadN(i64, i64, i32 signext)
 
 ; CHECK:    declare void @__asan_report_exp_load1(i64, i32)
 ; EXT:      declare void @__asan_report_exp_load1(i64, i32 zeroext)
 ; MIPS_EXT: declare void @__asan_report_exp_load1(i64, i32 signext)
+; LA_EXT:   declare void @__asan_report_exp_load1(i64, i32 signext)
 
 ; CHECK:    declare void @__asan_exp_load1(i64, i32)
 ; EXT:      declare void @__asan_exp_load1(i64, i32 zeroext)
 ; MIPS_EXT: declare void @__asan_exp_load1(i64, i32 signext)
+; LA_EXT:   declare void @__asan_exp_load1(i64, i32 signext)
diff --git a/llvm/test/Instrumentation/AddressSanitizer/mem-intrinsics.ll b/llvm/test/Instrumentation/AddressSanitizer/mem-intrinsics.ll
index c9d3132..67ef8d1 100644
--- a/llvm/test/Instrumentation/AddressSanitizer/mem-intrinsics.ll
+++ b/llvm/test/Instrumentation/AddressSanitizer/mem-intrinsics.ll
@@ -5,7 +5,8 @@
 ; RUN: opt < %s -passes=asan -asan-kernel -asan-kernel-mem-intrinsic-prefix -S | FileCheck --check-prefixes=CHECK,CHECK-PREFIX %s
 ; RUN: opt < %s -passes=asan -S -mtriple=s390x-unknown-linux | FileCheck --check-prefix=EXT %s
 ; RUN: opt < %s -passes=asan -S -mtriple=mips-linux-gnu | FileCheck --check-prefix=MIPS_EXT %s
-; REQUIRES: x86-registered-target, systemz-registered-target, mips-registered-target
+; RUN: opt < %s -passes=asan -S -mtriple=loongarch64-unknown-linux-gnu | FileCheck --check-prefix=LA_EXT %s
+; REQUIRES: x86-registered-target, systemz-registered-target, mips-registered-target, loongarch-registered-target
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-unknown-linux-gnu"
@@ -80,3 +81,4 @@ define void @memintr_element_atomic_test(ptr %a, ptr %b) nounwind uwtable saniti
 ; CHECK-PREFIX: declare ptr @__asan_memset(ptr, i32, i64)
 ; EXT:          declare ptr @__asan_memset(ptr, i32 zeroext, i64)
 ; MIPS_EXT:     declare ptr @__asan_memset(ptr, i32 signext, i64)
+; LA_EXT:       declare ptr @__asan_memset(ptr, i32 signext, i64)
diff --git a/llvm/test/Instrumentation/ThreadSanitizer/atomic.ll b/llvm/test/Instrumentation/ThreadSanitizer/atomic.ll
index 0312aa1..76afc4b 100644
--- a/llvm/test/Instrumentation/ThreadSanitizer/atomic.ll
+++ b/llvm/test/Instrumentation/ThreadSanitizer/atomic.ll
@@ -1,7 +1,8 @@
 ; RUN: opt < %s -passes=tsan -S | FileCheck %s
 ; RUN: opt < %s -passes=tsan -S -mtriple=s390x-unknown-linux | FileCheck --check-prefix=EXT %s
 ; RUN: opt < %s -passes=tsan -S -mtriple=mips-linux-gnu | FileCheck --check-prefix=MIPS_EXT %s
-; REQUIRES: x86-registered-target, systemz-registered-target, mips-registered-target
+; RUN: opt < %s -passes=tsan -S -mtriple=loongarch64-unknown-linux-gnu | FileCheck --check-prefix=LA_EXT %s
+; REQUIRES: x86-registered-target, systemz-registered-target, mips-registered-target, loongarch-registered-target
 ; Check that atomic memory operations are converted to calls into ThreadSanitizer runtime.
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 
@@ -2102,38 +2103,47 @@ entry:
 ; CHECK:    declare void @__tsan_atomic32_store(ptr, i32, i32)
 ; EXT:      declare void @__tsan_atomic32_store(ptr, i32 signext, i32 signext)
 ; MIPS_EXT: declare void @__tsan_atomic32_store(ptr, i32 signext, i32 signext)
+; LA_EXT:   declare void @__tsan_atomic32_store(ptr, i32 signext, i32 signext)
 
 ; CHECK:    declare i32 @__tsan_atomic32_compare_exchange_val(ptr, i32, i32, i32, i32)
 ; EXT:      declare signext i32 @__tsan_atomic32_compare_exchange_val(ptr, i32 signext, i32 signext, i32 signext, i32 signext)
 ; MIPS_EXT: declare i32 @__tsan_atomic32_compare_exchange_val(ptr, i32 signext, i32 signext, i32 signext, i32 signext)
+; LA_EXT:   declare signext i32 @__tsan_atomic32_compare_exchange_val(ptr, i32 signext, i32 signext, i32 signext, i32 signext)
 
 ; CHECK:    declare i64 @__tsan_atomic64_load(ptr, i32)
 ; EXT:      declare i64 @__tsan_atomic64_load(ptr, i32 signext)
 ; MIPS_EXT: declare i64 @__tsan_atomic64_load(ptr, i32 signext)
+; LA_EXT:   declare i64 @__tsan_atomic64_load(ptr, i32 signext)
 
 ; CHECK:    declare void @__tsan_atomic64_store(ptr, i64, i32)
 ; EXT:      declare void @__tsan_atomic64_store(ptr, i64, i32 signext)
 ; MIPS_EXT: declare void @__tsan_atomic64_store(ptr, i64, i32 signext)
+; LA_EXT:   declare void @__tsan_atomic64_store(ptr, i64, i32 signext)
 
 ; CHECK:    declare i64 @__tsan_atomic64_fetch_add(ptr, i64, i32)
 ; EXT:      declare i64 @__tsan_atomic64_fetch_add(ptr, i64, i32 signext)
 ; MIPS_EXT: declare i64 @__tsan_atomic64_fetch_add(ptr, i64, i32 signext)
+; LA_EXT:   declare i64 @__tsan_atomic64_fetch_add(ptr, i64, i32 signext)
 
 ; CHECK:    declare i64 @__tsan_atomic64_compare_exchange_val(ptr, i64, i64, i32, i32)
 ; EXT:      declare i64 @__tsan_atomic64_compare_exchange_val(ptr, i64, i64, i32 signext, i32 signext)
 ; MIPS_EXT: declare i64 @__tsan_atomic64_compare_exchange_val(ptr, i64, i64, i32 signext, i32 signext)
+; LA_EXT:   declare i64 @__tsan_atomic64_compare_exchange_val(ptr, i64, i64, i32 signext, i32 signext)
 
 ; CHECK:    declare void @__tsan_atomic_thread_fence(i32)
 ; EXT:      declare void @__tsan_atomic_thread_fence(i32 signext)
 ; MIPS_EXT: declare void @__tsan_atomic_thread_fence(i32 signext)
+; LA_EXT:   declare void @__tsan_atomic_thread_fence(i32 signext)
 
 ; CHECK:    declare void @__tsan_atomic_signal_fence(i32)
 ; EXT:      declare void @__tsan_atomic_signal_fence(i32 signext)
 ; MIPS_EXT: declare void @__tsan_atomic_signal_fence(i32 signext)
+; LA_EXT:   declare void @__tsan_atomic_signal_fence(i32 signext)
 
 ; CHECK:    declare ptr @__tsan_memset(ptr, i32, i64)
 ; EXT:      declare ptr @__tsan_memset(ptr, i32 signext, i64)
 ; MIPS_EXT: declare ptr @__tsan_memset(ptr, i32 signext, i64)
+; LA_EXT:   declare ptr @__tsan_memset(ptr, i32 signext, i64)
 
 !llvm.module.flags = !{!0, !1, !2}
 !llvm.dbg.cu = !{!8}