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| author | Craig Topper <craig.topper@intel.com> | 2020-07-15 15:14:46 -0700 |
|---|---|---|
| committer | Hans Wennborg <hans@chromium.org> | 2020-07-20 15:44:42 +0200 |
| commit | 2d499d7912ac83ff7a943b9061a557c759176fe6 (patch) | |
| tree | 21dee2a01b62fcbf5e49819a26b5e897cb3bf1eb | |
| parent | 76c22b392f18e533262de8db2fec5e6e25e0bd8b (diff) | |
| download | llvm-2d499d7912ac83ff7a943b9061a557c759176fe6.zip llvm-2d499d7912ac83ff7a943b9061a557c759176fe6.tar.gz llvm-2d499d7912ac83ff7a943b9061a557c759176fe6.tar.bz2 | |
[X86] Teach assembler parser to accept lsl and lar with a 64 or 32 source register when the destination is a 64 register.
Previously we only accepted a 32-bit source with a 64-bit dest.
Accepting 64-bit as well is more consistent with gas behavior. I
think maybe we should accept 16 bit register as well, but I'm not
sure.
(cherry picked from commit 3c2a56a857227b6bc39285747269f02cd7a9dbe5)
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSystem.td | 4 | ||||
| -rw-r--r-- | llvm/test/MC/X86/I286-64.s | 8 |
2 files changed, 10 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td index c23bc7e..d5f1064 100644 --- a/llvm/lib/Target/X86/X86InstrSystem.td +++ b/llvm/lib/Target/X86/X86InstrSystem.td @@ -223,7 +223,7 @@ def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), let mayLoad = 1 in def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; -def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), +def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32orGR64:$src), "lar{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; // i16mem operand in LSL32rm and GR32 operand in LSL32rr is not a typo. @@ -245,7 +245,7 @@ def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), let mayLoad = 1 in def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; -def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src), +def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR32orGR64:$src), "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB, NotMemoryFoldable; def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB; diff --git a/llvm/test/MC/X86/I286-64.s b/llvm/test/MC/X86/I286-64.s index 73376de..1bab0a6 100644 --- a/llvm/test/MC/X86/I286-64.s +++ b/llvm/test/MC/X86/I286-64.s @@ -32,6 +32,10 @@ larl %r13d, %r13d // CHECK: encoding: [0x44,0x0f,0x02,0x2a] larl (%rdx), %r13d +// CHECK: larq %eax, %rax +// CHECK: encoding: [0x48,0x0f,0x02,0xc0] +lar %rax, %rax + // CHECK: lgdtq 485498096 // CHECK: encoding: [0x0f,0x01,0x14,0x25,0xf0,0x1c,0xf0,0x1c] lgdtq 485498096 @@ -164,6 +168,10 @@ lsll %r13d, %r13d // CHECK: encoding: [0x44,0x0f,0x03,0x2a] lsll (%rdx), %r13d +// CHECK: lslq %eax, %rax +// CHECK: encoding: [0x48,0x0f,0x03,0xc0] +lsl %rax, %rax + // CHECK: ltrw 485498096 // CHECK: encoding: [0x0f,0x00,0x1c,0x25,0xf0,0x1c,0xf0,0x1c] ltrw 485498096 |