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| author | Philip Reames <preames@rivosinc.com> | 2023-09-15 12:31:26 -0700 |
|---|---|---|
| committer | Philip Reames <listmail@philipreames.com> | 2023-09-15 12:33:21 -0700 |
| commit | 52b33ff760b01e73dc4a0960f97812f9effe18f3 (patch) | |
| tree | d7b1fd969c64b87b39532f411d7fe4576cacc4c9 | |
| parent | 68033aaac5c94d1199e6cc3e6406e4d3fa10b040 (diff) | |
| download | llvm-52b33ff760b01e73dc4a0960f97812f9effe18f3.zip llvm-52b33ff760b01e73dc4a0960f97812f9effe18f3.tar.gz llvm-52b33ff760b01e73dc4a0960f97812f9effe18f3.tar.bz2 | |
[RISCV] Avoid toggling VL for hidden splat case in constant buildvector lowering
We have the analogous case in the single insert path. The reasoning here is that if the original VL fits in LMUL1, we'd prefer to clobber a few extra dead lanes than to force two VL toggles. VTYPE toggles are generally cheaper than VL toggles.
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 14 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll | 6 |
2 files changed, 15 insertions, 5 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index a89961d..605547a 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -3456,11 +3456,19 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG, (Sequence.size() * EltBitSize) <= 64) { unsigned SeqLen = Sequence.size(); MVT ViaIntVT = MVT::getIntegerVT(EltBitSize * SeqLen); - MVT ViaVecVT = MVT::getVectorVT(ViaIntVT, NumElts / SeqLen); assert((ViaIntVT == MVT::i16 || ViaIntVT == MVT::i32 || ViaIntVT == MVT::i64) && "Unexpected sequence type"); + // If we can use the original VL with the modified element type, this + // means we only have a VTYPE toggle, not a VL toggle. TODO: Should this + // be moved into InsertVSETVLI? + const unsigned RequiredVL = NumElts / SeqLen; + const unsigned ViaVecLen = + (Subtarget.getRealMinVLen() >= ViaIntVT.getSizeInBits() * NumElts) ? + NumElts : RequiredVL; + MVT ViaVecVT = MVT::getVectorVT(ViaIntVT, ViaVecLen); + unsigned EltIdx = 0; uint64_t EltMask = maskTrailingOnes<uint64_t>(EltBitSize); uint64_t SplatValue = 0; @@ -3494,6 +3502,10 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG, DAG.getUNDEF(ViaContainerVT), DAG.getConstant(SplatValue, DL, XLenVT), ViaVL); Splat = convertFromScalableVector(ViaVecVT, Splat, DAG, Subtarget); + if (ViaVecLen != RequiredVL) + Splat = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, + MVT::getVectorVT(ViaIntVT, RequiredVL), Splat, + DAG.getConstant(0, DL, XLenVT)); return DAG.getBitcast(VT, Splat); } } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll index 63d6de7..79947ca 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll @@ -518,9 +518,8 @@ define void @buildvec_seq_v8i8_v4i16(ptr %x) { ; CHECK-LABEL: buildvec_seq_v8i8_v4i16: ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, 513 -; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vmv.v.x v8, a1 -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vse8.v v8, (a0) ; CHECK-NEXT: ret store <8 x i8> <i8 1, i8 2, i8 1, i8 2, i8 1, i8 2, i8 undef, i8 2>, ptr %x @@ -623,9 +622,8 @@ define void @buildvec_seq_v4i16_v2i32(ptr %x) { ; CHECK-LABEL: buildvec_seq_v4i16_v2i32: ; CHECK: # %bb.0: ; CHECK-NEXT: li a1, -127 -; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma +; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vmv.v.x v8, a1 -; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret store <4 x i16> <i16 -127, i16 -1, i16 -127, i16 -1>, ptr %x |