From 3c0c78afabfed4b6fc161c159e628fbf14ff370b Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Mon, 3 Oct 2022 23:46:11 +0200 Subject: x86-64: Require BMI2 and LZCNT for AVX2 memrchr implementation The AVX2 memrchr implementation uses the 'shlxl' instruction, which belongs to the BMI2 CPU feature and uses the 'lzcnt' instruction, which belongs to the LZCNT CPU feature. Fixes: af5306a735eb ("x86: Optimize memrchr-avx2.S") Partially resolves: BZ #29611 Reviewed-by: Noah Goldstein --- sysdeps/x86/isa-level.h | 1 + 1 file changed, 1 insertion(+) (limited to 'sysdeps/x86/isa-level.h') diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h index 3c4480a..bbb90f5 100644 --- a/sysdeps/x86/isa-level.h +++ b/sysdeps/x86/isa-level.h @@ -80,6 +80,7 @@ #define AVX_X86_ISA_LEVEL 3 #define AVX2_X86_ISA_LEVEL 3 #define BMI2_X86_ISA_LEVEL 3 +#define LZCNT_X86_ISA_LEVEL 3 #define MOVBE_X86_ISA_LEVEL 3 /* ISA level >= 2 guaranteed includes. */ -- cgit v1.1