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2017-03-20posix_spawn: fix stack setup on ia64 [BZ #21275]gentoo/2.24Mike Frysinger1-5/+6
The ia64-specific clone2 call expects the base of the stack mapping and the stack size as sep arguments, not an initial stack value as on other stack-grows-down architectures. Reuse the stack-grows-up macro so we pass in the right stack base. Reported-by: Matt Turner <mattst88@gentoo.org> (cherry picked from commit ddc3fb333469c2997798742dc0509dc1e3201d91) (cherry picked from commit 7043946c7921c0e3850dd2b3d948336624bb0f62)
2017-02-09X86_64: Don't use PLT nor GOT in static archives [BZ #20750]H.J. Lu1-1/+2
There is no need to use PLT nor GOT in static archives to branch to a function, regardless whether static archives is compiled with PIC or not. When static archives are used to create dynamic executable, PLT/GOT may be used. The resulting executable still works correctly. [BZ #20750] * sysdeps/x86_64/sysdep.h (JUMPTARGET): Check SHARED instead of PIC. (cherry picked from commit c9070e6305c08365c5f8b604bdca39c699d70cfa) (cherry picked from commit d012ea850680a2a94959f1c5136502a0f712b30a)
2017-02-09Drop GLIBC_TUNABLES in setxid processesSiddhesh Poyarekar1-0/+1
Drop the GLIBC_TUNABLES environment variable from the environment of setxid processes to avoid passing it on to non-setxid children. This prevents potentially insecure tunables in the GLIBC_TUNABLES envvar from crossing over into a child that may use a libc that has tunables support. * sysdeps/generic/unsecvars.h: Add GLIBC_TUNABLES. (cherry picked from commit 537a06fbdeb9a6c2184c745c15ef3346681f5eeb)
2017-02-09powerpc: Fix write-after-destroy in lock elision [BZ #20822]Tulio Magno Quites Machado Filho3-12/+20
The update of *adapt_count after the release of the lock causes a race condition when thread A unlocks, thread B continues and destroys the mutex, and thread A writes to *adapt_count. (cherry picked from commit e9a96ea1aca4ebaa7c86e8b83b766f118d689d0f) (with changes from commit eb1321f291515dae75c83a40c39e775fdd38e97a) (cherry picked from commit 2762a7145bba9681b30ed5d4aed0c5d1df4329c8)
2016-12-08alpha: fix trunc for big input valuesAurelien Jarno2-8/+6
The alpha specific version of trunc and truncf always add and subtract 0x1.0p23 or 0x1.0p52 even for big values. This causes this kind of errors in the testsuite: Failure: Test: trunc_towardzero (0x1p107) Result: is: 1.6225927682921334e+32 0x1.fffffffffffffp+106 should be: 1.6225927682921336e+32 0x1.0000000000000p+107 difference: 1.8014398509481984e+16 0x1.0000000000000p+54 ulp : 0.5000 max.ulp : 0.0000 Change this by returning the input value when its absolute value is greater than 0x1.0p23 or 0x1.0p52. NaN have to go through the add and subtract operations to get possibly silenced. Finally remove the code to handle inexact exception, trunc should never generate such an exception. Changelog: * sysdeps/alpha/fpu/s_trunc.c (__trunc): Return the input value when its absolute value is greater than 0x1.0p52. [_IEEE_FP_INEXACT] Remove. * sysdeps/alpha/fpu/s_truncf.c (__truncf): Return the input value when its absolute value is greater than 0x1.0p23. [_IEEE_FP_INEXACT] Remove. (cherry picked from commit b74d259fe793499134eb743222cd8dd7c74a31ce) (cherry picked from commit e6eab16cc302e6c42f79e1af02ce98ebb9a783bc)
2016-12-08alpha: fix rint on sNaN inputAurelien Jarno2-0/+6
The alpha version of rint wrongly return sNaN for sNaN input. Fix that by checking for NaN and by returning the input value added with itself in that case. Changelog: * sysdeps/alpha/fpu/s_rint.c (__rint): Add argument with itself when it is a NaN. * sysdeps/alpha/fpu/s_rintf.c (__rintf): Likewise. (cherry picked from commit cb7f9d63b921ea1a1cbb4ab377a8484fd5da9a2b) (cherry picked from commit 8eb9a92e0522f2d4f2d4167df919d066c85d3408)
2016-12-08alpha: fix floor on sNaN inputAurelien Jarno2-8/+6
The alpha version of floor wrongly return sNaN for sNaN input. Fix that by checking for NaN and by returning the input value added with itself in that case. Finally remove the code to handle inexact exception, floor should never generate such an exception. Changelog: * sysdeps/alpha/fpu/s_floor.c (__floor): Add argument with itself when it is a NaN. [_IEEE_FP_INEXACT] Remove. * sysdeps/alpha/fpu/s_floorf.c (__floorf): Likewise. (cherry picked from commit 65cc568cf57156e5230db9a061645e54ff028a41) (cherry picked from commit 1912cc082df4739c2388c375f8d486afdaa7d49b)
2016-12-08alpha: fix ceil on sNaN inputAurelien Jarno2-8/+6
The alpha version of ceil wrongly return sNaN for sNaN input. Fix that by checking for NaN and by returning the input value added with itself in that case. Finally remove the code to handle inexact exception, ceil should never generate such an exception. Changelog: * sysdeps/alpha/fpu/s_ceil.c (__ceil): Add argument with itself when it is a NaN. [_IEEE_FP_INEXACT] Remove. * sysdeps/alpha/fpu/s_ceilf.c (__ceilf): Likewise. (cherry picked from commit 062e53c195b4a87754632c7d51254867247698b4) (cherry picked from commit 3eff6f84311d2679a58a637e3be78b4ced275762)
2016-12-08X86-64: Add _dl_runtime_resolve_avx[512]_{opt|slow} [BZ #20508]H.J. Lu5-3/+165
There is transition penalty when SSE instructions are mixed with 256-bit AVX or 512-bit AVX512 load instructions. Since _dl_runtime_resolve_avx and _dl_runtime_profile_avx512 save/restore 256-bit YMM/512-bit ZMM registers, there is transition penalty when SSE instructions are used with lazy binding on AVX and AVX512 processors. To avoid SSE transition penalty, if only the lower 128 bits of the first 8 vector registers are non-zero, we can preserve %xmm0 - %xmm7 registers with the zero upper bits. For AVX and AVX512 processors which support XGETBV with ECX == 1, we can use XGETBV with ECX == 1 to check if the upper 128 bits of YMM registers or the upper 256 bits of ZMM registers are zero. We can restore only the non-zero portion of vector registers with AVX/AVX512 load instructions which will zero-extend upper bits of vector registers. This patch adds _dl_runtime_resolve_sse_vex which saves and restores XMM registers with 128-bit AVX store/load instructions. It is used to preserve YMM/ZMM registers when only the lower 128 bits are non-zero. _dl_runtime_resolve_avx_opt and _dl_runtime_resolve_avx512_opt are added and used on AVX/AVX512 processors supporting XGETBV with ECX == 1 so that we store and load only the non-zero portion of vector registers. This avoids SSE transition penalty caused by _dl_runtime_resolve_avx and _dl_runtime_profile_avx512 when only the lower 128 bits of vector registers are used. _dl_runtime_resolve_avx_slow is added and used for AVX processors which don't support XGETBV with ECX == 1. Since there is no SSE transition penalty on AVX512 processors which don't support XGETBV with ECX == 1, _dl_runtime_resolve_avx512_slow isn't provided. [BZ #20495] [BZ #20508] * sysdeps/x86/cpu-features.c (init_cpu_features): For Intel processors, set Use_dl_runtime_resolve_slow and set Use_dl_runtime_resolve_opt if XGETBV suports ECX == 1. * sysdeps/x86/cpu-features.h (bit_arch_Use_dl_runtime_resolve_opt): New. (bit_arch_Use_dl_runtime_resolve_slow): Likewise. (index_arch_Use_dl_runtime_resolve_opt): Likewise. (index_arch_Use_dl_runtime_resolve_slow): Likewise. * sysdeps/x86_64/dl-machine.h (elf_machine_runtime_setup): Use _dl_runtime_resolve_avx512_opt and _dl_runtime_resolve_avx_opt if Use_dl_runtime_resolve_opt is set. Use _dl_runtime_resolve_slow if Use_dl_runtime_resolve_slow is set. * sysdeps/x86_64/dl-trampoline.S: Include <cpu-features.h>. (_dl_runtime_resolve_opt): New. Defined for AVX and AVX512. (_dl_runtime_resolve): Add one for _dl_runtime_resolve_sse_vex. * sysdeps/x86_64/dl-trampoline.h (_dl_runtime_resolve_avx_slow): New. (_dl_runtime_resolve_opt): Likewise. (_dl_runtime_profile): Define only if _dl_runtime_profile is defined. (cherry picked from commit fb0f7a6755c1bfaec38f490fbfcaa39a66ee3604) (cherry picked from commit 4b8790c81c1a7b870a43810ec95e08a2e501123d)
2016-12-08x86_64: fix static build of __memcpy_chk for compilers defaulting to PIC/PIEAurelien Jarno1-1/+1
When glibc is compiled with gcc 6.2 that has been configured with to default to PIC/PIE, the static version of __memcpy_chk is not built, as the test is done on PIC instead of SHARED. Fix the test to check for SHARED, like it is done for similar functions like memmove_chk. Changelog: * sysdeps/x86_64/memcpy_chk.S (__memcpy_chk): Check for SHARED instead of PIC. (cherry picked from commit 380ec16d62f459d5a28cfc25b7b20990c45e1cc9) (cherry picked from commit 2d16e81babd1d7b66d10cec0bc6d6d86a7e0c95e)
2016-12-08MIPS: Add `.insn' to ensure a text label is defined as code not dataMaciej W. Rozycki3-0/+3
Avoid a build error with microMIPS compilation and recent versions of GAS which complain if a branch targets a label which is marked as data rather than microMIPS code: ../sysdeps/mips/mips32/crti.S: Assembler messages: ../sysdeps/mips/mips32/crti.S:72: Error: branch to a symbol in another ISA mode make[2]: *** [.../csu/crti.o] Error 1 as commit 9d862524f6ae ("MIPS: Verify the ISA mode and alignment of branch and jump targets") closed a hole in branch processing, making relocation calculation respect the ISA mode of the symbol referred. This allowed diagnosing the situation where an attempt is made to pass control from code assembled for one ISA mode to code assembled for a different ISA mode and either relaxing the branch to a cross-mode jump or if that is not possible, then reporting this as an error rather than letting such code build and then fail unpredictably at the run time. This however requires the correct annotation of branch targets as code, because the ISA mode is not relevant for data symbols and is therefore not recorded for them. The `.insn' pseudo-op is used for this purpose and has been supported by GAS since: Wed Feb 12 14:36:29 1997 Ian Lance Taylor <ian@cygnus.com> * config/tc-mips.c (mips_pseudo_table): Add "insn". (s_insn): New static function. * doc/c-mips.texi: Document .insn. so there has been no reason to avoid it where required. More recently this pseudo-op has been documented, by the microMIPS architecture specification[1][2], as required for the correct interpretation of any code label which is not followed by an actual instruction in an assembly source. Use it in our crti.S files then, to mark that the trailing label there with no instructions following is indeed not a code bug and the branch is legitimate. References: [1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS32 Instruction Set", MIPS Technologies, Inc., Document Number: MD00582, Revision 5.04, January 15, 2014, Section 7.1 "Assembly-Level Compatibility", p. 533 [2] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64 Instruction Set", MIPS Technologies, Inc., Document Number: MD00594, Revision 5.04, January 15, 2014, Section 8.1 "Assembly-Level Compatibility", p. 623 2016-11-23 Matthew Fortune <Matthew.Fortune@imgtec.com> Maciej W. Rozycki <macro@imgtec.com> * sysdeps/mips/mips32/crti.S (_init): Add `.insn' pseudo-op at `.Lno_weak_fn' label. * sysdeps/mips/mips64/n32/crti.S (_init): Likewise. * sysdeps/mips/mips64/n64/crti.S (_init): Likewise. (cherry picked from commit cfaf1949ff1f8336b54c43796d0e2531bc8a40a2) (cherry picked from commit 65a2b63756a4d622b938910d582d8b807c471c9a)
2016-11-06Fix cmpli usage in power6 memset.Joseph Myers2-2/+2
Building glibc for powerpc64 with recent (2.27.51.20161012) binutils, with multi-arch enabled, I get the error: ../sysdeps/powerpc/powerpc64/power6/memset.S: Assembler messages: ../sysdeps/powerpc/powerpc64/power6/memset.S:254: Error: operand out of range (5 is not between 0 and 1) ../sysdeps/powerpc/powerpc64/power6/memset.S:254: Error: operand out of range (128 is not between 0 and 31) ../sysdeps/powerpc/powerpc64/power6/memset.S:254: Error: missing operand Indeed, cmpli is documented as a four-operand instruction, and looking at nearby code it seems likely cmpldi was intended. This patch fixes this powerpc64 code accordingly, and makes a corresponding change to the powerpc32 code. Tested for powerpc, powerpc64 and powerpc64le by Tulio Magno Quites Machado Filho * sysdeps/powerpc/powerpc32/power6/memset.S (memset): Use cmplwi instead of cmpli. * sysdeps/powerpc/powerpc64/power6/memset.S (memset): Use cmpldi instead of cmpli. (cherry picked from commit 78b7adbaea643f2f213bb113e3ec933416a769a8)
2016-10-24Fix Linux sh4 pread/pwrite argument passingAdhemerval Zanella10-100/+19
Although conceptually correct for p{read,write}{64} offset argument passing, sh4 implementation does not generate the correct expected code. The __ALIGNMENT_ARG redefinition is incorrect for two reasons: 1. the kernel-features.h header is included multiple times (since it contains no guards) and 2. the value it redefines is also incorrect (should be '0, ' instead of empty definition). This patch fixes it by adding another macro, SYSCALL_LL_PRW{64}, meant to be used to pass the offset argument on p{read,write}64. It is basically the already define SYSCALL_LL{64} plus __ALIGNMENT_ARG unless __ASSUME_PRW_DUMMY_ARG is define. In this case an empty dummy argument is used regardless how __ALIGNMENT_ARG is defined (sh4 case). Checked on x86_64, i686, aarch64, armhf, and powerpc64le (basically a sanity check). Also, John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> and James Clarke <jrtc27@jrtc27.com> help me check on a debian sh4 bootstrap using 2.24 plus this patch to verify it also corrected fixed the regression issue. I also verified the generated object for a 2.24 build and master with this patch for sh4 and both look identical. * sysdeps/unix/sysv/linux/pread.c (__libc_pread): Use SYSCALL_LL_PRW. * sysdeps/unix/sysv/linux/pwrite.c (__libc_pwrite): Likewise. * sysdeps/unix/sysv/linux/pread64.c (__libc_pread64): Use SYSCALL_LL64_PRW. * sysdeps/unix/sysv/linux/pwrite64.c (__libc_pwrite64): Likewise. * sysdeps/unix/sysv/linux/sh/kernel-features.h: Define __ASSUME_PRW_DUMMY_ARG. * sysdeps/unix/sysv/linux/sh/pread.c: Remove file. * sysdeps/unix/sysv/linux/sh/pread64.c: Likewise. * sysdeps/unix/sysv/linux/sh/pwrite.c: Likewise. * sysdeps/unix/sysv/linux/sh/pwrite64.c: Likewise. * sysdeps/unix/sysv/linux/sysdep.h: Define SYSCALL_LL_PRW and SYSCALL_LL_PRW64 based on __ASSUME_PRW_DUMMY_ARG.
2016-10-05powerpc: Regenerate ULPsTulio Magno Quites Machado Filho1-53/+53
* sysdeps/powerpc/fpu/libm-test-ulps: Regenerated.
2016-09-28posix: Correctly block/unblock all signals on Linux posix_spawnAdhemerval Zanella1-6/+2
This patch correctly block and unblocks all signals when executing Linux posix_spawn by using the __libc_signal_{un}block_all functions instead of default sigprocmask. The latter might remove both SIGCANCEL and SIGSETXID from the blocked signal list. Checked on x86_64, i686, powerpc64le, and aarch64. * sysdeps/unix/sysv/linux/spawni.c (__spawnix): Correctly block and unblock all signals when executing the clone vfork child. (SIGALL_SET): Remove macro.
2016-09-28posix: Correctly enable/disable cancellation on Linux posix_spawnAdhemerval Zanella1-2/+4
This patch correctly enable and disable asynchronous cancellation on Linux posix_spawn. Current code invert the logic by enabling and disabling instead. It also adds a new test to check if posix_spawn is not a cancellation entrypoint. Checked on x86_64, i686, powerpc64le, and aarch64. * nptl/Makefile (tests): Add tst-exec5. * nptl/tst-exec5.c: New file. * sysdeps/unix/sysv/linux/spawni.c (__spawni): Correctly enable and disable asynchronous cancellation.
2016-09-19powerpc: Fix POWER9 impliesTulio Magno Quites Machado Filho2-2/+1
Fix multiarch build for POWER9 by correcting the order of the directories listed at sysnames configure variable. (cherry picked from commit 1850ce5a2ea3b908b26165e7e951cd4334129f07)
2016-09-02NaCl: Fix libc.abilist missing GLIBC_2.24 A.Roland McGrath1-0/+1
* sysdeps/arm/nacl/libc.abilist: Add GLIBC_2.24 A.
2016-09-02NaCl: Fix compile error for __dup after libc_hidden_proto addition.Roland McGrath1-0/+1
* sysdeps/nacl/dup.c: Add libc_hidden_def. (cherry picked from commit 6b75ba1388bff6a81bad410d7318d385a043b3cb)
2016-09-02Fix generic wait3 after union wait_status removal.Roland McGrath1-1/+1
* sysdeps/posix/wait3.c: Don't treat STAT_LOC as a union, since it's not any more. (cherry picked from commit 9a3d16ac152447567bfc822497c564a0630c79fe)
2016-09-02NaCl: Fix compile error in clock function.Roland McGrath1-1/+1
* sysdeps/nacl/clock.c (clock): nacl_abi_clock_t -> nacl_irt_clock_t (cherry picked from commit 307c2c2dfff76330a29a3ab69a0177b118142145)
2016-08-18arm: mark __startcontext as .cantunwind (bug 20435)Andreas Schwab1-0/+7
__startcontext marks the bottom of the call stack of the contexts created by makecontext. (cherry picked from commit 9e2ff6c9cc54c0b4402b8d49e4abe7000fde7617) Also includes the NEWS update, cherry-picked from commits 056dd72af83f5459ce6d545a49dea6dba7d635dc and 4d047efdbc55b0d68947cde682e5363d16a66294.
2016-08-18Do not override objects in libc.a in other static libraries [BZ #20452]Florian Weimer13-1/+16
With this change, we no longer add sysdep.o and similar objects which are present in libc.a to other static libraries. (cherry picked from commit d9067fca40b8aac156d73cfa44d6875813555a6c)
2016-08-15sparc: remove fdim sparc specific implementationsAurelien Jarno11-314/+2
The fdim and fdimf functions on sparc do not fully follow the standard and do not set errno to ERANGE when the result overflows. Since glibc 2.24 this causes the two following tests to fail: Failure: fdim (max_value, -max_value): errno set to 0, expected 34 (ERANGE) Failure: fdim_upward (max_value, -max_value): errno set to 0, expected 34 (ERANGE) It happens that using GCC with the generic C code generates very similar code to the sparc specific implementations. Therefore this patches remove them. Note it might still worth adding a vis3 specific version of fdim on sparc32/sparcv9, this is done in a following patch to ease backporting. Changelog: * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile [$(subdir) = math && $(have-as-vis3) = yes] (libm-sysdep_routines): Remove s_fdimf-vis3, s_fdim-vis3. * sysdeps/sparc/sparc32/fpu/s_fdim.S: Delete file. * sysdeps/sparc/sparc32/fpu/s_fdimf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdim.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fdimf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_fdim.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_fdimf.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_fdim.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_fdimf.S: Likewise. (cherry picked from commit 8a9f4eb95894eae7e725e79721ba26fbc5b4ed06)
2016-08-15Fix sNaN handling in nearbyint on 32-bit sparc.David S. Miller4-10/+10
* sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyint-vis3.S (__nearbyint_vis3): Don't check for sNaN before float register is loaded with the incoming argument. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_nearbyintf-vis3.S (__nearbyintf_vis3): Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyint.S (__nearbyint): Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_nearbyintf.S (__nearbyintf): Likewise. (cherry picked from commit 3ef3f1b93fdf20143865cc16dd75f39a7f0fac2f)
2016-08-14powerpc: fix ifunc-sel.h fix asm constraints and clobber listAurelien Jarno1-2/+4
As pointer out on the mailing list, the inline assembly code in sysdeps/powerpc/ifunc-sel.h doesn't have a list of clobbered registers and used wrong constraints. This patch fixes that. I verified it doesn't introduce any change in the generated code. Changelog: * sysdeps/powerpc/ifunc-sel.h (ifunc_sel): Add "11", "12", "cr0" to the clobber list. Use "i" constraint instead of "X". (ifunc_one): Add "12" to the clobber list. Use "i" constraint instead of "X". (cherry picked from commit 30f926d3b3dcb74c038155715ed341d5c4b334eb)
2016-08-14powerpc: fix ifunc-sel.h with GCC 6Aurelien Jarno1-3/+4
On 32-bit PowerPC GCC 6 always saves the PIC register on the stack in the prologue and adjust the stack in the epilogue. It is therefore not possible anymore to just exit the function in the inline asm code, otherwise it corrupts the stack pointer. This causes the following tests to fail when using GCC 6: FAIL: elf/ifuncmain1 FAIL: elf/ifuncmain1pic FAIL: elf/ifuncmain1picstatic FAIL: elf/ifuncmain1pie FAIL: elf/ifuncmain1staticpic FAIL: elf/ifuncmain1staticpie FAIL: elf/ifuncmain1vis FAIL: elf/ifuncmain1vispic FAIL: elf/ifuncmain1vispie FAIL: elf/ifuncmain2pic FAIL: elf/ifuncmain2picstatic FAIL: elf/ifuncmain3 FAIL: elf/ifuncmain4picstatic FAIL: elf/ifuncmain5 FAIL: elf/ifuncmain5picstatic FAIL: elf/ifuncmain5staticpic The solution is to replace the beqlr instructions by a beq to the end of the inline asm code. This fixes all the above failures. ChangeLog: * sysdeps/powerpc/ifunc-sel.h (ifunc_sel): Replace beqlr instructions by beq instructions jumping to the end of the function. (cherry picked from commit ee71e5b6dd6a21e981ad0fa74359e066f5a8b359)
2016-08-04x86: Use sysdep.o from libc.a in static librariesFlorian Weimer1-0/+2
Static libraries can use the sysdep.o copy in libc.a without a performance penalty. This results in a visible difference if libpthread.a is relinked into a single object file (which is needed to support libraries which check for the presence of certain symbols to enable threading support, which generally fails with static linking unless libpthread.a is relinked). (cherry picked from commit e67330ab57bfd0f964539576ae7dcc658c456724)
2016-08-02sparc: remove ceil, floor, trunc sparc specific implementationsAurelien Jarno46-2245/+10
The ceil, floor and trunc functions on sparc do not fully follow the standard and trigger an inexact exception when presented a value which is not an integer. Since glibc 2.24 this causes a few tests to fail, for instance: testing double (without inline functions) Failure: ceil (lit_pi): Exception "Inexact" set Failure: ceil (-lit_pi): Exception "Inexact" set Failure: ceil (min_subnorm_value): Exception "Inexact" set Failure: ceil (min_value): Exception "Inexact" set Failure: ceil (0.1): Exception "Inexact" set Failure: ceil (0.25): Exception "Inexact" set Failure: ceil (0.625): Exception "Inexact" set Failure: ceil (-min_subnorm_value): Exception "Inexact" set Failure: ceil (-min_value): Exception "Inexact" set Failure: ceil (-0.1): Exception "Inexact" set Failure: ceil (-0.25): Exception "Inexact" set Failure: ceil (-0.625): Exception "Inexact" set I tried to fix that by using the same strategy than used on other architectures, that is by saving the FSR register at the beginning and restoring it at the end of the function. When doing so I noticed a comment that this operation might be very costly, so I decided to do some benchmarks. The benchmarks below represent the time required to run each of the function 60 millions of times with different input value. I have done that in the basic V9 code, the VIS2 code, and using the default C implementation of the libc, for both sparc32 and sparc64, on a Niagara T1 based machine and an UltraSparc IIIi. Given I don't have access to a more recent machine), I haven't been able to test the VIS3 version. Also it should be noted that it doesn't make sense to do this benchmark for V8 or earlier as in that case we use the default C implementation. The results are available in the table below, the "+ fix" version correspond to the one saving and restoring the FSR. Niagara T1 / sparc32 -------------------- ceilf ceil floorf floor truncf trunc V9 19.10 22.48 19.10 22.48 16.59 19.27 V9 + fix 19.77 23.34 19.77 23.33 17.27 20.12 VIS2 16.87 19.62 16.87 19.62 VIS2 + fix 17.55 20.47 17.55 20.47 C impl 11.39 13.80 11.40 13.80 10.88 10.84 Niagara T1 / sparc64 -------------------- ceilf ceil floorf floor truncf trunc V9 18.14 22.23 18.14 22.23 15.64 19.02 V9 + fix 18.82 23.08 18.82 23.08 16.32 19.87 VIS2 15.92 19.37 15.92 19.37 VIS2 + fix 16.59 20.22 16.59 20.22 C impl 11.39 13.60 11.39 15.36 10.88 12.65 UltraSparc IIIi / sparc32 ------------------------- ceilf ceil floorf floor truncf trunc V9 4.81 7.09 6.61 11.64 4.91 7.05 V9 + fix 7.20 10.42 7.14 10.54 6.76 9.47 VIS2 4.81 7.03 4.76 7.13 VIS2 + fix 6.76 9.51 6.71 9.63 C impl 3.88 8.62 3.90 9.45 3.57 6.62 UltraSparc IIIi / sparc64 ------------------------- ceilf ceil floorf floor truncf trunc V9 3.48 4.39 3.48 4.41 3.01 3.85 V9 + fix 4.76 5.90 4.76 5.90 4.86 6.26 VIS2 2.95 3.61 2.95 3.61 VIS2 + fix 4.24 5.37 4.30 7.97 C impl 3.63 4.89 3.62 6.38 3.33 4.03 The first thing that should be noted is that the C implementation is always faster on the Niagara T1 based machine. On the UltraSparc IIIi the float version on sparc32 is also faster. Coming back about the fix saving and restoring the FSR, it appears it has a big impact as expected. In that case the C implementation is always faster than the fixed implementations. This patch therefore removes the sparc specific implementations in favor of the generic ones. Changelog: * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile [$(subdir) = math] (libm-sysdep_routines): Remove. [$(subdir) = math && $(have-as-vis3) = yes] (libm-sysdep_routines): Remove s_ceilf-vis3, s_ceil-vis3, s_floorf-vis3, s_floor-vis3, s_truncf-vis3, s_trunc-vis3. * sysdeps/sparc/sparc64/fpu/multiarch/Makefile: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis2.S: Delete file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis2.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis2.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis2.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_trunc.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf-vis3.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_truncf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_ceil.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_ceilf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_floor.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_floorf.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_trunc.S: Likewise. * sysdeps/sparc/sparc32/sparcv9/fpu/s_truncf.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis2.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis2.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis2.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis2.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_trunc-vis3.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_trunc.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_truncf-vis3.S: Likewise. * sysdeps/sparc/sparc64/fpu/multiarch/s_truncf.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_ceil.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_ceilf.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_floor.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_floorf.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_trunc.S: Likewise. * sysdeps/sparc/sparc64/fpu/s_truncf.S: Likewise.
2016-07-27Don't compile do_test with -mavx/-mavx/-mavx512H.J. Lu11-78/+141
Don't compile do_test with -mavx, -mavx nor -mavx512 since they won't run on non-AVX machines. [BZ #20384] * sysdeps/x86_64/fpu/Makefile (extra-test-objs): Add test-double-libmvec-sincos-avx-main.o, test-double-libmvec-sincos-avx2-main.o, test-double-libmvec-sincos-main.o, test-float-libmvec-sincosf-avx-main.o, test-float-libmvec-sincosf-avx2-main.o and test-float-libmvec-sincosf-main.o. test-float-libmvec-sincosf-avx512-main.o. ($(objpfx)test-double-libmvec-sincos): Also link with $(objpfx)test-double-libmvec-sincos-main.o. ($(objpfx)test-double-libmvec-sincos-avx): Also link with $(objpfx)test-double-libmvec-sincos-avx-main.o. ($(objpfx)test-double-libmvec-sincos-avx2): Also link with $(objpfx)test-double-libmvec-sincos-avx2-main.o. ($(objpfx)test-float-libmvec-sincosf): Also link with $(objpfx)test-float-libmvec-sincosf-main.o. ($(objpfx)test-float-libmvec-sincosf-avx): Also link with $(objpfx)test-float-libmvec-sincosf-avx2-main.o. [$(config-cflags-avx512) == yes] (extra-test-objs): Add test-double-libmvec-sincos-avx512-main.o and ($(objpfx)test-double-libmvec-sincos-avx512): Also link with $(objpfx)test-double-libmvec-sincos-avx512-main.o. ($(objpfx)test-float-libmvec-sincosf-avx512): Also link with $(objpfx)test-float-libmvec-sincosf-avx512-main.o. (CFLAGS-test-double-libmvec-sincos.c): Removed. (CFLAGS-test-float-libmvec-sincosf.c): Likewise. (CFLAGS-test-double-libmvec-sincos-main.c): New. (CFLAGS-test-double-libmvec-sincos-avx-main.c): Likewise. (CFLAGS-test-double-libmvec-sincos-avx2-main.c): Likewise. (CFLAGS-test-float-libmvec-sincosf-main.c): Likewise. (CFLAGS-test-float-libmvec-sincosf-avx-main.c): Likewise. (CFLAGS-test-float-libmvec-sincosf-avx2-main.c): Likewise. (CFLAGS-test-float-libmvec-sincosf-avx512-main.c): Likewise. (CFLAGS-test-double-libmvec-sincos-avx.c): Set to -DREQUIRE_AVX. (CFLAGS-test-float-libmvec-sincosf-avx.c ): Likewise. (CFLAGS-test-double-libmvec-sincos-avx2.c): Set to -DREQUIRE_AVX2. (CFLAGS-test-float-libmvec-sincosf-avx2.c ): Likewise. (CFLAGS-test-double-libmvec-sincos-avx512.c): Set to -DREQUIRE_AVX512F. (CFLAGS-test-float-libmvec-sincosf-avx512.c): Likewise. * sysdeps/x86_64/fpu/test-double-libmvec-sincos.c: Rewritten. * sysdeps/x86_64/fpu/test-float-libmvec-sincosf.c: Likewise. * sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx-main.c: New file. * sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx2-main.c: Likewise. * sysdeps/x86_64/fpu/test-double-libmvec-sincos-avx512-main.c: Likewise. * sysdeps/x86_64/fpu/test-double-libmvec-sincos-main.c: Likewise. * sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx-main.c: Likewise. * sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx2-main.c: Likewise. * sysdeps/x86_64/fpu/test-float-libmvec-sincosf-avx512-main.c: Likewise. * sysdeps/x86_64/fpu/test-float-libmvec-sincosf-main.c: Likewise.
2016-07-27Nios II localplt.data update: remove __eqsf2Chung-Lin Tang1-1/+0
2016-07-21powerpc: Fix missing verb and typo in comment about AT_HWCAP entryGustavo Romero1-2/+2
Fix missing verb and typo in comment about AT_HWCAP entry, in the context of mcontext_t struct definition for PPC64 Linux kernels.
2016-07-21[AArch64] Update libm-test-ulpsSzabolcs Nagy1-4/+4
This partly reverts commit f8238ae3c7701dbd9c04028861916de64e578114 that regenerated the ulps, to make the max ulps good for gcc-5, gcc-6 and gcc-trunk as well. * sysdeps/aarch64/libm-test-ulps: Updated.
2016-07-20S390: Do not clobber r13 with memcpy on 31bit with copies >1MB.Stefan Liebler1-8/+5
If the default memcpy variant is called with a length of >1MB on 31bit, r13 is clobbered as the algorithm is switching to mvcle. The mvcle code returns without restoring r13. All other cases are restoring r13. If memcpy is called from outside libc the ifunc resolver will only select this variant if running on machines older than z10. Otherwise or if memcpy is called from inside libc, this default memcpy variant is called. The testcase timezone/tst-tzset is triggering this issue in some combinations of gcc versions and optimization levels. This bug was introduced in commit 04bb21ac93e90d7696bcaf8febe2b2dd2d83585a and thus is a regression compared to former glibc 2.23 release. This patch removes the usage of r13 at all. Thus it is not saved and restored. The base address for execute-instruction is now stored in r5 which is obtained after r5 is not needed anymore as 256byte block counter. ChangeLog: * sysdeps/s390/s390-32/memcpy.S (memcpy): Eliminate the usage of r13 as it is not restored in mvcle case.
2016-07-19microblaze: fix variable name collision with syscall macrosMike Frysinger1-21/+21
If a function passes in a variable named "ret", the code will miscompile when it declares a local ret variable. In some cases, it's even a build failure like so: ../sysdeps/unix/sysv/linux/spawni.c: In function '__spawni_child': ../sysdeps/unix/sysv/linux/spawni.c:289:5: error: address of register variable 'ret' requested while (write_not_cancel (p, &ret, sizeof ret) < 0)
2016-07-18i386: Compile rtld-*.os with -mno-sse -mno-mmx -mfpmath=387H.J. Lu1-2/+5
Compile i386 rtld-*.os with -mno-sse -mno-mmx -mfpmath=387 so that no code in ld.so uses mm/xmm/ymm/zmm registers on i386 since the first 3 mm/xmm/ymm/zmm registers are used to pass vector parameters which must be preserved. * sysdeps/i386/Makefile (rtld-CFLAGS): New. [subdir == elf] (CFLAGS-.os): Replace -mno-sse -mno-mmx -mfpmath=387 with $(rtld-CFLAGS). [subdir != elf] (CFLAGS-.os): Compile rtld-*.os with $(rtld-CFLAGS).
2016-07-18Fix cos computation for multiple precision fallback (bz #20357)Siddhesh Poyarekar1-2/+2
During the sincos consolidation I made two mistakes, one was a logical error due to which cos(0x1.8475e5afd4481p+0) returned sin(0x1.8475e5afd4481p+0) instead. The second issue was an error in negating inputs for the correct quadrants for sine. I could not find a suitable test case for this despite running a program to search for such an input for a couple of hours. Following patch fixes both issues. Tested on x86_64. Thanks to Matt Clay for identifying the issue. [BZ #20357] * sysdeps/ieee754/dbl-64/s_sin.c (sloww): Fix up condition to call __mpsin/__mpcos and to negate values. * math/auto-libm-test-in: Add test. * math/auto-libm-test-out: Regenerate.
2016-07-18[AArch64] Regenerate libm-test-ulpsSzabolcs Nagy1-10/+10
* sysdeps/aarch64/libm-test-ulps: Regenerated.
2016-07-13Refactor Linux raise implementation (BZ#15368)Adhemerval Zanella3-50/+77
This patch changes both the nptl and libc Linux raise implementation to avoid the issues described in BZ#15368. The strategy used is summarized in bug report first comment: 1. Block all signals (including internal NPTL ones); 2. Get pid and tid directly from syscall (not relying on cached values); 3. Call tgkill; 4. Restore old signal mask. Tested on x86_64 and i686. [BZ #15368] * sysdeps/unix/sysv/linux/nptl-signals.h (__nptl_clear_internal_signals): New function. (__libc_signal_block_all): Likewise. (__libc_signal_block_app): Likewise. (__libc_signal_restore_set): Likewise. * sysdeps/unix/sysv/linux/pt-raise.c (raise): Use Linux raise.c implementation. * sysdeps/unix/sysv/linux/raise.c (raise): Reimplement to not use the cached pid/tid value in pthread structure.
2016-07-13Regenerate i686 libm-test-ulps with GCC 6.1 at -O3 [BZ #20347]H.J. Lu1-2/+2
This fixes with GCC 6.1 and -O3 on i686: Failure: Test: j0_downward (0xap+0) Result: is: -2.45935813e-01 -0x1.f7ad32p-3 should be: -2.45935768e-01 -0x1.f7ad2cp-3 difference: 4.47034835e-08 0x1.800000p-25 ulp : 3.0000 max.ulp : 2.0000 Maximal error of `j0_downward' is : 3 ulp accepted: 2 ulp [BZ #20347] * sysdeps/i386/i686/fpu/multiarch/libm-test-ulps: Regenerated.
2016-07-12x86-64: Add p{read,write}[v]64 to syscalls.list [BZ #20348]H.J. Lu1-0/+4
64-bit off_t in pread64, preadv, pwrite64 and pwritev syscalls is passed in one 64-bit register for both x32 and x86-64. Since the inline asm statement only passes long, which is 32-bit for x32, in registers, 64-bit off_t is truncated to 32-bit on x32. Since __ASSUME_PREADV and __ASSUME_PWRITEV are defined unconditionally, these syscalls can be implemented in syscalls.list to pass 64-bit off_t in one 64-bit register. Tested on x86-64 and x32 with off_t > 4GB on pread64/pwrite64 and preadv64/pwritev64. [BZ #20348] * sysdeps/unix/sysv/linux/x86_64/syscalls.list: Add pread64, preadv64, pwrite64 and pwritev64.
2016-07-12x86-64: Properly align stack in _dl_tlsdesc_dynamic [BZ #20309]H.J. Lu1-6/+7
Since _dl_tlsdesc_dynamic is called via PLT, we need to add 8 bytes for push in the PLT entry to align the stack. [BZ #20309] * configure.ac (have-mtls-dialect-gnu2): Set to yes if -mtls-dialect=gnu2 works. * configure: Regenerated. * elf/Makefile [have-mtls-dialect-gnu2 = yes] (tests): Add tst-gnu2-tls1. (modules-names): Add tst-gnu2-tls1mod. ($(objpfx)tst-gnu2-tls1): New. (tst-gnu2-tls1mod.so-no-z-defs): Likewise. (CFLAGS-tst-gnu2-tls1mod.c): Likewise. * elf/tst-gnu2-tls1.c: New file. * elf/tst-gnu2-tls1mod.c: Likewise. * sysdeps/x86_64/dl-tlsdesc.S (_dl_tlsdesc_dynamic): Add 8 bytes for push in the PLT entry to align the stack.
2016-07-11X86-64: Define LO_HI_LONG to skip pos_h [BZ #20349]H.J. Lu1-0/+4
Define LO_HI_LONG to skip pos_h since it is ignored by kernel: static inline loff_t pos_from_hilo(unsigned long high, unsigned long low) { #define HALF_LONG_BITS (BITS_PER_LONG / 2) return (((loff_t)high << HALF_LONG_BITS) << HALF_LONG_BITS) | low; } where size of loff_t == size of long. [BZ #20349] * sysdeps/unix/sysv/linux/x86_64/sysdep.h (LO_HI_LONG): New.
2016-07-11[AArch64] Add bits/hwcap.h for aarch64 linuxSzabolcs Nagy1-0/+34
AArch64 uses HWCAP bits but they are not defined in sys/auxv.h. This patch adds a copy of the linux v4.6 arm64 uapi asm/hwcap.h definitions. * sysdeps/unix/sysv/linux/aarch64/bits/hwcap.h: New.
2016-07-11[AArch64] Fix libc internal asm profiling codeSzabolcs Nagy2-2/+35
When glibc is built with --enable-profile, the ENTRY of asm functions includes CALL_MCOUNT for profiling. (matters for binaries static linked against libc_p.a.) CALL_MCOUNT did not save/restore argument registers around the _mcount call so it clobbered them. (it is enough to only save/restore the arguments passed to a given asm function, but that would be too many asm changes so it is simpler to always save all argument registers in this macro.) float args are not saved: mcount does not clobber the float regs and currently no asm function takes float arguments anyway. [BZ #18707] * sysdeps/aarch64/Makefile (CFLAGS-mcount.c): Add -mgeneral-regs-only. * sysdeps/aarch64/sysdep.h (CALL_MCOUNT): Save argument registers.
2016-07-08Fix LO_HI_LONG definitionAdhemerval Zanella1-7/+3
The p{read,write}v{64} consolidation patch [1] added a wrong guard for LO_HI_LONG definition. It currently uses both '__WORDSIZE == 64' and 'defined __ASSUME_WORDSIZE64_ILP32' to set the value to be passed in one argument, otherwise it will be split in two. However it fails on MIPS64n32 where syscalls n32 uses the compat implementation in the kernel meaning the off_t arguments are passed in two separate registers. GLIBC already defines a macro for such cases (__OFF_T_MATCHES_OFF64_T), so this patch uses it instead. Checked on x86_64, i686, x32, aarch64, armhf, and s390. * sysdeps/unix/sysv/linux/sysdep.h [__WORDSIZE == 64 || __ASSUME_WORDSIZE64_ILP32] (LO_HI_LONG): Remove guards. * misc/tst-preadvwritev-common.c: New file. * misc/tst-preadvwritev.c: Use tst-preadvwritev-common.c. * misc/tst-preadvwritev64.c: Use tst-preadwritev-common.c and add a check for files larger than 2GB. [1] 4751bbe2ad4d1bfa05774e29376d553ecfe563b0
2016-07-08Remove __ASSUME_OFF_DIFF_OFF64 definitionAdhemerval Zanella9-9/+8
This patch removes the __ASSUME_OFF_DIFF_OFF64 define introduced in p{read,write} consolidation patch. This define was added based on the idea 32 bits ports would continue to follow previous off{64}_t definition where off_t size differs from off64_t one. However, with recent AArch64/ILP32 patch submission and also with discussion for RISCV kernel interface, 32 bits ports now may aim to use off_t and off64_t with the same size as 64 bits. So current assumption for both p{read,write} and p{read,write}v are not compatible with new type definition. This patch now makes the syscall wrappers to only depend on __OFF_T_MATCHES_OFF64_T to define the default and 64-suffix variant, as follow: <function>.c #ifndef __OFF_T_MATCHES_OFF64_T /* build <function> */ #endif and <function>64.c /* build <function>64 */ #ifdef __OFF_T_MATCHES_OFF64_T weak_alias (fallocate64, fallocate) #endif Tested on x86_64, i686, x32, and armhf. * sysdeps/unix/sysv/linux/mips/kernel-features.h (__ASSUME_OFF_DIFF_OFF64): Remove define. * sysdeps/unix/sysv/linux/pread.c [__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pread): Replace by __OFF_T_MATCHES_OFF64_T. * sysdeps/unix/sysv/linux/pread64.c [__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pread64): Likewise. * sysdeps/unix/sysv/linux/preadv.c [__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (preadv): Likewise. * sysdeps/unix/sysv/linux/preadv64.c [__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (preadv64): Likewise. * sysdeps/unix/sysv/linux/pwrite.c [__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pwrite): Likewise. * sysdeps/unix/sysv/linux/pwrite64.c [__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pwrite64): Likewise. * sysdeps/unix/sysv/linux/pwritev.c [__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pwritev): Likewise. * sysdeps/unix/sysv/linux/pwritev64.c [__WORDSIZE != 64 || __ASSUME_OFF_DIFF_OFF64] (pwritev64): Likewise.
2016-07-08tile: only define __ASSUME_ALIGNED_REGISTER_PAIRS for 32-bitChris Metcalf1-1/+3
The previous uses of this symbol were all in wordsize-32 code. In commit eeddfa91cbb1 ("Consolidate off_t/off64_t syscall argument passing") it was expanded to be used in pread/pwrite. Accordingly, we only define it in 32-bit compilation modes now. Both tilepro and tilegx32 follow this convention for the kernel ABI. tilegx64 follows it for passing 128-bit values, but there are no such ABIs in the kernel.
2016-07-08ppc: Fix modf (sNaN) for pre-POWER5+ CPU (bug 20240).Aurelien Jarno2-0/+10
Commit a6a4395d fixed modf implementation by compiling s_modf.c and s_modff.c with -fsignaling-nans. However these files are also included from the pre-POWER5+ implementation, and thus these files should also be compiled with -fsignaling-nans. Changelog: [BZ #20240] * sysdeps/powerpc/powerpc32/power4/fpu/multiarch/Makefile (CFLAGS-s_modf-ppc32.c): New variable. (CFLAGS-s_modff-ppc32.c): Likewise. * sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile (CFLAGS-s_modf-ppc64.c): Likewise. (CFLAGS-s_modff-ppc64.c): Likewise.
2016-07-06S390: Use DT_JUMPREL in prelink undo code.Stefan Liebler3-10/+6
On s390, the current prelink undo code in elf_machine_lazy_rel() has the requirement, that the plt stubs use the first got slots after the 3 reserved ones. In case of undoing prelink, the plt got slots are reset to the correct addresses whithin the corresponding plt-stub. Therefore the address is calculated by the address of the first plt-stub-address which was written by prelink (see l->l_mach.plt) to got[1] and index of current relocation multiplied with 32 (=size of one plt slot). The index was calculated with &current-got-slot - &got[3]. This patch removes the requirement, that the plt-got-slots are starting at got[3]. The index is now calculated with &current-reloc - &reloc[0]. The first struct Elf64_Rela is stored at DT_JMPREL. This patch is needed to prepare for partial relro support. Ulrich Weigand suggested this approach to use DT_JMPREL - Thanks. ChangeLog: * sysdeps/s390/linkmap.h (struct link_map_machine): Remove member gotplt and add member jmprel. * sysdeps/s390/s390-32/dl-machine.h (elf_machine_runtime_setup): Setup member jmprel with DT_JMPREL instead of gotplt with &got[3]. (elf_machine_lazy_rel): Calculate address with reloc and jmprel. * sysdeps/s390/s390-64/dl-machine.h: Likewise.
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