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2017-10-22x86-64: Use fxsave/xsave/xsavec in _dl_runtime_resolve [BZ #21265]H.J. Lu3-22/+85
2017-08-06x86-64: Use _dl_runtime_resolve_opt only with AVX512F [BZ #21871]H.J. Lu1-2/+5
2017-04-28x86: Use AVX2 memcpy/memset on Skylake server [BZ #21396]H.J. Lu2-1/+8
2017-04-28x86: Set Prefer_No_VZEROUPPER if AVX512ER is availableH.J. Lu2-2/+21
2016-11-30X86-64: Add _dl_runtime_resolve_avx[512]_{opt|slow} [BZ #20508]H.J. Lu2-0/+20
2016-07-01Fixed wrong vector sincos/sincosf ABI to have it compatible withAndrew Senkevich1-0/+98
2016-06-30Check Prefer_ERMS in memmove/memcpy/mempcpy/memsetH.J. Lu1-0/+3
2016-06-29Avoid array-bounds warning for strncat on i586 (bug 20260)Andreas Schwab1-2/+1
2016-06-07Check FMA after COMMON_CPUID_INDEX_80000001H.J. Lu1-4/+9
2016-05-27Count number of logical processors sharing L2 cacheH.J. Lu1-34/+116
2016-05-20Remove special L2 cache case for Knights LandingH.J. Lu1-2/+0
2016-05-19Correct Intel processor level type mask from CPUIDH.J. Lu1-1/+1
2016-05-19Check the HTT bit before counting logical threadsH.J. Lu2-76/+85
2016-05-13Support non-inclusive caches on Intel processorsH.J. Lu1-1/+11
2016-05-11Remove x86 ifunc-defines.sym and rtld-global-offsets.symH.J. Lu4-10/+18
2016-05-08Move sysdeps/x86_64/cacheinfo.c to sysdeps/x86H.J. Lu1-0/+673
2016-04-15Detect Intel Goldmont and Airmont processorsH.J. Lu1-0/+8
2016-04-01Remove Fast_Copy_Backward from Intel Core processorsH.J. Lu1-5/+1
2016-03-28Initial Enhanced REP MOVSB/STOSB (ERMS) supportH.J. Lu1-0/+4
2016-03-28[x86] Add a feature bit: Fast_Unaligned_CopyH.J. Lu2-1/+16
2016-03-22Set index_arch_AVX_Fast_Unaligned_Load only for Intel processorsH.J. Lu2-74/+88
2016-03-10Add _arch_/_cpu_ to index_*/bit_* in x86 cpu-features.hH.J. Lu2-147/+155
2016-03-08Define _HAVE_STRING_ARCH_mempcpy to 1 for x86H.J. Lu1-0/+3
2016-02-18Add _STRING_INLINE_unaligned and string_private.hH.J. Lu2-2/+22
2016-01-14Set index_Fast_Unaligned_Load for Excavator family CPUsAmit Pawar1-0/+8
2016-01-04Update copyright dates with scripts/update-copyrights.Joseph Myers28-28/+28
2015-12-19Added memset optimized with AVX512 for KNL hardware.Andrew Senkevich2-0/+6
2015-12-15Add Prefer_MAP_32BIT_EXEC to map executable pages with MAP_32BIThjl/32bit/masterH.J. Lu1-0/+3
2015-12-15Enable Silvermont optimizations for Knights LandingH.J. Lu1-0/+3
2015-12-07Utilize x86_64 vector math functions w/o -fopenmp.Andrew Senkevich1-0/+6
2015-11-30Update family and model detection for AMD CPUsH.J. Lu1-12/+15
2015-11-27Better workaround for aliases of *_finite symbols in vector math library.Andrew Senkevich1-29/+0
2015-11-14Run tst-prelink test for GLOB_DAT relocH.J. Lu3-46/+0
2015-11-10Add a test for prelink outputH.J. Lu3-0/+46
2015-10-28Handle more state in i386/x86_64 fesetenv (bug 16068).Joseph Myers3-1/+347
2015-10-28Fix i386/x86_64 fesetenv SSE exception clearing (bug 19181).Joseph Myers2-1/+47
2015-09-25Fix pow missing underflows (bug 18825).Joseph Myers1-0/+1
2015-09-04Rename bits/linkmap.h to linkmap.h (bug 14912).Joseph Myers1-0/+0
2015-08-27Detect and select i586/i686 implementation at run-timefedora/masterH.J. Lu3-3/+38
2015-08-26Don't disable SSE in x86-64 ld.soH.J. Lu2-114/+0
2015-08-20Move x86_64 init-arch.h to sysdeps/x86/init-arch.hH.J. Lu1-0/+22
2015-08-20nptl: Document crash due to incorrect use of locksFlorian Weimer1-1/+3
2015-08-19Also check __i586__/__i686__ for HAS_I586/HAS_I686H.J. Lu1-8/+9
2015-08-18Define HAS_CPUID/HAS_I586/HAS_I686 from -march=H.J. Lu2-2/+29
2015-08-13Check if cpuid is available in init_cpu_featuresH.J. Lu1-0/+12
2015-08-13Add _dl_x86_cpu_features to rtld_globalH.J. Lu10-0/+572
2015-07-09Preserve bound registers for pointer pass/returnIgor Zamyatin1-0/+2
2015-07-07Do not create invalid pointers in C code of string functions.Torvald Riegel1-7/+11
2015-06-18Vector sincosf for x86_64 and tests.Andrew Senkevich1-0/+2
2015-06-18Vector sincos for x86_64 and tests.Andrew Senkevich1-0/+2
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