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AgeCommit message (Expand)AuthorFilesLines
2021-03-30Move __isnanf128 to libc.soSiddhesh Poyarekar1-0/+1
2021-03-29x86: Add string/memory function tests in RTM regionH.J. Lu12-0/+618
2021-03-29x86: Set Prefer_No_VZEROUPPER and add Prefer_AVX2_STRCMPH.J. Lu3-2/+21
2021-03-29x86: Properly disable XSAVE related features [BZ #27605]H.J. Lu2-0/+56
2021-03-24elf: Fix not compiling ifunc tests that need gcc ifunc supportSamuel Thibault1-0/+2
2021-03-15Build get-cpuid-feature-leaf.c without stack-protector [BZ #27555]Siddhesh Poyarekar2-0/+4
2021-03-15x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444]H.J. Lu7-0/+79
2021-03-06x86: Set minimum x86-64 level marker [BZ #27318]H.J. Lu3-11/+58
2021-03-02x86: Add CPU-specific diagnostics to ld.so --list-diagnosticsFlorian Weimer2-0/+120
2021-03-02x86: Automate generation of PREFERRED_FEATURE_INDEX_1 bitfieldFlorian Weimer2-34/+51
2021-02-22x86: Use x86/nptl/pthreaddef.hH.J. Lu1-0/+49
2021-02-22x86: Remove unused variables for raw cache sizes from cacheinfo.hFlorian Weimer1-12/+0
2021-02-22<bits/platform/x86.h>: Correct x86_cpu_TBMH.J. Lu1-1/+1
2021-02-12x86: Remove the extra space between "# endif"H.J. Lu1-1/+1
2021-02-10x86: Use SIZE_MAX instead of (long int)-1 for tunable range valueSiddhesh Poyarekar1-5/+5
2021-02-10tunables: Simplify TUNABLE_SET interfaceSiddhesh Poyarekar1-9/+6
2021-02-07x86: Add PTWRITE feature detection [BZ #27346]H.J. Lu9-5/+44
2021-02-02x86: Adding an upper bound for Enhanced REP MOVSB.Sajan Karumanchi3-1/+20
2021-02-01sysconf: Add _SC_MINSIGSTKSZ/_SC_SIGSTKSZ [BZ #20305]H.J. Lu2-0/+30
2021-01-29x86: Properly set usable CET feature bits [BZ #26625]H.J. Lu10-13/+120
2021-01-25Fix misplaced constAndreas Schwab2-2/+2
2021-01-22x86: Properly match CPU features in /proc/cpuinfo [BZ #27222]H.J. Lu1-13/+30
2021-01-21x86: Check ifunc resolver with CPU_FEATURE_USABLE [BZ #27072]H.J. Lu6-0/+184
2021-01-21Use hidden visibility for early static PIE codeSzabolcs Nagy1-0/+5
2021-01-21<sys/platform/x86.h>: Remove the C preprocessor magicH.J. Lu12-832/+1153
2021-01-14x86: Move x86 processor cache info to cpu_featuresH.J. Lu5-412/+551
2021-01-14Fix x86 build with --enable-tunable=noAdhemerval Zanella1-0/+1
2021-01-13ldconfig/x86: Store ISA level in cache and aux cacheH.J. Lu1-0/+31
2021-01-13x86: Set header.feature_1 in TCB for always-on CET [BZ #27177]H.J. Lu3-1/+11
2021-01-07x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker [BZ #26717]H.J. Lu17-41/+607
2021-01-04Drop nan-pseudo-number.h usage from testsSiddhesh Poyarekar1-1/+0
2021-01-02Update copyright dates with scripts/update-copyrightsPaul Eggert81-81/+81
2020-12-30x86 long double: Consider pseudo numbers as signalingSiddhesh Poyarekar1-0/+30
2020-12-24Remove _ISOMAC check from <cpu-features.h>H.J. Lu1-81/+75
2020-12-24x86: Remove the duplicated CPU_FEATURE_CPU_PH.J. Lu1-2/+0
2020-12-24Partially revert 681900d29683722b1cb0a8e565a0585846ec5a61Siddhesh Poyarekar2-12/+1
2020-12-24x86 long double: Support pseudo numbers in isnanlSiddhesh Poyarekar1-0/+45
2020-12-24x86 long double: Support pseudo numbers in fpclassifylSiddhesh Poyarekar1-0/+46
2020-12-22<sys/platform/x86.h>: Add Intel LAM supportH.J. Lu2-0/+4
2020-12-14x86: Remove the default REP MOVSB threshold tunable value [BZ #27061]H.J. Lu1-2/+4
2020-12-11elf: Pass the fd to note processingSzabolcs Nagy1-3/+3
2020-12-04x86: Adjust tst-cpu-features-supports.c for GCC 11H.J. Lu1-5/+10
2020-12-04x86: Set RDRAND usable if CPU supports RDRANDH.J. Lu1-0/+1
2020-11-13x86: Remove UP macro. Define LOCK_PREFIX unconditionally.Florian Weimer1-7/+1
2020-10-28x86: Restore processing of cache size tunables in init_cacheinfoFlorian Weimer1-8/+4
2020-10-28x86: Optimizing memcpy for AMD Zen architecture.Sajan Karumanchi1-6/+26
2020-10-16x86: Initialize CPU info via IFUNC relocation [BZ 26203]H.J. Lu7-857/+943
2020-10-09<sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM supportH.J. Lu3-0/+18
2020-10-09<sys/platform/x86.h>: Add Intel HRESET supportH.J. Lu2-0/+4
2020-10-09<sys/platform/x86.h>: Add AVX-VNNI supportH.J. Lu3-0/+7
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