32bit memset-sse2.S fails with uneven cache size

32bit memset-sse2.S assumes cache size is multiple of 128 bytes.  If
it isn't true, memset-sse2.S will fail.  For example, a processor can
have 24576 KB L3 cache and 20 cores. That is 2516582 byte per core. Half
of it is 1258291, which isn't helpful for vector instructions.  This
patch rounds cache sizes to multiple of 256 bytes and adds "raw" cache
sizes.
(cherry picked from commit c0dde15b5dba7e02ce6f36eab3a4d1c166f9951b)

2 files changed, 22 insertions, 2 deletions

diff --git a/sysdeps/i386/i686/cacheinfo.c b/sysdeps/i386/i686/cacheinfo.c
index f8b7f52..3635961 100644
--- a/sysdeps/i386/i686/cacheinfo.c
+++ b/sysdeps/i386/i686/cacheinfo.c
@@ -1,7 +1,11 @@
 #define __x86_64_data_cache_size __x86_data_cache_size
+#define __x86_64_raw_data_cache_size __x86_raw_data_cache_size
 #define __x86_64_data_cache_size_half __x86_data_cache_size_half
+#define __x86_64_raw_data_cache_size_half __x86_raw_data_cache_size_half
 #define __x86_64_shared_cache_size __x86_shared_cache_size
+#define __x86_64_raw_shared_cache_size __x86_raw_shared_cache_size
 #define __x86_64_shared_cache_size_half __x86_shared_cache_size_half
+#define __x86_64_raw_shared_cache_size_half __x86_raw_shared_cache_size_half
 
 #define DISABLE_PREFETCHW
 #define DISABLE_PREFERRED_MEMORY_INSTRUCTION
diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c
index 5422037..eae54e7 100644
--- a/sysdeps/x86_64/cacheinfo.c
+++ b/sysdeps/x86_64/cacheinfo.c
@@ -455,13 +455,21 @@ __cache_sysconf (int name)
 
 
 /* Data cache size for use in memory and string routines, typically
-   L1 size.  */
+   L1 size, rounded to multiple of 256 bytes.  */
 long int __x86_64_data_cache_size_half attribute_hidden = 32 * 1024 / 2;
 long int __x86_64_data_cache_size attribute_hidden = 32 * 1024;
+/* Similar to __x86_64_data_cache_size_half, but not rounded.  */
+long int __x86_64_raw_data_cache_size_half attribute_hidden = 32 * 1024 / 2;
+/* Similar to __x86_64_data_cache_size, but not rounded.  */
+long int __x86_64_raw_data_cache_size attribute_hidden = 32 * 1024;
 /* Shared cache size for use in memory and string routines, typically
-   L2 or L3 size.  */
+   L2 or L3 size, rounded to multiple of 256 bytes.  */
 long int __x86_64_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
 long int __x86_64_shared_cache_size attribute_hidden = 1024 * 1024;
+/* Similar to __x86_64_shared_cache_size_half, but not rounded.  */
+long int __x86_64_raw_shared_cache_size_half attribute_hidden = 1024 * 1024 / 2;
+/* Similar to __x86_64_shared_cache_size, but not rounded.  */
+long int __x86_64_raw_shared_cache_size attribute_hidden = 1024 * 1024;
 
 #ifndef DISABLE_PREFETCHW
 /* PREFETCHW support flag for use in memory and string routines.  */
@@ -661,12 +669,20 @@ init_cacheinfo (void)
 
   if (data > 0)
     {
+      __x86_64_raw_data_cache_size_half = data / 2;
+      __x86_64_raw_data_cache_size = data;
+      /* Round data cache size to multiple of 256 bytes.  */
+      data = data & ~255L;
       __x86_64_data_cache_size_half = data / 2;
       __x86_64_data_cache_size = data;
     }
 
   if (shared > 0)
     {
+      __x86_64_raw_shared_cache_size_half = shared / 2;
+      __x86_64_raw_shared_cache_size = shared;
+      /* Round shared cache size to multiple of 256 bytes.  */
+      shared = shared & ~255L;
       __x86_64_shared_cache_size_half = shared / 2;
       __x86_64_shared_cache_size = shared;
     }