x86-64: Use fxsave/xsave/xsavec in _dl_runtime_resolve [BZ #21265]

In _dl_runtime_resolve, use fxsave/xsave/xsavec to preserve all vector,
mask and bound registers.  It simplifies _dl_runtime_resolve and supports
different calling conventions.  ld.so code size is reduced by more than
1 KB.  However, use fxsave/xsave/xsavec takes a little bit more cycles
than saving and restoring vector and bound registers individually.

Latency for _dl_runtime_resolve to lookup the function, foo, from one
shared library plus libc.so:

                             Before    After     Change

Westmere (SSE)/fxsave         345      866       151%
IvyBridge (AVX)/xsave         420      643       53%
Haswell (AVX)/xsave           713      1252      75%
Skylake (AVX+MPX)/xsavec      559      719       28%
Skylake (AVX512+MPX)/xsavec   145      272       87%
Ryzen (AVX)/xsavec            280      553       97%

This is the worst case where portion of time spent for saving and
restoring registers is bigger than majority of cases.  With smaller
_dl_runtime_resolve code size, overall performance impact is negligible.

On IvyBridge, differences in build and test time of binutils with lazy
binding GCC and binutils are noises.  On Westmere, differences in
bootstrap and "makc check" time of GCC 7 with lazy binding GCC and
binutils are also noises.

	[BZ #21265]
	* sysdeps/x86/cpu-features-offsets.sym (XSAVE_STATE_SIZE_OFFSET):
	New.
	* sysdeps/x86/cpu-features.c: Include <libc-internal.h>.
	(init_cpu_features): Set xsave_state_size and bit_XSAVEC_Usable
	if needed.
	* sysdeps/x86/cpu-features.h (bit_XSAVEC_Usable): New.
	(STATE_SAVE_OFFSET): Likewise.
	(STATE_SAVE_MASK): Likewise.
	[__ASSEMBLER__]: Include <cpu-features-offsets.h>.
	(cpu_features): Add xsave_state_size.
	(index_XSAVEC_Usable): New.
	* sysdeps/x86_64/dl-machine.h (elf_machine_runtime_setup):
	Replace _dl_runtime_resolve_sse, _dl_runtime_resolve_avx and
	_dl_runtime_resolve_avx512 with _dl_runtime_resolve_fxsave,
	_dl_runtime_resolve_xsave and _dl_runtime_resolve_xsavec.
	* sysdeps/x86_64/dl-trampoline.S: Include <cpu-features.h>.
	(DL_RUNTIME_UNALIGNED_VEC_SIZE): Removed.
	(DL_RUNTIME_RESOLVE_REALIGN_STACK): Check STATE_SAVE_ALIGNMENT
	instead of VEC_SIZE.
	(REGISTER_SAVE_BND0): Removed.
	(REGISTER_SAVE_BND1): Likewise.
	(REGISTER_SAVE_BND3): Likewise.
	(REGISTER_SAVE_RAX): Always defined to 0.
	(VMOV): Removed.
	(_dl_runtime_resolve_avx512): Likewise.
	(_dl_runtime_resolve_avx): Likewise.
	(_dl_runtime_resolve_sse): Likewise.
	(USE_FXSAVE): New.
	(_dl_runtime_resolve_fxsave): Likewise.
	(USE_XSAVE): Likewise.
	(_dl_runtime_resolve_xsave): Likewise.
	(USE_XSAVEC): Likewise.
	(_dl_runtime_resolve_xsavec): Likewise.
	* sysdeps/x86_64/dl-trampoline.h (_dl_runtime_resolve_avx512):
	Removed.
	(_dl_runtime_resolve_avx): Likewise.
	(_dl_runtime_resolve_sse): Likewise.
	(_dl_runtime_resolve_fxsave): New.
	(_dl_runtime_resolve_xsave): Likewise.
	(_dl_runtime_resolve_xsavec): Likewise.
	(_dl_runtime_profile): Defined only if _dl_runtime_profile is
	defined.

(cherry picked from commit b52b0d793dcb226ecb0ecca1e672ca265973233c)

3 files changed, 86 insertions, 0 deletions

diff --git a/sysdeps/x86/cpu-features-offsets.sym b/sysdeps/x86/cpu-features-offsets.sym
index a9d53d1..1415005 100644
--- a/sysdeps/x86/cpu-features-offsets.sym
+++ b/sysdeps/x86/cpu-features-offsets.sym
@@ -5,3 +5,5 @@
 #define rtld_global_ro_offsetof(mem) offsetof (struct rtld_global_ro, mem)
 
 RTLD_GLOBAL_RO_DL_X86_CPU_FEATURES_OFFSET rtld_global_ro_offsetof (_dl_x86_cpu_features)
+
+XSAVE_STATE_SIZE_OFFSET	offsetof (struct cpu_features, xsave_state_size)
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 218ff2b..2060fa3 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -18,6 +18,7 @@
 
 #include <cpuid.h>
 #include <cpu-features.h>
+#include <libc-internal.h>
 
 static inline void
 get_common_indeces (struct cpu_features *cpu_features,
@@ -225,6 +226,71 @@ init_cpu_features (struct cpu_features *cpu_features)
 	  /* Determine if FMA4 is usable.  */
 	  if (HAS_CPU_FEATURE (FMA4))
 	    cpu_features->feature[index_FMA4_Usable] |= bit_FMA4_Usable;
+
+	  /* For _dl_runtime_resolve, set xsave_state_size to xsave area
+	     size + integer register save size and align it to 64 bytes.  */
+	  if (cpu_features->max_cpuid >= 0xd)
+	    {
+	      unsigned int eax, ebx, ecx, edx;
+
+	      __cpuid_count (0xd, 0, eax, ebx, ecx, edx);
+	      if (ebx != 0)
+		{
+		  cpu_features->xsave_state_size
+		= ALIGN_UP (ebx + STATE_SAVE_OFFSET, 64);
+
+		  __cpuid_count (0xd, 1, eax, ebx, ecx, edx);
+
+		  /* Check if XSAVEC is available.  */
+		  if ((eax & (1 << 1)) != 0)
+		    {
+		      unsigned int xstate_comp_offsets[32];
+		      unsigned int xstate_comp_sizes[32];
+		      unsigned int i;
+
+		      xstate_comp_offsets[0] = 0;
+		      xstate_comp_offsets[1] = 160;
+		      xstate_comp_offsets[2] = 576;
+		      xstate_comp_sizes[0] = 160;
+		      xstate_comp_sizes[1] = 256;
+
+		      for (i = 2; i < 32; i++)
+			{
+			  if ((STATE_SAVE_MASK & (1 << i)) != 0)
+			    {
+			      __cpuid_count (0xd, i, eax, ebx, ecx, edx);
+			      xstate_comp_sizes[i] = eax;
+			    }
+			  else
+			    {
+			      ecx = 0;
+			      xstate_comp_sizes[i] = 0;
+			    }
+
+			  if (i > 2)
+			    {
+			      xstate_comp_offsets[i]
+				= (xstate_comp_offsets[i - 1]
+				   + xstate_comp_sizes[i -1]);
+			      if ((ecx & (1 << 1)) != 0)
+				xstate_comp_offsets[i]
+			      = ALIGN_UP (xstate_comp_offsets[i], 64);
+			    }
+			}
+
+		      /* Use XSAVEC.  */
+		      unsigned int size
+			= xstate_comp_offsets[31] + xstate_comp_sizes[31];
+		      if (size)
+			{
+			  cpu_features->xsave_state_size
+			    = ALIGN_UP (size + STATE_SAVE_OFFSET, 64);
+			  cpu_features->feature[index_XSAVEC_Usable]
+			    |= bit_XSAVEC_Usable;
+			}
+		    }
+		}
+	    }
 	}
     }
 
diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h
index e354920..ca39751 100644
--- a/sysdeps/x86/cpu-features.h
+++ b/sysdeps/x86/cpu-features.h
@@ -35,6 +35,7 @@
 #define bit_I686			(1 << 15)
 #define bit_Prefer_MAP_32BIT_EXEC	(1 << 16)
 #define bit_Prefer_No_VZEROUPPER	(1 << 17)
+#define bit_XSAVEC_Usable		(1 << 18)
 
 /* CPUID Feature flags.  */
 
@@ -70,10 +71,20 @@
 /* The current maximum size of the feature integer bit array.  */
 #define FEATURE_INDEX_MAX 1
 
+/* Offset for fxsave/xsave area used by _dl_runtime_resolve.  Also need
+   space to preserve RCX, RDX, RSI, RDI, R8, R9 and RAX.  It must be
+   aligned to 16 bytes for fxsave and 64 bytes for xsave.  */
+#define STATE_SAVE_OFFSET (8 * 7 + 8)
+
+/* Save SSE, AVX, AVX512, mask and bound registers.  */
+#define STATE_SAVE_MASK \
+  ((1 << 1) | (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | (1 << 7))
+
 #ifdef	__ASSEMBLER__
 
 # include <ifunc-defines.h>
 # include <rtld-global-offsets.h>
+# include <cpu-features-offsets.h>
 
 # define index_CX8	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
 # define index_CMOV	COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET
@@ -185,6 +196,12 @@ struct cpu_features
   } cpuid[COMMON_CPUID_INDEX_MAX];
   unsigned int family;
   unsigned int model;
+  /* The type must be unsigned long int so that we use
+
+	sub xsave_state_size_offset(%rip) %RSP_LP
+
+     in _dl_runtime_resolve.  */
+  unsigned long int xsave_state_size;
   unsigned int feature[FEATURE_INDEX_MAX];
 };
 
@@ -255,6 +272,7 @@ extern const struct cpu_features *__get_cpu_features (void)
 # define index_I686			FEATURE_INDEX_1
 # define index_Prefer_MAP_32BIT_EXEC	FEATURE_INDEX_1
 # define index_Prefer_No_VZEROUPPER     FEATURE_INDEX_1
+# define index_XSAVEC_Usable		FEATURE_INDEX_1
 
 #endif	/* !__ASSEMBLER__ */