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| author | H.J. Lu <hjl.tools@gmail.com> | 2016-03-28 19:22:59 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2016-03-28 19:23:31 -0700 |
| commit | 0791f91dff9a77263fa8173b143d854cad902c6d (patch) | |
| tree | 72a8411f6e8a1f8e6edfcdc93ed79789000c71a2 /nscd/nscd_conf.c | |
| parent | 9ff9351d028d43af1cc2eaf432004ada0996bbf0 (diff) | |
| download | glibc-0791f91dff9a77263fa8173b143d854cad902c6d.zip glibc-0791f91dff9a77263fa8173b143d854cad902c6d.tar.gz glibc-0791f91dff9a77263fa8173b143d854cad902c6d.tar.bz2 | |
Initial Enhanced REP MOVSB/STOSB (ERMS) support
The newer Intel processors support Enhanced REP MOVSB/STOSB (ERMS) which
has a feature bit in CPUID. This patch adds the Enhanced REP MOVSB/STOSB
(ERMS) bit to x86 cpu-features.
* sysdeps/x86/cpu-features.h (bit_cpu_ERMS): New.
(index_cpu_ERMS): Likewise.
(reg_ERMS): Likewise.
Diffstat (limited to 'nscd/nscd_conf.c')
0 files changed, 0 insertions, 0 deletions