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authorTejas Belagod <Tejas.Belagod@arm.com>2022-06-27 18:00:50 +0000
committerSzabolcs Nagy <szabolcs.nagy@arm.com>2022-06-30 14:01:08 +0100
commite9dd3682963a7038d699430e3ece68045b6caafc (patch)
tree6291bcded33b627d881c13aa161cd4329b12b4b6 /manual
parent71d87d85bf54f6522813aec97c19bdd24997341e (diff)
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AArch64: Add asymmetric faulting mode for tag violations in mem.tagging tunable
The new asymmetric mode is available when HWCAP2_MTE3 is set (support is available), bit2 is set in the tunable (user request per application), and the system is configured such that the asymmetric mode is preferred over sync or async (per-cpu system-wide setting). Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
Diffstat (limited to 'manual')
-rw-r--r--manual/tunables.texi3
1 files changed, 3 insertions, 0 deletions
diff --git a/manual/tunables.texi b/manual/tunables.texi
index 2c07601..83cdcda 100644
--- a/manual/tunables.texi
+++ b/manual/tunables.texi
@@ -602,6 +602,9 @@ Bit 1 enables precise faulting mode for tag violations on systems that
support deferred tag violation reporting. This may cause programs
to run more slowly.
+Bit 2 enables either precise or deferred faulting mode for tag violations
+whichever is preferred by the system.
+
Other bits are currently reserved.
@Theglibc{} startup code will automatically enable memory tagging