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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2015-01-11 19:33:17 -0600 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2015-01-14 07:58:04 -0500 |
| commit | 6831ddb38379c1924bd19b3203d161a4c3ed1e2e (patch) | |
| tree | 4466f71de1e366b05ce851e1e3ec9f3b49ca6e78 /ChangeLog | |
| parent | 473b6083820fd156985bf7b2cb60db9d4031b536 (diff) | |
| download | glibc-6831ddb38379c1924bd19b3203d161a4c3ed1e2e.zip glibc-6831ddb38379c1924bd19b3203d161a4c3ed1e2e.tar.gz glibc-6831ddb38379c1924bd19b3203d161a4c3ed1e2e.tar.bz2 | |
powerpc: Fix POWER7/PPC64 performance regression on LE
This patch fixes a performance regression on the POWER7/PPC64 memcmp
porting for Little Endian. The LE code uses 'ldbrx' instruction to read
the memory on byte reversed form, however ISA 2.06 just provide the indexed
form which uses a register value as additional index, instead of a fixed value
enconded in the instruction.
And the port strategy for LE uses r0 index value and update the address
value on each compare loop interation. For large compare size values,
it adds 8 more instructions plus some more depending of trailing
size. This patch fixes it by adding pre-calculate indexes to remove the
address update on loops and tailing sizes.
For large sizes it shows a considerable gain, with double performance
pairing with BE.
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -1,5 +1,8 @@ 2015-01-13 Adhemerval Zanella <azanella@linux.vnet.ibm.com> + * sysdeps/powerpc/powerpc64/power7/memcmp.S (memcmp): Fix performance + regression on LE. + * sysdeps/powerpc/powerpc64/multiarch/strncmp-power8.S: New file. * sysdeps/powerpc/powerpc64/power8/strncmp.S: New file. * sysdeps/powerpc/powerpc64/multiarch/Makefile [sysdep_routines]: Add |