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| author | Noah Goldstein <goldstein.w.n@gmail.com> | 2023-08-11 18:37:27 -0500 |
|---|---|---|
| committer | Noah Goldstein <goldstein.w.n@gmail.com> | 2023-09-11 22:47:26 -0500 |
| commit | ed4ceabea12dc3748f7ee390187744c8d1911510 (patch) | |
| tree | 7fd5aebdafeb42031a43834e3aa93a40f172f255 | |
| parent | 05c28930951588234226567227350c2339844f3d (diff) | |
| download | glibc-ed4ceabea12dc3748f7ee390187744c8d1911510.zip glibc-ed4ceabea12dc3748f7ee390187744c8d1911510.tar.gz glibc-ed4ceabea12dc3748f7ee390187744c8d1911510.tar.bz2 | |
x86: Use `3/4*sizeof(per-thread-L3)` as low bound for NT threshold.
On some machines we end up with incomplete cache information. This can
make the new calculation of `sizeof(total-L3)/custom-divisor` end up
lower than intended (and lower than the prior value). So reintroduce
the old bound as a lower bound to avoid potentially regressing code
where we don't have complete information to make the decision.
Reviewed-by: DJ Delorie <dj@redhat.com>
(cherry picked from commit 8b9a0af8ca012217bf90d1dc0694f85b49ae09da)
| -rw-r--r-- | sysdeps/x86/cacheinfo.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c index 47a2487..6c0a80d 100644 --- a/sysdeps/x86/cacheinfo.c +++ b/sysdeps/x86/cacheinfo.c @@ -891,12 +891,21 @@ init_cacheinfo (void) modern HW detects streaming patterns and provides proper LRU hints so that the maximum thrashing capped at 1/associativity. */ unsigned long int non_temporal_threshold = shared / 4; + + /* If the computed non_temporal_threshold <= 3/4 * per-thread L3, we most + likely have incorrect/incomplete cache info in which case, default to + 3/4 * per-thread L3 to avoid regressions. */ + unsigned long int non_temporal_threshold_lowbound + = shared_per_thread * 3 / 4; + if (non_temporal_threshold < non_temporal_threshold_lowbound) + non_temporal_threshold = non_temporal_threshold_lowbound; + /* If no ERMS, we use the per-thread L3 chunking. Normal cacheable stores run a higher risk of actually thrashing the cache as they don't have a HW LRU hint. As well, their performance in highly parallel situations is noticeably worse. */ if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS)) - non_temporal_threshold = shared_per_thread * 3 / 4; + non_temporal_threshold = non_temporal_threshold_lowbound; __x86_shared_non_temporal_threshold = (cpu_features->non_temporal_threshold != 0 |