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authorH.J. Lu <hjl.tools@gmail.com>2023-04-05 09:21:32 -0700
committerH.J. Lu <hjl.tools@gmail.com>2023-04-05 14:46:10 -0700
commitfb90dc8513f67d1cc0578452aee3459e9b9ab626 (patch)
treec40b25f3cd7dde99191abb96f235f5a8ac0bdc62
parentf47b7d96fbecc6a81c144e7d152b1cb748efd682 (diff)
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<sys/platform/x86.h>: Add LBR support
Add architectural LBR support to <sys/platform/x86.h>. Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
-rw-r--r--manual/platform.texi3
-rw-r--r--sysdeps/x86/bits/platform/x86.h2
-rw-r--r--sysdeps/x86/tst-get-cpu-features.c1
3 files changed, 5 insertions, 1 deletions
diff --git a/manual/platform.texi b/manual/platform.texi
index 2ab687c..b72518e 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -407,6 +407,9 @@ the indirect branch predictor barrier (IBPB).
@code{LAM} -- Linear Address Masking.
@item
+@code{LBR} -- Architectural LBR.
+
+@item
@code{LM} -- Long mode.
@item
diff --git a/sysdeps/x86/bits/platform/x86.h b/sysdeps/x86/bits/platform/x86.h
index 6d9dd6d..1040c2a 100644
--- a/sysdeps/x86/bits/platform/x86.h
+++ b/sysdeps/x86/bits/platform/x86.h
@@ -219,7 +219,7 @@ enum
x86_cpu_TSXLDTRK = x86_cpu_index_7_edx + 16,
x86_cpu_INDEX_7_EDX_17 = x86_cpu_index_7_edx + 17,
x86_cpu_PCONFIG = x86_cpu_index_7_edx + 18,
- x86_cpu_INDEX_7_EDX_19 = x86_cpu_index_7_edx + 19,
+ x86_cpu_LBR = x86_cpu_index_7_edx + 19,
x86_cpu_IBT = x86_cpu_index_7_edx + 20,
x86_cpu_INDEX_7_EDX_21 = x86_cpu_index_7_edx + 21,
x86_cpu_AMX_BF16 = x86_cpu_index_7_edx + 22,
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index 8b7e70ae..cfc8692 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -166,6 +166,7 @@ do_test (void)
CHECK_CPU_FEATURE_PRESENT (SERIALIZE);
CHECK_CPU_FEATURE_PRESENT (HYBRID);
CHECK_CPU_FEATURE_PRESENT (TSXLDTRK);
+ CHECK_CPU_FEATURE_PRESENT (LBR);
CHECK_CPU_FEATURE_PRESENT (PCONFIG);
CHECK_CPU_FEATURE_PRESENT (IBT);
CHECK_CPU_FEATURE_PRESENT (AMX_BF16);