From 15091ded14ec08bd3f3a686d420c6009e1d2c518 Mon Sep 17 00:00:00 2001
From: Yoshinori Sato <ysato@users.sourceforge.jp>
Date: Tue, 4 May 2021 22:22:58 +0900
Subject: sim: h8300 special case test

In "mov. [bwl] reg, @ -reg", added a special case test
using the same register.
---
 sim/testsuite/h8300/ChangeLog |  6 ++++++
 sim/testsuite/h8300/movb.s    | 13 +++++++++++--
 sim/testsuite/h8300/movl.s    | 10 ++++++++++
 sim/testsuite/h8300/movw.s    | 10 ++++++++++
 4 files changed, 37 insertions(+), 2 deletions(-)

(limited to 'sim')

diff --git a/sim/testsuite/h8300/ChangeLog b/sim/testsuite/h8300/ChangeLog
index 3a91705..17c4ac1 100644
--- a/sim/testsuite/h8300/ChangeLog
+++ b/sim/testsuite/h8300/ChangeLog
@@ -1,3 +1,9 @@
+2021-05-04  Yoshinori Sato  <ysato@users.sourceforge.jp>
+
+	* movb.s: Add special case predec test.
+	* movw.s: Likewise.
+	* movl.s: Likewise.
+
 2021-04-08  Mike Frysinger  <vapier@gentoo.org>
 
 	* allinsn.exp (arch): Delete.
diff --git a/sim/testsuite/h8300/movb.s b/sim/testsuite/h8300/movb.s
index 87dcdf3..06d7611 100644
--- a/sim/testsuite/h8300/movb.s
+++ b/sim/testsuite/h8300/movb.s
@@ -1,4 +1,4 @@
-# Hitachi H8 testcase 'mov.w'
+# Hitachi H8 testcase 'mov.b'
 # mach(): h8300h h8300s h8sx
 # as(h8300h):	--defsym sim_cpu=1
 # as(h8300s):	--defsym sim_cpu=2
@@ -792,6 +792,16 @@ mov_b_reg8_to_predec:		; pre-decrement from register to mem
 	beq	.Lnext48
 	fail
 .Lnext48:
+	;; Special case in same register
+	;; CCR confirmation omitted
+	mov.l	#byte_dst+1, er1
+	mov.l	er1, er0
+	mov.b	r0l, @-er0
+	mov.b	@byte_dst, r0l
+	cmp.b	r1l, r0l
+	beq	.Lnext47
+	fail
+.Lnext47:
 	mov.b	#0, r0l
 	mov.b	r0l, @byte_dst	; zero it again for the next use.
 
@@ -2218,4 +2228,3 @@ mov_b_abs32_to_abs32:		; 32-bit absolute addr, memory to memory
 
 fail1:
 	fail
-	
\ No newline at end of file
diff --git a/sim/testsuite/h8300/movl.s b/sim/testsuite/h8300/movl.s
index dcc3922..63a8613 100644
--- a/sim/testsuite/h8300/movl.s
+++ b/sim/testsuite/h8300/movl.s
@@ -1282,6 +1282,16 @@ mov_l_reg32_to_predec:		; pre-decrement from register to mem
 	beq	.Lnext48
 	fail
 .Lnext48:
+	;; Special case in same register
+	;; CCR confirmation omitted
+	mov.l	#long_dst+4, er1
+	mov.l	er1, er0
+	mov.l	er0, @-er0
+	mov.l	@long_dst, er0
+	cmp.l	er1, er0
+	beq	.Lnext47
+	fail
+.Lnext47:
 	mov.l	#0, er0
 	mov.l	er0, @long_dst	; zero it again for the next use.
 
diff --git a/sim/testsuite/h8300/movw.s b/sim/testsuite/h8300/movw.s
index b8b09ea..2502b36 100644
--- a/sim/testsuite/h8300/movw.s
+++ b/sim/testsuite/h8300/movw.s
@@ -988,6 +988,16 @@ mov_w_reg16_to_predec:		; pre-decrement from register to mem
 	beq	.Lnext48
 	fail
 .Lnext48:
+	;; Special case in same register
+	;; CCR confirmation omitted
+	mov.l	#word_dst+2, er1
+	mov.l	er1, er0
+	mov.w	r0, @-er0
+	mov.w	@word_dst, r0
+	cmp.w	r1, r0
+	beq	.Lnext47
+	fail
+.Lnext47:
 	mov.w	#0, r0
 	mov.w	r0, @word_dst	; zero it again for the next use.
 
-- 
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