From 800eeca487f145ccc5481a03bfff2b871a2fd361 Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Fri, 21 Apr 2000 20:22:24 +0000 Subject: IA-64 ELF support. --- opcodes/ChangeLog | 23 + opcodes/Makefile.am | 34 + opcodes/Makefile.in | 34 + opcodes/configure | 1 + opcodes/configure.in | 1 + opcodes/disassemble.c | 6 + opcodes/ia64-asmtab.c | 5580 +++++++++++++++++++++++++++++++++++++++++++++++++ opcodes/ia64-asmtab.h | 145 ++ opcodes/ia64-dis.c | 264 +++ opcodes/ia64-gen.c | 2723 ++++++++++++++++++++++++ opcodes/ia64-ic.tbl | 205 ++ opcodes/ia64-opc-a.c | 364 ++++ opcodes/ia64-opc-b.c | 486 +++++ opcodes/ia64-opc-d.c | 12 + opcodes/ia64-opc-f.c | 625 ++++++ opcodes/ia64-opc-i.c | 296 +++ opcodes/ia64-opc-m.c | 1042 +++++++++ opcodes/ia64-opc-x.c | 178 ++ opcodes/ia64-opc.c | 741 +++++++ opcodes/ia64-opc.h | 129 ++ opcodes/ia64-raw.tbl | 171 ++ opcodes/ia64-war.tbl | 2 + opcodes/ia64-waw.tbl | 125 ++ 23 files changed, 13187 insertions(+) create mode 100644 opcodes/ia64-asmtab.c create mode 100644 opcodes/ia64-asmtab.h create mode 100644 opcodes/ia64-dis.c create mode 100644 opcodes/ia64-gen.c create mode 100644 opcodes/ia64-ic.tbl create mode 100644 opcodes/ia64-opc-a.c create mode 100644 opcodes/ia64-opc-b.c create mode 100644 opcodes/ia64-opc-d.c create mode 100644 opcodes/ia64-opc-f.c create mode 100644 opcodes/ia64-opc-i.c create mode 100644 opcodes/ia64-opc-m.c create mode 100644 opcodes/ia64-opc-x.c create mode 100644 opcodes/ia64-opc.c create mode 100644 opcodes/ia64-opc.h create mode 100644 opcodes/ia64-raw.tbl create mode 100644 opcodes/ia64-war.tbl create mode 100644 opcodes/ia64-waw.tbl (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8c529a8..bb18a8a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,26 @@ +Fri Apr 21 13:20:53 2000 Richard Henderson + David Mosberger + Timothy Wall + Bob Manson + Jim Wilson + + * Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h. + (CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c, + ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c, + ia64-asmtab.c. + (ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo. + (ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen, + ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules. + * Makefile.in: Rebuild. + * configure Rebuild. + * configure.in (bfd_ia64_arch): New target. + * disassemble.c (ARCH_ia64): Define. + (disassembler): Support ARCH_ia64. + * ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl, + ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c, + ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl, + ia64-war.tbl, ia64-waw.tbl): New files. + 2000-04-20 Alexandre Oliva * m10300-dis.c (HAVE_AM30, HAVE_AM33): Define. diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index 1f44cdc..3b21289 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -25,6 +25,8 @@ HFILES = \ mcore-opc.h \ sh-opc.h \ sysdep.h \ + ia64-asmtab.h \ + ia64-opc.h \ w65-opc.h \ z8k-opc.h @@ -58,6 +60,16 @@ CFILES = \ i370-opc.c \ i386-dis.c \ i960-dis.c \ + ia64-dis.c \ + ia64-opc-a.c \ + ia64-opc-b.c \ + ia64-opc-f.c \ + ia64-opc-i.c \ + ia64-opc-m.c \ + ia64-opc-d.c \ + ia64-opc.c \ + ia64-gen.c \ + ia64-asmtab.c \ m32r-asm.c \ m32r-desc.c \ m32r-dis.c \ @@ -120,6 +132,8 @@ ALL_MACHINES = \ i370-dis.lo \ i370-opc.lo \ i960-dis.lo \ + ia64-dis.lo \ + ia64-opc.lo \ m32r-asm.lo \ m32r-desc.lo \ m32r-dis.lo \ @@ -202,6 +216,23 @@ CLEANFILES = \ +ia64-ic.tbl: $(srcdir)/ia64-ic.tbl + $(LN_S) -f $(srcdir)/ia64-ic.tbl +ia64-raw.tbl: $(srcdir)/ia64-raw.tbl + $(LN_S) -f $(srcdir)/ia64-raw.tbl +ia64-waw.tbl: $(srcdir)/ia64-waw.tbl + $(LN_S) -f $(srcdir)/ia64-waw.tbl +ia64-war.tbl: $(srcdir)/ia64-war.tbl + $(LN_S) -f $(srcdir)/ia64-war.tbl + +ia64-gen: ia64-gen.o + $(LINK) ia64-gen.o $(LIBIBERTY) + +ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \ + ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h + +ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl + ./ia64-gen > $(srcdir)/ia64-asmtab.c # This dependency stuff is copied from BFD. @@ -315,6 +346,9 @@ i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h sysdep.h config.h opintl.h i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) +ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ia64.h $(BFD_H) +ia64-opc.lo: $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/libiberty.h \ + $(INCDIR)/ansidecl.h sysdep.h ia64-asmtab.h ia64-asmtab.c m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h opintl.h diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 7e64477..5d25c9a 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -128,6 +128,8 @@ HFILES = \ mcore-opc.h \ sh-opc.h \ sysdep.h \ + ia64-asmtab.h \ + ia64-opc.h \ w65-opc.h \ z8k-opc.h @@ -162,6 +164,16 @@ CFILES = \ i370-opc.c \ i386-dis.c \ i960-dis.c \ + ia64-dis.c \ + ia64-opc-a.c \ + ia64-opc-b.c \ + ia64-opc-f.c \ + ia64-opc-i.c \ + ia64-opc-m.c \ + ia64-opc-d.c \ + ia64-opc.c \ + ia64-gen.c \ + ia64-asmtab.c \ m32r-asm.c \ m32r-desc.c \ m32r-dis.c \ @@ -225,6 +237,8 @@ ALL_MACHINES = \ i370-dis.lo \ i370-opc.lo \ i960-dis.lo \ + ia64-dis.lo \ + ia64-opc.lo \ m32r-asm.lo \ m32r-desc.lo \ m32r-dis.lo \ @@ -676,6 +690,23 @@ all-redirect all-am all installdirs-am installdirs mostlyclean-generic \ distclean-generic clean-generic maintainer-clean-generic clean \ mostlyclean distclean maintainer-clean +ia64-ic.tbl: $(srcdir)/ia64-ic.tbl + $(LN_S) -f $(srcdir)/ia64-ic.tbl +ia64-raw.tbl: $(srcdir)/ia64-raw.tbl + $(LN_S) -f $(srcdir)/ia64-raw.tbl +ia64-waw.tbl: $(srcdir)/ia64-waw.tbl + $(LN_S) -f $(srcdir)/ia64-waw.tbl +ia64-war.tbl: $(srcdir)/ia64-war.tbl + $(LN_S) -f $(srcdir)/ia64-war.tbl + +ia64-gen: ia64-gen.o + $(LINK) ia64-gen.o $(LIBIBERTY) + +ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \ + ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h + +ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl + ./ia64-gen > $(srcdir)/ia64-asmtab.c disassemble.lo: disassemble.c $(INCDIR)/dis-asm.h $(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/disassemble.c @@ -812,6 +843,9 @@ i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h sysdep.h config.h opintl.h i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) +ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ia64.h $(BFD_H) +ia64-opc.lo: $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/libiberty.h \ + $(INCDIR)/ansidecl.h sysdep.h ia64-asmtab.h ia64-asmtab.c m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h opintl.h diff --git a/opcodes/configure b/opcodes/configure index 1b30f7e..99a7d20 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -3955,6 +3955,7 @@ if test x${all_targets} = xfalse ; then bfd_i386_arch) ta="$ta i386-dis.lo" ;; bfd_i860_arch) ;; bfd_i960_arch) ta="$ta i960-dis.lo" ;; + bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; diff --git a/opcodes/configure.in b/opcodes/configure.in index 6895c57..847897b 100644 --- a/opcodes/configure.in +++ b/opcodes/configure.in @@ -166,6 +166,7 @@ if test x${all_targets} = xfalse ; then bfd_i386_arch) ta="$ta i386-dis.lo" ;; bfd_i860_arch) ;; bfd_i960_arch) ta="$ta i960-dis.lo" ;; + bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; bfd_m68k_arch) ta="$ta m68k-dis.lo m68k-opc.lo" ;; bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 373b652..479e9e7 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -33,6 +33,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_i370 #define ARCH_i386 #define ARCH_i960 +#define ARCH_ia64 #define ARCH_fr30 #define ARCH_m32r #define ARCH_m68k @@ -147,6 +148,11 @@ disassembler (abfd) disassemble = print_insn_i960; break; #endif +#ifdef ARCH_ia64 + case bfd_arch_ia64: + disassemble = print_insn_ia64; + break; +#endif #ifdef ARCH_fr30 case bfd_arch_fr30: disassemble = print_insn_fr30; diff --git a/opcodes/ia64-asmtab.c b/opcodes/ia64-asmtab.c new file mode 100644 index 0000000..6b30ec6 --- /dev/null +++ b/opcodes/ia64-asmtab.c @@ -0,0 +1,5580 @@ +/* This file is automatically generated by ia64-gen. Do not edit! */ +static const char *ia64_strings[] = { + "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and", + "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call", + "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmpxchg1", + "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop", "czx1", + "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", "exit", + "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", "fandcm", + "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", "fetchadd4", + "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", "fmerge", "fmin", + "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", "fnmpy", "fnorm", "for", + "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", "fpcvt", "fpma", "fpmax", + "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", "fpnegabs", "fpnma", + "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", "fselect", "fsetc", + "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", "g", "ga", "ge", + "getf", "geu", "gt", "gtu", "h", "hu", "i", "ia", "imp", "invala", "itc", + "itr", "l", "ld1", "ld2", "ld4", "ld8", "ldf", "ldf8", "ldfd", "ldfe", + "ldfp8", "ldfpd", "ldfps", "ldfs", "le", "leu", "lfetch", "loadrs", + "loop", "lr", "lt", "ltu", "lu", "m", "many", "mf", "mix1", "mix2", + "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne", "neq", "nge", "ngt", + "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1", "nt2", "nta", "nz", + "or", "orcm", "ord", "pack2", "pack4", "padd1", "padd2", "padd4", "pavg1", + "pavg2", "pavgsub1", "pavgsub2", "pcmp1", "pcmp2", "pcmp4", "pmax1", + "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2", "popcnt", "pr", "probe", + "psad1", "pshl2", "pshl4", "pshladd2", "pshr2", "pshr4", "pshradd2", + "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz", "rel", "ret", "rfi", + "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3", "sa", "se", "setf", + "shl", "shladd", "shladdp4", "shr", "shrp", "sig", "spill", "spnt", + "sptk", "srlz", "ssm", "sss", "st1", "st2", "st4", "st8", "stf", "stf8", + "stfd", "stfe", "stfs", "sub", "sum", "sxt1", "sxt2", "sxt4", "sync", + "tak", "tbit", "thash", "tnat", "tpa", "trunc", "ttag", "u", "unc", + "unord", "unpack1", "unpack2", "unpack4", "uss", "uus", "uuu", "w", + "wexit", "wtop", "x", "xchg1", "xchg2", "xchg4", "xchg8", "xf", "xma", + "xmpy", "xor", "xuf", "z", "zxt1", "zxt2", "zxt4", +}; + +static const struct ia64_dependency +dependencies[] = { + { "ALAT", 0, 0, 0, -1, }, + { "AR[BSP]", 25, 0, 2, 17, }, + { "AR[BSPSTORE]", 25, 0, 2, 18, }, + { "AR[CCV]", 25, 0, 2, 32, }, + { "AR[EC]", 25, 0, 2, 66, }, + { "AR[FPSR].sf0.controls", 29, 0, 2, -1, }, + { "AR[FPSR].sf1.controls", 29, 0, 2, -1, }, + { "AR[FPSR].sf2.controls", 29, 0, 2, -1, }, + { "AR[FPSR].sf3.controls", 29, 0, 2, -1, }, + { "AR[FPSR].sf0.flags", 29, 0, 2, -1, }, + { "AR[FPSR].sf1.flags", 29, 0, 2, -1, }, + { "AR[FPSR].sf2.flags", 29, 0, 2, -1, }, + { "AR[FPSR].sf3.flags", 29, 0, 2, -1, }, + { "AR[FPSR].traps", 29, 0, 2, -1, }, + { "AR[FPSR].rv", 29, 0, 2, -1, }, + { "AR[ITC]", 25, 0, 2, 44, }, + { "AR[K%], % in 0 - 7", 1, 0, 2, -1, }, + { "AR[LC]", 25, 0, 2, 65, }, + { "AR[PFS]", 25, 0, 2, 64, }, + { "AR[PFS]", 25, 0, 2, 64, }, + { "AR[PFS]", 25, 0, 0, 64, }, + { "AR[RNAT]", 25, 0, 2, 19, }, + { "AR[RSC]", 25, 0, 2, 16, }, + { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, }, + { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, }, + { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, }, + { "BR%, % in 0 - 7", 5, 0, 2, -1, }, + { "BR%, % in 0 - 7", 5, 0, 0, -1, }, + { "BR%, % in 0 - 7", 5, 0, 2, -1, }, + { "CFM", 6, 0, 2, -1, }, + { "CFM", 6, 0, 2, -1, }, + { "CFM", 6, 0, 2, -1, }, + { "CFM", 6, 0, 2, -1, }, + { "CFM", 6, 0, 0, -1, }, + { "CPUID#", 7, 0, 5, -1, }, + { "CR[CMCV]", 26, 0, 3, 74, }, + { "CR[DCR]", 26, 0, 3, 0, }, + { "CR[EOI]", 26, 0, 6, 67, "SC Section 10.8.3.4", }, + { "CR[GPTA]", 26, 0, 3, 9, }, + { "CR[IFA]", 26, 0, 1, 20, }, + { "CR[IFA]", 26, 0, 3, 20, }, + { "CR[IFS]", 26, 0, 3, 23, }, + { "CR[IFS]", 26, 0, 1, 23, }, + { "CR[IFS]", 26, 0, 1, 23, }, + { "CR[IHA]", 26, 0, 3, 25, }, + { "CR[IIM]", 26, 0, 3, 24, }, + { "CR[IIP]", 26, 0, 3, 19, }, + { "CR[IIP]", 26, 0, 1, 19, }, + { "CR[IIPA]", 26, 0, 3, 22, }, + { "CR[IPSR]", 26, 0, 3, 16, }, + { "CR[IPSR]", 26, 0, 1, 16, }, + { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, }, + { "CR[ISR]", 26, 0, 3, 17, }, + { "CR[ITIR]", 26, 0, 3, 21, }, + { "CR[ITIR]", 26, 0, 1, 21, }, + { "CR[ITM]", 26, 0, 3, 1, }, + { "CR[ITV]", 26, 0, 3, 72, }, + { "CR[IVA]", 26, 0, 4, 2, }, + { "CR[IVR]", 26, 0, 6, 65, "SC Section 10.8.3.2", }, + { "CR[LID]", 26, 0, 6, 64, "SC Section 10.8.3.1", }, + { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, }, + { "CR[PMV]", 26, 0, 3, 73, }, + { "CR[PTA]", 26, 0, 3, 8, }, + { "CR[TPR]", 26, 0, 3, 66, }, + { "CR[TPR]", 26, 0, 6, 66, "SC Section 10.8.3.3", }, + { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, }, + { "DBR#", 11, 0, 2, -1, }, + { "DBR#", 11, 0, 3, -1, }, + { "DTC", 0, 0, 3, -1, }, + { "DTC", 0, 0, 2, -1, }, + { "DTC", 0, 0, 0, -1, }, + { "DTC", 0, 0, 2, -1, }, + { "DTC_LIMIT*", 0, 0, 2, -1, }, + { "DTR", 0, 0, 3, -1, }, + { "DTR", 0, 0, 2, -1, }, + { "DTR", 0, 0, 3, -1, }, + { "DTR", 0, 0, 0, -1, }, + { "DTR", 0, 0, 2, -1, }, + { "FR%, % in 0 - 1", 12, 0, 0, -1, }, + { "FR%, % in 2 - 127", 13, 0, 2, -1, }, + { "FR%, % in 2 - 127", 13, 0, 0, -1, }, + { "GR0", 14, 0, 0, -1, }, + { "GR%, % in 1 - 127", 15, 0, 0, -1, }, + { "GR%, % in 1 - 127", 15, 0, 2, -1, }, + { "IBR#", 16, 0, 2, -1, }, + { "InService*", 17, 0, 3, -1, }, + { "InService*", 17, 0, 2, -1, }, + { "InService*", 17, 0, 2, -1, }, + { "IP", 0, 0, 0, -1, }, + { "ITC", 0, 0, 4, -1, }, + { "ITC", 0, 0, 2, -1, }, + { "ITC", 0, 0, 0, -1, }, + { "ITC", 0, 0, 4, -1, }, + { "ITC", 0, 0, 2, -1, }, + { "ITC_LIMIT*", 0, 0, 2, -1, }, + { "ITR", 0, 0, 2, -1, }, + { "ITR", 0, 0, 4, -1, }, + { "ITR", 0, 0, 2, -1, }, + { "ITR", 0, 0, 0, -1, }, + { "ITR", 0, 0, 4, -1, }, + { "memory", 0, 0, 0, -1, }, + { "MSR#", 18, 0, 5, -1, }, + { "PKR#", 19, 0, 3, -1, }, + { "PKR#", 19, 0, 0, -1, }, + { "PKR#", 19, 0, 2, -1, }, + { "PKR#", 19, 0, 2, -1, }, + { "PMC#", 20, 0, 2, -1, }, + { "PMC#", 20, 0, 6, -1, "SC+3 Section 12.1.1", }, + { "PMD#", 21, 0, 2, -1, }, + { "PR0", 0, 0, 0, -1, }, + { "PR%, % in 1 - 62", 22, 0, 2, -1, }, + { "PR%, % in 1 - 62", 22, 0, 2, -1, }, + { "PR%, % in 1 - 62", 22, 0, 0, -1, }, + { "PR63", 23, 0, 2, -1, }, + { "PR63", 23, 0, 2, -1, }, + { "PR63", 23, 0, 0, -1, }, + { "PSR.ac", 27, 0, 1, 3, }, + { "PSR.ac", 27, 0, 3, 3, }, + { "PSR.ac", 27, 0, 2, 3, }, + { "PSR.be", 27, 0, 1, 1, }, + { "PSR.be", 27, 0, 3, 1, }, + { "PSR.be", 27, 0, 2, 1, }, + { "PSR.bn", 27, 0, 2, 44, }, + { "PSR.cpl", 27, 0, 1, 32, }, + { "PSR.da", 27, 0, 3, 38, }, + { "PSR.db", 27, 0, 3, 24, }, + { "PSR.db", 27, 0, 2, 24, }, + { "PSR.db", 27, 0, 3, 24, }, + { "PSR.dd", 27, 0, 3, 39, }, + { "PSR.dfh", 27, 0, 3, 19, }, + { "PSR.dfh", 27, 0, 2, 19, }, + { "PSR.dfl", 27, 0, 3, 18, }, + { "PSR.dfl", 27, 0, 2, 18, }, + { "PSR.di", 27, 0, 3, 22, }, + { "PSR.di", 27, 0, 2, 22, }, + { "PSR.dt", 27, 0, 3, 17, }, + { "PSR.dt", 27, 0, 2, 17, }, + { "PSR.ed", 27, 0, 3, 43, }, + { "PSR.i", 27, 0, 2, 14, }, + { "PSR.i", 27, 0, 3, 14, }, + { "PSR.ia", 27, 0, 0, 14, }, + { "PSR.ic", 27, 0, 2, 13, }, + { "PSR.ic", 27, 0, 3, 13, }, + { "PSR.id", 27, 0, 0, 14, }, + { "PSR.is", 27, 0, 0, 14, }, + { "PSR.it", 27, 0, 3, 14, }, + { "PSR.lp", 27, 0, 2, 25, }, + { "PSR.lp", 27, 0, 3, 25, }, + { "PSR.lp", 27, 0, 3, 25, }, + { "PSR.mc", 27, 0, 0, 35, }, + { "PSR.mfh", 27, 0, 2, 5, }, + { "PSR.mfl", 27, 0, 2, 4, }, + { "PSR.pk", 27, 0, 3, 15, }, + { "PSR.pk", 27, 0, 2, 15, }, + { "PSR.pp", 27, 0, 2, 21, }, + { "PSR.ri", 27, 0, 0, 41, }, + { "PSR.rt", 27, 0, 2, 27, }, + { "PSR.rt", 27, 0, 3, 27, }, + { "PSR.rt", 27, 0, 3, 27, }, + { "PSR.si", 27, 0, 2, 23, }, + { "PSR.si", 27, 0, 3, 23, }, + { "PSR.sp", 27, 0, 2, 20, }, + { "PSR.sp", 27, 0, 3, 20, }, + { "PSR.ss", 27, 0, 3, 40, }, + { "PSR.tb", 27, 0, 3, 26, }, + { "PSR.tb", 27, 0, 2, 26, }, + { "PSR.up", 27, 0, 2, 2, }, + { "RR#", 24, 0, 3, -1, }, + { "RR#", 24, 0, 2, -1, }, + { "RSE", 28, 0, 2, -1, }, + { "ALAT", 0, 1, 0, -1, }, + { "AR[BSP]", 25, 1, 2, 17, }, + { "AR[BSPSTORE]", 25, 1, 2, 18, }, + { "AR[CCV]", 25, 1, 2, 32, }, + { "AR[EC]", 25, 1, 2, 66, }, + { "AR[FPSR].sf0.controls", 29, 1, 2, -1, }, + { "AR[FPSR].sf1.controls", 29, 1, 2, -1, }, + { "AR[FPSR].sf2.controls", 29, 1, 2, -1, }, + { "AR[FPSR].sf3.controls", 29, 1, 2, -1, }, + { "AR[FPSR].sf0.flags", 29, 1, 0, -1, }, + { "AR[FPSR].sf0.flags", 29, 1, 2, -1, }, + { "AR[FPSR].sf0.flags", 29, 1, 2, -1, }, + { "AR[FPSR].sf1.flags", 29, 1, 0, -1, }, + { "AR[FPSR].sf1.flags", 29, 1, 2, -1, }, + { "AR[FPSR].sf1.flags", 29, 1, 2, -1, }, + { "AR[FPSR].sf2.flags", 29, 1, 0, -1, }, + { "AR[FPSR].sf2.flags", 29, 1, 2, -1, }, + { "AR[FPSR].sf2.flags", 29, 1, 2, -1, }, + { "AR[FPSR].sf3.flags", 29, 1, 0, -1, }, + { "AR[FPSR].sf3.flags", 29, 1, 2, -1, }, + { "AR[FPSR].sf3.flags", 29, 1, 2, -1, }, + { "AR[FPSR].rv", 29, 1, 2, -1, }, + { "AR[FPSR].traps", 29, 1, 2, -1, }, + { "AR[ITC]", 25, 1, 2, 44, }, + { "AR[K%], % in 0 - 7", 1, 1, 2, -1, }, + { "AR[LC]", 25, 1, 2, 65, }, + { "AR[PFS]", 25, 1, 0, 64, }, + { "AR[PFS]", 25, 1, 2, 64, }, + { "AR[PFS]", 25, 1, 2, 64, }, + { "AR[RNAT]", 25, 1, 2, 19, }, + { "AR[RSC]", 25, 1, 2, 16, }, + { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, }, + { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, }, + { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, }, + { "BR%, % in 0 - 7", 5, 1, 0, -1, }, + { "CFM", 6, 1, 2, -1, }, + { "CPUID#", 7, 1, 0, -1, }, + { "CR[CMCV]", 26, 1, 2, 74, }, + { "CR[DCR]", 26, 1, 2, 0, }, + { "CR[EOI]", 26, 1, 6, 67, "SC Section 10.8.3.4", }, + { "CR[GPTA]", 26, 1, 2, 9, }, + { "CR[IFA]", 26, 1, 2, 20, }, + { "CR[IFS]", 26, 1, 2, 23, }, + { "CR[IHA]", 26, 1, 2, 25, }, + { "CR[IIM]", 26, 1, 2, 24, }, + { "CR[IIP]", 26, 1, 2, 19, }, + { "CR[IIPA]", 26, 1, 2, 22, }, + { "CR[IPSR]", 26, 1, 2, 16, }, + { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, }, + { "CR[ISR]", 26, 1, 2, 17, }, + { "CR[ITIR]", 26, 1, 2, 21, }, + { "CR[ITM]", 26, 1, 2, 1, }, + { "CR[ITV]", 26, 1, 2, 72, }, + { "CR[IVA]", 26, 1, 2, 2, }, + { "CR[IVR]", 26, 1, 6, 65, "SC", }, + { "CR[LID]", 26, 1, 6, 64, "SC", }, + { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, }, + { "CR[PMV]", 26, 1, 2, 73, }, + { "CR[PTA]", 26, 1, 2, 8, }, + { "CR[TPR]", 26, 1, 2, 66, }, + { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, }, + { "DBR#", 11, 1, 2, -1, }, + { "DTC", 0, 1, 0, -1, }, + { "DTC", 0, 1, 2, -1, }, + { "DTC", 0, 1, 2, -1, }, + { "DTC_LIMIT*", 0, 1, 2, -1, }, + { "DTR", 0, 1, 2, -1, }, + { "DTR", 0, 1, 2, -1, }, + { "DTR", 0, 1, 2, -1, }, + { "DTR", 0, 1, 0, -1, }, + { "FR%, % in 0 - 1", 12, 1, 0, -1, }, + { "FR%, % in 2 - 127", 13, 1, 2, -1, }, + { "GR0", 14, 1, 0, -1, }, + { "GR%, % in 1 - 127", 15, 1, 2, -1, }, + { "IBR#", 16, 1, 2, -1, }, + { "InService*", 17, 1, 6, -1, "SC", }, + { "IP", 0, 1, 0, -1, }, + { "ITC", 0, 1, 0, -1, }, + { "ITC", 0, 1, 2, -1, }, + { "ITC", 0, 1, 2, -1, }, + { "ITR", 0, 1, 2, -1, }, + { "ITR", 0, 1, 2, -1, }, + { "ITR", 0, 1, 0, -1, }, + { "memory", 0, 1, 0, -1, }, + { "MSR#", 18, 1, 6, -1, "SC", }, + { "PKR#", 19, 1, 0, -1, }, + { "PKR#", 19, 1, 0, -1, }, + { "PKR#", 19, 1, 2, -1, }, + { "PMC#", 20, 1, 2, -1, }, + { "PMD#", 21, 1, 2, -1, }, + { "PR0", 0, 1, 0, -1, }, + { "PR%, % in 1 - 62", 22, 1, 0, -1, }, + { "PR%, % in 1 - 62", 22, 1, 0, -1, }, + { "PR%, % in 1 - 62", 22, 1, 2, -1, }, + { "PR%, % in 1 - 62", 22, 1, 2, -1, }, + { "PR63", 23, 1, 0, -1, }, + { "PR63", 23, 1, 0, -1, }, + { "PR63", 23, 1, 2, -1, }, + { "PR63", 23, 1, 2, -1, }, + { "PSR.ac", 27, 1, 2, 3, }, + { "PSR.be", 27, 1, 2, 1, }, + { "PSR.bn", 27, 1, 2, 44, }, + { "PSR.cpl", 27, 1, 2, 32, }, + { "PSR.da", 27, 1, 2, 38, }, + { "PSR.db", 27, 1, 2, 24, }, + { "PSR.dd", 27, 1, 2, 39, }, + { "PSR.dfh", 27, 1, 2, 19, }, + { "PSR.dfl", 27, 1, 2, 18, }, + { "PSR.di", 27, 1, 2, 22, }, + { "PSR.dt", 27, 1, 2, 17, }, + { "PSR.ed", 27, 1, 2, 43, }, + { "PSR.i", 27, 1, 2, 14, }, + { "PSR.ia", 27, 1, 2, 14, }, + { "PSR.ic", 27, 1, 2, 13, }, + { "PSR.id", 27, 1, 2, 14, }, + { "PSR.is", 27, 1, 2, 14, }, + { "PSR.it", 27, 1, 2, 14, }, + { "PSR.lp", 27, 1, 2, 25, }, + { "PSR.mc", 27, 1, 2, 35, }, + { "PSR.mfh", 27, 1, 0, 5, }, + { "PSR.mfh", 27, 1, 2, 5, }, + { "PSR.mfh", 27, 1, 2, 5, }, + { "PSR.mfl", 27, 1, 0, 4, }, + { "PSR.mfl", 27, 1, 2, 4, }, + { "PSR.mfl", 27, 1, 2, 4, }, + { "PSR.pk", 27, 1, 2, 15, }, + { "PSR.pp", 27, 1, 2, 21, }, + { "PSR.ri", 27, 1, 2, 41, }, + { "PSR.rt", 27, 1, 2, 27, }, + { "PSR.si", 27, 1, 2, 23, }, + { "PSR.sp", 27, 1, 2, 20, }, + { "PSR.ss", 27, 1, 2, 40, }, + { "PSR.tb", 27, 1, 2, 26, }, + { "PSR.up", 27, 1, 2, 2, }, + { "RR#", 24, 1, 2, -1, }, + { "RSE", 28, 1, 2, -1, }, + { "PR63", 23, 2, 2, -1, }, +}; + +static const short dep0[] = { + 88, 249, 2131, 2294, +}; + +static const short dep1[] = { + 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 20602, + +}; + +static const short dep2[] = { + 2131, 2294, +}; + +static const short dep3[] = { + 32, 33, 2129, 2130, 2131, 2294, 4127, 20602, +}; + +static const short dep4[] = { + 32, 33, 81, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, + 20602, +}; + +static const short dep5[] = { + 88, 249, 2157, 2158, 2160, 2161, 2163, 2311, 2314, 2315, 2318, 2319, +}; + +static const short dep6[] = { + 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2311, 2314, 2315, + 2318, 2319, 4127, 20602, +}; + +static const short dep7[] = { + 88, 249, 22637, 22638, 22640, 22641, 22643, 22791, 22794, 22795, 22798, 22799, + +}; + +static const short dep8[] = { + 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, 22791, + 22794, 22795, 22798, 22799, +}; + +static const short dep9[] = { + 88, 249, 2312, 2314, 2316, 2318, +}; + +static const short dep10[] = { + 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2312, 2315, 2316, + 2319, 4127, 20602, +}; + +static const short dep11[] = { + 88, 249, 2313, 2315, 2317, 2319, +}; + +static const short dep12[] = { + 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2313, 2314, 2317, + 2318, 4127, 20602, +}; + +static const short dep13[] = { + 88, 249, 2312, 2313, 2314, 2315, 2316, 2317, 2318, 2319, +}; + +static const short dep14[] = { + 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2312, 2313, 2314, + 2315, 2316, 2317, 2318, 2319, 4127, 20602, +}; + +static const short dep15[] = { + 88, 249, 2357, +}; + +static const short dep16[] = { + 32, 33, 88, 145, 163, 164, 249, 2074, 2075, 2157, 2159, 2160, 2162, 2163, + 4127, +}; + +static const short dep17[] = { + 88, 144, 249, 288, 2357, 28841, 28980, +}; + +static const short dep18[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, + 23, 24, 25, 32, 33, 88, 133, 145, 163, 164, 249, 288, 2074, 2075, 2157, 2159, + 2160, 2162, 2163, 4127, 28841, 28980, +}; + +static const short dep19[] = { + 1, 4, 32, 88, 123, 171, 174, 208, 249, 275, 2357, 28841, 28980, +}; + +static const short dep20[] = { + 1, 18, 20, 30, 32, 33, 88, 145, 147, 148, 163, 164, 171, 174, 208, 249, 275, + 2074, 2075, 2157, 2159, 2160, 2162, 2163, 4127, 28841, 28980, +}; + +static const short dep21[] = { + 1, 32, 43, 88, 171, 208, 215, 249, 28841, 28980, +}; + +static const short dep22[] = { + 1, 30, 32, 33, 88, 142, 163, 171, 208, 215, 249, 4127, 28841, 28980, +}; + +static const short dep23[] = { + 32, 88, 208, 249, +}; + +static const short dep24[] = { + 88, 163, 208, 249, +}; + +static const short dep25[] = { + 1, 32, 88, 117, 118, 120, 121, 122, 123, 124, 127, 128, 129, 130, 131, 132, + 133, 134, 135, 136, 137, 139, 140, 141, 142, 143, 144, 145, 148, 149, 150, + 151, 152, 153, 154, 155, 158, 159, 160, 161, 162, 163, 164, 165, 166, 171, + 208, 249, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, + 285, 286, 287, 288, 289, 290, 291, 293, 294, 296, 297, 298, 299, 300, 301, + 302, 303, 304, 305, 306, 28841, 28980, +}; + +static const short dep26[] = { + 1, 30, 32, 33, 42, 43, 47, 50, 64, 88, 123, 163, 171, 208, 249, 272, 273, + 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, + 289, 290, 291, 293, 294, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, + 306, 4127, 28841, 28980, +}; + +static const short dep27[] = { + 88, 122, 249, 274, +}; + +static const short dep28[] = { + 88, 123, 163, 249, 274, +}; + +static const short dep29[] = { + 88, 123, 249, 275, +}; + +static const short dep30[] = { + 18, 19, 88, 89, 92, 96, 99, 123, 145, 163, 249, 275, +}; + +static const short dep31[] = { + 32, 33, 88, 163, 249, 2157, 2159, 2160, 2162, 2163, 4127, +}; + +static const short dep32[] = { + 1, 18, 32, 88, 171, 196, 197, 208, 249, 2074, 2252, 2255, 2357, 28841, 28980, + +}; + +static const short dep33[] = { + 1, 4, 30, 32, 33, 88, 123, 145, 163, 164, 171, 196, 198, 208, 249, 2074, 2075, + 2157, 2159, 2160, 2162, 2163, 2253, 2255, 4127, 28841, 28980, +}; + +static const short dep34[] = { + 88, 249, +}; + +static const short dep35[] = { + 88, 163, 249, 2074, 2076, +}; + +static const short dep36[] = { + 32, 33, 88, 145, 163, 164, 249, 2157, 2159, 2160, 2162, 2163, 4127, +}; + +static const short dep37[] = { + 4, 29, 30, 31, 88, 113, 114, 174, 208, 249, 270, 271, 2357, +}; + +static const short dep38[] = { + 4, 29, 32, 33, 88, 145, 163, 164, 174, 208, 249, 270, 271, 309, 2157, 2159, + 2160, 2162, 2163, 4127, +}; + +static const short dep39[] = { + 17, 88, 195, 249, 2357, +}; + +static const short dep40[] = { + 17, 32, 33, 88, 145, 163, 164, 195, 249, 2157, 2159, 2160, 2162, 2163, 4127, + +}; + +static const short dep41[] = { + 4, 17, 29, 30, 31, 88, 113, 114, 174, 195, 208, 249, 270, 271, 2357, +}; + +static const short dep42[] = { + 4, 17, 29, 32, 33, 88, 145, 163, 164, 174, 195, 208, 249, 270, 271, 309, 2157, + 2159, 2160, 2162, 2163, 4127, +}; + +static const short dep43[] = { + 1, 4, 30, 32, 33, 88, 123, 145, 163, 164, 171, 196, 198, 208, 249, 2157, 2159, + 2160, 2162, 2163, 2253, 2255, 4127, 28841, 28980, +}; + +static const short dep44[] = { + 88, 163, 249, +}; + +static const short dep45[] = { + 9, 88, 179, 180, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, + 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799, +}; + +static const short dep46[] = { + 5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 22791, 22794, 22795, + 22798, 22799, +}; + +static const short dep47[] = { + 9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 2127, 2292, + 18582, 18583, 18724, 18725, 18727, 18728, 22637, 22638, 22639, 22641, 22642, + 22791, 22794, 22795, 22798, 22799, +}; + +static const short dep48[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190, + 249, 2126, 2127, 2128, 2157, 2158, 2161, 2292, 4127, 16513, 16515, 18724, + 18726, 18727, 18729, 22791, 22794, 22795, 22798, 22799, +}; + +static const short dep49[] = { + 10, 88, 182, 183, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, + 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799, +}; + +static const short dep50[] = { + 6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 22791, 22794, 22795, + 22798, 22799, +}; + +static const short dep51[] = { + 11, 88, 185, 186, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, + 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799, +}; + +static const short dep52[] = { + 7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 22791, 22794, 22795, + 22798, 22799, +}; + +static const short dep53[] = { + 12, 88, 188, 189, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, + 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799, +}; + +static const short dep54[] = { + 8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 22791, 22794, 22795, + 22798, 22799, +}; + +static const short dep55[] = { + 9, 88, 179, 180, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, + +}; + +static const short dep56[] = { + 5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, +}; + +static const short dep57[] = { + 9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 2127, 2292, + 18582, 18583, 18724, 18725, 18727, 18728, +}; + +static const short dep58[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190, + 249, 2126, 2127, 2128, 2157, 2158, 2161, 2292, 4127, 16513, 16515, 18724, + 18726, 18727, 18729, +}; + +static const short dep59[] = { + 10, 88, 182, 183, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, + +}; + +static const short dep60[] = { + 6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, +}; + +static const short dep61[] = { + 11, 88, 185, 186, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, + +}; + +static const short dep62[] = { + 7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, +}; + +static const short dep63[] = { + 12, 88, 188, 189, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, + +}; + +static const short dep64[] = { + 8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, +}; + +static const short dep65[] = { + 88, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, +}; + +static const short dep66[] = { + 32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 2292, 4127, 16513, + 16515, 18724, 18726, 18727, 18729, +}; + +static const short dep67[] = { + 5, 88, 175, 249, +}; + +static const short dep68[] = { + 5, 32, 33, 88, 163, 175, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep69[] = { + 5, 32, 33, 88, 163, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep70[] = { + 6, 88, 176, 249, +}; + +static const short dep71[] = { + 5, 32, 33, 88, 163, 176, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep72[] = { + 7, 88, 177, 249, +}; + +static const short dep73[] = { + 5, 32, 33, 88, 163, 177, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep74[] = { + 8, 88, 178, 249, +}; + +static const short dep75[] = { + 5, 32, 33, 88, 163, 178, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep76[] = { + 9, 88, 180, 181, 249, +}; + +static const short dep77[] = { + 32, 33, 88, 163, 180, 181, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep78[] = { + 32, 33, 88, 163, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep79[] = { + 10, 88, 183, 184, 249, +}; + +static const short dep80[] = { + 32, 33, 88, 163, 183, 184, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep81[] = { + 11, 88, 186, 187, 249, +}; + +static const short dep82[] = { + 32, 33, 88, 163, 186, 187, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep83[] = { + 12, 88, 189, 190, 249, +}; + +static const short dep84[] = { + 32, 33, 88, 163, 189, 190, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep85[] = { + 9, 13, 14, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep86[] = { + 9, 10, 13, 14, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep87[] = { + 9, 11, 13, 14, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep88[] = { + 9, 12, 13, 14, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep89[] = { + 9, 88, 179, 180, 249, +}; + +static const short dep90[] = { + 5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep91[] = { + 9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, +}; + +static const short dep92[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190, + 249, 2157, 2158, 2161, 4127, +}; + +static const short dep93[] = { + 10, 88, 182, 183, 249, +}; + +static const short dep94[] = { + 6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep95[] = { + 11, 88, 185, 186, 249, +}; + +static const short dep96[] = { + 7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep97[] = { + 12, 88, 188, 189, 249, +}; + +static const short dep98[] = { + 8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep99[] = { + 9, 88, 179, 180, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318, + 2319, +}; + +static const short dep100[] = { + 5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 2311, 2314, 2315, 2318, 2319, 4127, 16513, 16515, +}; + +static const short dep101[] = { + 9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 2157, 2158, + 2159, 2161, 2162, 2311, 2314, 2315, 2318, 2319, +}; + +static const short dep102[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190, + 249, 2126, 2127, 2128, 2157, 2158, 2161, 2311, 2314, 2315, 2318, 2319, 4127, + 16513, 16515, +}; + +static const short dep103[] = { + 10, 88, 182, 183, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318, + 2319, +}; + +static const short dep104[] = { + 6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 2311, 2314, 2315, 2318, 2319, 4127, 16513, 16515, +}; + +static const short dep105[] = { + 11, 88, 185, 186, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318, + 2319, +}; + +static const short dep106[] = { + 7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 2311, 2314, 2315, 2318, 2319, 4127, 16513, 16515, +}; + +static const short dep107[] = { + 12, 88, 188, 189, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318, + 2319, +}; + +static const short dep108[] = { + 8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 2311, 2314, 2315, 2318, 2319, 4127, 16513, 16515, +}; + +static const short dep109[] = { + 9, 88, 179, 180, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, + 22798, 22799, +}; + +static const short dep110[] = { + 5, 13, 14, 32, 33, 88, 163, 179, 181, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 4127, 16513, 16515, 22791, 22794, 22795, 22798, 22799, +}; + +static const short dep111[] = { + 9, 10, 11, 12, 88, 179, 180, 182, 183, 185, 186, 188, 189, 249, 22637, 22638, + 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799, +}; + +static const short dep112[] = { + 5, 6, 7, 8, 13, 14, 32, 33, 88, 163, 179, 181, 182, 184, 185, 187, 188, 190, + 249, 2126, 2127, 2128, 2157, 2158, 2161, 4127, 16513, 16515, 22791, 22794, + 22795, 22798, 22799, +}; + +static const short dep113[] = { + 10, 88, 182, 183, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, + 22798, 22799, +}; + +static const short dep114[] = { + 6, 13, 14, 32, 33, 88, 163, 182, 184, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 4127, 16513, 16515, 22791, 22794, 22795, 22798, 22799, +}; + +static const short dep115[] = { + 11, 88, 185, 186, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, + 22798, 22799, +}; + +static const short dep116[] = { + 7, 13, 14, 32, 33, 88, 163, 185, 187, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 4127, 16513, 16515, 22791, 22794, 22795, 22798, 22799, +}; + +static const short dep117[] = { + 12, 88, 188, 189, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, + 22798, 22799, +}; + +static const short dep118[] = { + 8, 13, 14, 32, 33, 88, 163, 188, 190, 249, 2126, 2127, 2128, 2157, 2158, 2161, + 4127, 16513, 16515, 22791, 22794, 22795, 22798, 22799, +}; + +static const short dep119[] = { + 88, 249, 2157, 2158, 2159, 2161, 2162, 2311, 2314, 2315, 2318, 2319, +}; + +static const short dep120[] = { + 32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 2311, 2314, 2315, + 2318, 2319, 4127, 16513, 16515, +}; + +static const short dep121[] = { + 88, 249, 22637, 22638, 22639, 22641, 22642, 22791, 22794, 22795, 22798, 22799, + +}; + +static const short dep122[] = { + 32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 4127, 16513, 16515, + 22791, 22794, 22795, 22798, 22799, +}; + +static const short dep123[] = { + 13, 14, 32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 2292, 4127, + 16513, 16515, 18724, 18726, 18727, 18729, +}; + +static const short dep124[] = { + 32, 33, 88, 145, 163, 164, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, + 20602, +}; + +static const short dep125[] = { + 88, 249, 2075, 2076, 2253, 2254, +}; + +static const short dep126[] = { + 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2252, 2254, 4127, + 20602, +}; + +static const short dep127[] = { + 32, 33, 88, 163, 249, 2074, 2076, 2157, 2158, 2161, 2294, 4127, 20602, +}; + +static const short dep128[] = { + 88, 249, 14446, 14448, 14449, 14451, 14602, 14603, 14606, 14607, +}; + +static const short dep129[] = { + 32, 33, 88, 163, 249, 2129, 2130, 2131, 4127, 14602, 14603, 14606, 14607, + 20602, 24685, 24686, 24689, +}; + +static const short dep130[] = { + 88, 110, 112, 113, 115, 249, 14602, 14603, 14606, 14607, +}; + +static const short dep131[] = { + 32, 33, 88, 163, 249, 4127, 14602, 14603, 14606, 14607, 24685, 24686, 24689, + +}; + +static const short dep132[] = { + 32, 33, 88, 163, 249, 2157, 2158, 2161, 2294, 4127, 20602, +}; + +static const short dep133[] = { + 32, 33, 88, 110, 113, 163, 249, 2294, 4127, 20602, 24685, +}; + +static const short dep134[] = { + 4, 17, 19, 20, 88, 174, 195, 198, 249, 2073, 2251, +}; + +static const short dep135[] = { + 32, 33, 88, 163, 174, 195, 197, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2251, + 4127, 20602, +}; + +static const short dep136[] = { + 4, 17, 18, 19, 32, 33, 88, 163, 249, 2073, 2157, 2158, 2161, 2294, 4127, 20602, + +}; + +static const short dep137[] = { + 0, 32, 33, 88, 145, 163, 164, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep138[] = { + 0, 88, 170, 249, +}; + +static const short dep139[] = { + 0, 32, 33, 88, 145, 163, 164, 170, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep140[] = { + 32, 33, 88, 163, 170, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep141[] = { + 2, 21, 88, 172, 199, 249, 28841, 28980, +}; + +static const short dep142[] = { + 1, 2, 21, 22, 88, 157, 158, 163, 172, 199, 249, 28841, 28980, +}; + +static const short dep143[] = { + 1, 21, 22, 30, 32, 33, 88, 157, 158, 163, 172, 199, 249, 4127, 28841, 28980, + +}; + +static const short dep144[] = { + 0, 32, 33, 88, 163, 170, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep145[] = { + 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 22, 23, 88, 171, 172, + 173, 175, 176, 177, 178, 180, 181, 183, 184, 186, 187, 189, 190, 191, 192, + 193, 199, 200, 201, 249, 2064, 2073, 2242, 2251, 28841, 28980, +}; + +static const short dep146[] = { + 22, 32, 33, 88, 123, 163, 171, 172, 173, 175, 176, 177, 178, 180, 181, 183, + 184, 186, 187, 189, 190, 191, 192, 193, 199, 200, 201, 249, 2129, 2130, 2131, + 2157, 2158, 2161, 2242, 2251, 4127, 20602, 28841, 28980, +}; + +static const short dep147[] = { + 88, 249, 14452, 14454, 14455, 14457, 14486, 14487, 14502, 14608, 14609, 14629, + 14630, 14632, 14633, 14642, +}; + +static const short dep148[] = { + 32, 33, 88, 162, 163, 249, 2157, 2158, 2161, 4127, 14608, 14609, 14629, 14630, + 14632, 14633, 14642, +}; + +static const short dep149[] = { + 14452, 14454, 14455, 14457, 14486, 14487, 14502, 14608, 14609, 14629, 14630, + 14632, 14633, 14642, +}; + +static const short dep150[] = { + 162, 14608, 14609, 14629, 14630, 14632, 14633, 14642, +}; + +static const short dep151[] = { + 88, 249, 14453, 14454, 14456, 14457, 14465, 14466, 14467, 14468, 14469, 14470, + 14471, 14472, 14474, 14477, 14478, 14486, 14487, 14488, 14489, 14490, 14495, + 14496, 14497, 14498, 14502, 14608, 14609, 14615, 14616, 14617, 14618, 14620, + 14622, 14629, 14630, 14632, 14633, 14634, 14635, 14638, 14639, 14642, +}; + +static const short dep152[] = { + 32, 33, 64, 88, 123, 163, 249, 2157, 2158, 2161, 4127, 14608, 14609, 14615, + 14616, 14617, 14618, 14620, 14622, 14629, 14630, 14632, 14633, 14634, 14635, + 14638, 14639, 14642, +}; + +static const short dep153[] = { + 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 22, 23, 32, 33, 88, 123, + 160, 163, 249, 2064, 2073, 2157, 2158, 2161, 2294, 4127, 20602, 28841, +}; + +static const short dep154[] = { + 35, 36, 37, 38, 39, 40, 41, 42, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55, + 56, 57, 59, 61, 62, 63, 64, 85, 87, 88, 210, 211, 212, 213, 214, 215, 216, + 217, 218, 219, 220, 222, 223, 224, 225, 226, 228, 230, 231, 232, 248, 249, + 2108, 2277, +}; + +static const short dep155[] = { + 32, 33, 87, 88, 123, 142, 163, 210, 211, 212, 213, 214, 215, 216, 217, 218, + 219, 220, 222, 223, 224, 225, 226, 228, 230, 231, 232, 248, 249, 2129, 2130, + 2131, 2157, 2158, 2161, 2277, 4127, 20602, +}; + +static const short dep156[] = { + 51, 86, 88, 221, 248, 249, 2131, 2294, +}; + +static const short dep157[] = { + 32, 33, 35, 36, 38, 40, 41, 43, 44, 45, 46, 48, 49, 52, 53, 55, 56, 57, 58, + 59, 61, 62, 63, 85, 86, 88, 123, 142, 163, 221, 248, 249, 2099, 2108, 2157, + 2158, 2161, 2294, 4127, 20602, +}; + +static const short dep158[] = { + 2, 21, 33, 88, 172, 199, 208, 249, 2131, 2294, 28841, 28980, +}; + +static const short dep159[] = { + 2, 18, 19, 21, 22, 30, 32, 33, 88, 157, 158, 163, 172, 199, 208, 249, 2294, + 4127, 20602, 28841, 28980, +}; + +static const short dep160[] = { + 88, 117, 118, 120, 121, 125, 126, 129, 130, 131, 132, 133, 134, 135, 136, + 138, 141, 142, 146, 147, 150, 151, 152, 153, 154, 156, 157, 159, 160, 161, + 162, 164, 165, 166, 249, 272, 273, 277, 279, 280, 281, 282, 284, 286, 290, + 293, 294, 296, 297, 298, 299, 301, 302, 303, 305, 306, +}; + +static const short dep161[] = { + 32, 33, 64, 88, 123, 163, 249, 272, 273, 277, 279, 280, 281, 282, 284, 286, + 290, 293, 294, 296, 297, 298, 299, 301, 302, 303, 305, 306, 2129, 2130, 2131, + 2157, 2158, 2161, 4127, 20602, +}; + +static const short dep162[] = { + 88, 116, 118, 119, 121, 150, 151, 166, 249, 272, 273, 293, 294, 296, 297, + 306, +}; + +static const short dep163[] = { + 32, 33, 88, 162, 163, 249, 272, 273, 293, 294, 296, 297, 306, 2129, 2130, + 2131, 2157, 2158, 2161, 4127, 20602, +}; + +static const short dep164[] = { + 32, 33, 88, 118, 121, 123, 126, 127, 130, 132, 134, 136, 138, 139, 141, 145, + 146, 148, 149, 150, 151, 153, 154, 156, 158, 159, 161, 163, 165, 166, 249, + 2157, 2158, 2161, 2294, 4127, 20602, +}; + +static const short dep165[] = { + 32, 33, 88, 118, 121, 150, 151, 163, 166, 249, 2157, 2158, 2161, 2294, 4127, + 20602, +}; + +static const short dep166[] = { + 32, 33, 67, 68, 73, 75, 88, 102, 123, 152, 163, 167, 249, 2129, 2130, 2131, + 2157, 2158, 2161, 2294, 4127, 20602, +}; + +static const short dep167[] = { + 32, 33, 67, 68, 73, 75, 88, 102, 123, 124, 125, 127, 128, 152, 163, 167, 249, + 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, +}; + +static const short dep168[] = { + 68, 69, 88, 92, 93, 236, 237, 249, 251, 252, +}; + +static const short dep169[] = { + 32, 33, 39, 54, 69, 71, 77, 88, 90, 93, 123, 142, 163, 167, 236, 237, 249, + 251, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, +}; + +static const short dep170[] = { + 32, 33, 39, 54, 69, 71, 88, 90, 93, 95, 97, 123, 142, 163, 167, 236, 237, + 249, 251, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, +}; + +static const short dep171[] = { + 88, 249, 12455, 12456, 12595, +}; + +static const short dep172[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 12595, + 20602, +}; + +static const short dep173[] = { + 88, 249, 6210, 6211, 6378, +}; + +static const short dep174[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6378, + 20602, +}; + +static const short dep175[] = { + 88, 249, 6228, 6391, +}; + +static const short dep176[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6391, + 20602, +}; + +static const short dep177[] = { + 88, 249, 6246, 6247, 6248, 6249, 6402, 6404, 8451, +}; + +static const short dep178[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6249, + 6403, 6404, 8295, 8450, 20602, +}; + +static const short dep179[] = { + 88, 249, 6250, 6251, 6405, +}; + +static const short dep180[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6405, + 20602, +}; + +static const short dep181[] = { + 88, 249, 6252, 6406, +}; + +static const short dep182[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 6406, + 20602, +}; + +static const short dep183[] = { + 88, 249, 10341, 10497, +}; + +static const short dep184[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 10497, + 20602, +}; + +static const short dep185[] = { + 68, 69, 73, 74, 88, 92, 93, 236, 237, 239, 240, 249, 251, 252, +}; + +static const short dep186[] = { + 32, 33, 39, 69, 71, 74, 77, 88, 90, 93, 123, 142, 163, 167, 236, 237, 239, + 241, 249, 251, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, +}; + +static const short dep187[] = { + 68, 69, 88, 92, 93, 95, 96, 236, 237, 249, 251, 252, 253, 254, +}; + +static const short dep188[] = { + 32, 33, 39, 54, 69, 71, 88, 90, 93, 95, 97, 123, 142, 163, 167, 236, 237, + 249, 251, 252, 253, 254, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, + +}; + +static const short dep189[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, + 12456, 20602, +}; + +static const short dep190[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, + 6210, 20602, +}; + +static const short dep191[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, + 6228, 20602, +}; + +static const short dep192[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, + 6248, 8294, 20602, +}; + +static const short dep193[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, + 6250, 20602, +}; + +static const short dep194[] = { + 32, 33, 88, 123, 162, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, + 4127, 6251, 6252, 20602, +}; + +static const short dep195[] = { + 32, 33, 88, 123, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, + 10341, 20602, +}; + +static const short dep196[] = { + 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, 6178, + 20602, +}; + +static const short dep197[] = { + 68, 70, 71, 88, 89, 90, 91, 235, 236, 249, 250, 251, +}; + +static const short dep198[] = { + 32, 33, 69, 70, 74, 76, 88, 91, 93, 95, 98, 123, 163, 167, 235, 237, 249, + 250, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, +}; + +static const short dep199[] = { + 68, 70, 71, 72, 88, 89, 90, 91, 94, 235, 236, 238, 249, 250, 251, +}; + +static const short dep200[] = { + 32, 33, 69, 70, 72, 74, 76, 88, 91, 93, 94, 95, 98, 123, 163, 167, 235, 237, + 238, 249, 250, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, +}; + +static const short dep201[] = { + 68, 70, 71, 75, 76, 77, 88, 89, 90, 91, 235, 236, 241, 242, 249, 250, 251, + +}; + +static const short dep202[] = { + 32, 33, 69, 70, 74, 76, 88, 91, 93, 123, 163, 167, 235, 237, 240, 242, 249, + 250, 252, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, +}; + +static const short dep203[] = { + 68, 70, 71, 88, 89, 90, 91, 97, 98, 99, 235, 236, 249, 250, 251, 254, 255, + +}; + +static const short dep204[] = { + 32, 33, 69, 70, 88, 91, 93, 95, 98, 123, 163, 167, 235, 237, 249, 250, 252, + 253, 255, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, +}; + +static const short dep205[] = { + 32, 33, 38, 62, 88, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, + 4127, 20602, +}; + +static const short dep206[] = { + 32, 33, 88, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, + 20602, +}; + +static const short dep207[] = { + 32, 33, 68, 73, 75, 88, 123, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, + 2161, 2294, 4127, 20602, +}; + +static const short dep208[] = { + 32, 33, 88, 145, 163, 164, 249, 2126, 2127, 2128, 2129, 2130, 2131, 2157, + 2158, 2161, 4127, 16513, 16515, 20602, +}; + +static const short dep209[] = { + 32, 33, 68, 73, 75, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, + 20602, +}; + +static const short dep210[] = { + 32, 33, 69, 70, 88, 91, 123, 163, 235, 237, 249, 250, 252, 2129, 2130, 2131, + 2157, 2158, 2161, 4127, 20602, +}; + +static const short dep211[] = { + 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, 127, + 128, 135, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, 4127, + 20602, +}; + +static const short dep212[] = { + 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, + 127, 128, 135, 137, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, + 2294, 4127, 20602, +}; + +static const short dep213[] = { + 0, 88, 170, 249, 2131, 2294, +}; + +static const short dep214[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, + 127, 128, 135, 152, 163, 167, 170, 249, 2129, 2130, 2131, 2157, 2158, 2161, + 2294, 4127, 20602, +}; + +static const short dep215[] = { + 0, 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, + 125, 127, 128, 135, 137, 152, 163, 167, 170, 249, 2129, 2130, 2131, 2157, + 2158, 2161, 2294, 4127, 20602, +}; + +static const short dep216[] = { + 23, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, + 127, 128, 135, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, + 4127, 20602, +}; + +static const short dep217[] = { + 0, 88, 170, 249, 2294, 26706, +}; + +static const short dep218[] = { + 0, 88, 100, 170, 249, 256, +}; + +static const short dep219[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 102, 116, 117, 119, 120, 123, 124, 125, 127, + 128, 135, 152, 163, 167, 170, 249, 256, 2129, 2130, 2131, 2157, 2158, 2161, + 4127, 20602, +}; + +static const short dep220[] = { + 0, 23, 88, 100, 170, 201, 249, 256, +}; + +static const short dep221[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 102, 116, 117, 119, 120, 123, 124, 125, 127, + 128, 135, 152, 163, 167, 170, 201, 249, 256, 2129, 2130, 2131, 2157, 2158, + 2161, 4127, 20602, +}; + +static const short dep222[] = { + 0, 88, 100, 170, 249, 256, 2131, 2294, +}; + +static const short dep223[] = { + 0, 3, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, + 125, 127, 128, 135, 152, 163, 167, 170, 249, 256, 2129, 2130, 2131, 2157, + 2158, 2161, 2294, 4127, 20602, +}; + +static const short dep224[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, + 127, 128, 135, 152, 163, 167, 170, 249, 256, 2129, 2130, 2131, 2157, 2158, + 2161, 2294, 4127, 20602, +}; + +static const short dep225[] = { + 32, 33, 88, 163, 249, 2126, 2127, 2128, 2157, 2158, 2161, 2294, 4127, 16513, + 16515, 20602, +}; + +static const short dep226[] = { + 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, 127, + 128, 135, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2292, 4127, + 16513, 16515, 18724, 18726, 18727, 18729, 20602, +}; + +static const short dep227[] = { + 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, + 127, 128, 135, 137, 152, 163, 167, 249, 2129, 2130, 2131, 2157, 2158, 2161, + 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 20602, +}; + +static const short dep228[] = { + 0, 88, 170, 249, 2127, 2292, 18582, 18583, 18724, 18725, 18727, 18728, +}; + +static const short dep229[] = { + 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, 125, + 127, 128, 135, 152, 163, 167, 170, 249, 2129, 2130, 2131, 2157, 2158, 2161, + 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 20602, +}; + +static const short dep230[] = { + 0, 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 116, 117, 119, 120, 123, 124, + 125, 127, 128, 135, 137, 152, 163, 167, 170, 249, 2129, 2130, 2131, 2157, + 2158, 2161, 2292, 4127, 16513, 16515, 18724, 18726, 18727, 18729, 20602, +}; + +static const short dep231[] = { + 0, 88, 170, 249, 2128, 2292, 18582, 18583, 18724, 18725, 18727, 18728, +}; + +static const short dep232[] = { + 32, 33, 67, 88, 123, 137, 163, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep233[] = { + 32, 33, 67, 88, 123, 124, 128, 137, 163, 249, 2157, 2158, 2161, 4127, +}; + +static const short dep234[] = { + 32, 33, 67, 88, 123, 137, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 2294, + 4127, 20602, +}; + +static const short dep235[] = { + 32, 33, 67, 88, 123, 124, 128, 137, 163, 249, 2129, 2130, 2131, 2157, 2158, + 2161, 2294, 4127, 20602, +}; + +static const short dep236[] = { + 32, 33, 88, 163, 249, 2129, 2130, 2131, 2157, 2158, 2161, 4127, 20602, +}; + +static const short dep237[] = { + 32, 33, 88, 163, 249, 2157, 2158, 2159, 2160, 2161, 2162, 2163, 4127, +}; + +static const short dep238[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 19, 20, 21, 22, 23, + 88, 171, 172, 173, 174, 175, 176, 177, 178, 180, 181, 183, 184, 186, 187, + 189, 190, 191, 192, 193, 195, 198, 199, 200, 201, 249, 2064, 2073, 2131, 2242, + 2251, 2294, 28841, 28980, +}; + +static const short dep239[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, + 32, 33, 88, 123, 160, 163, 171, 172, 173, 174, 175, 176, 177, 178, 180, 181, + 183, 184, 186, 187, 189, 190, 191, 192, 193, 195, 197, 199, 200, 201, 249, + 2064, 2073, 2129, 2130, 2131, 2157, 2158, 2161, 2242, 2251, 2294, 4127, 20602, + 28841, 28980, +}; + +#define NELS(X) (sizeof(X)/sizeof(X[0])) +static const struct ia64_opcode_dependency +op_dependencies[] = { + { NELS(dep1), dep1, NELS(dep0), dep0, }, + { NELS(dep3), dep3, NELS(dep2), dep2, }, + { NELS(dep4), dep4, NELS(dep0), dep0, }, + { NELS(dep6), dep6, NELS(dep5), dep5, }, + { NELS(dep8), dep8, NELS(dep7), dep7, }, + { NELS(dep10), dep10, NELS(dep9), dep9, }, + { NELS(dep12), dep12, NELS(dep11), dep11, }, + { NELS(dep14), dep14, NELS(dep13), dep13, }, + { NELS(dep16), dep16, NELS(dep15), dep15, }, + { NELS(dep18), dep18, NELS(dep17), dep17, }, + { NELS(dep20), dep20, NELS(dep19), dep19, }, + { NELS(dep22), dep22, NELS(dep21), dep21, }, + { NELS(dep24), dep24, NELS(dep23), dep23, }, + { NELS(dep26), dep26, NELS(dep25), dep25, }, + { NELS(dep28), dep28, NELS(dep27), dep27, }, + { NELS(dep30), dep30, NELS(dep29), dep29, }, + { NELS(dep31), dep31, NELS(dep15), dep15, }, + { NELS(dep33), dep33, NELS(dep32), dep32, }, + { NELS(dep35), dep35, NELS(dep34), dep34, }, + { NELS(dep36), dep36, NELS(dep15), dep15, }, + { NELS(dep38), dep38, NELS(dep37), dep37, }, + { NELS(dep40), dep40, NELS(dep39), dep39, }, + { NELS(dep42), dep42, NELS(dep41), dep41, }, + { NELS(dep43), dep43, NELS(dep32), dep32, }, + { NELS(dep44), dep44, NELS(dep34), dep34, }, + { NELS(dep46), dep46, NELS(dep45), dep45, }, + { NELS(dep48), dep48, NELS(dep47), dep47, }, + { NELS(dep50), dep50, NELS(dep49), dep49, }, + { NELS(dep52), dep52, NELS(dep51), dep51, }, + { NELS(dep54), dep54, NELS(dep53), dep53, }, + { NELS(dep56), dep56, NELS(dep55), dep55, }, + { NELS(dep58), dep58, NELS(dep57), dep57, }, + { NELS(dep60), dep60, NELS(dep59), dep59, }, + { NELS(dep62), dep62, NELS(dep61), dep61, }, + { NELS(dep64), dep64, NELS(dep63), dep63, }, + { NELS(dep66), dep66, NELS(dep65), dep65, }, + { NELS(dep68), dep68, NELS(dep67), dep67, }, + { NELS(dep69), dep69, NELS(dep34), dep34, }, + { NELS(dep71), dep71, NELS(dep70), dep70, }, + { NELS(dep73), dep73, NELS(dep72), dep72, }, + { NELS(dep75), dep75, NELS(dep74), dep74, }, + { NELS(dep77), dep77, NELS(dep76), dep76, }, + { NELS(dep78), dep78, NELS(dep34), dep34, }, + { NELS(dep80), dep80, NELS(dep79), dep79, }, + { NELS(dep82), dep82, NELS(dep81), dep81, }, + { NELS(dep84), dep84, NELS(dep83), dep83, }, + { NELS(dep85), dep85, NELS(dep34), dep34, }, + { NELS(dep86), dep86, NELS(dep34), dep34, }, + { NELS(dep87), dep87, NELS(dep34), dep34, }, + { NELS(dep88), dep88, NELS(dep34), dep34, }, + { NELS(dep90), dep90, NELS(dep89), dep89, }, + { NELS(dep92), dep92, NELS(dep91), dep91, }, + { NELS(dep94), dep94, NELS(dep93), dep93, }, + { NELS(dep96), dep96, NELS(dep95), dep95, }, + { NELS(dep98), dep98, NELS(dep97), dep97, }, + { NELS(dep100), dep100, NELS(dep99), dep99, }, + { NELS(dep102), dep102, NELS(dep101), dep101, }, + { NELS(dep104), dep104, NELS(dep103), dep103, }, + { NELS(dep106), dep106, NELS(dep105), dep105, }, + { NELS(dep108), dep108, NELS(dep107), dep107, }, + { NELS(dep110), dep110, NELS(dep109), dep109, }, + { NELS(dep112), dep112, NELS(dep111), dep111, }, + { NELS(dep114), dep114, NELS(dep113), dep113, }, + { NELS(dep116), dep116, NELS(dep115), dep115, }, + { NELS(dep118), dep118, NELS(dep117), dep117, }, + { NELS(dep120), dep120, NELS(dep119), dep119, }, + { NELS(dep122), dep122, NELS(dep121), dep121, }, + { NELS(dep123), dep123, NELS(dep65), dep65, }, + { NELS(dep124), dep124, NELS(dep34), dep34, }, + { NELS(dep126), dep126, NELS(dep125), dep125, }, + { NELS(dep127), dep127, NELS(dep0), dep0, }, + { NELS(dep129), dep129, NELS(dep128), dep128, }, + { NELS(dep131), dep131, NELS(dep130), dep130, }, + { NELS(dep132), dep132, NELS(dep0), dep0, }, + { NELS(dep133), dep133, NELS(dep0), dep0, }, + { NELS(dep135), dep135, NELS(dep134), dep134, }, + { NELS(dep136), dep136, NELS(dep0), dep0, }, + { NELS(dep137), dep137, NELS(dep34), dep34, }, + { NELS(dep139), dep139, NELS(dep138), dep138, }, + { NELS(dep140), dep140, NELS(dep138), dep138, }, + { NELS(dep142), dep142, NELS(dep141), dep141, }, + { NELS(dep143), dep143, NELS(dep141), dep141, }, + { NELS(dep144), dep144, NELS(dep138), dep138, }, + { NELS(dep146), dep146, NELS(dep145), dep145, }, + { NELS(dep148), dep148, NELS(dep147), dep147, }, + { NELS(dep150), dep150, NELS(dep149), dep149, }, + { NELS(dep152), dep152, NELS(dep151), dep151, }, + { NELS(dep153), dep153, NELS(dep0), dep0, }, + { NELS(dep155), dep155, NELS(dep154), dep154, }, + { NELS(dep157), dep157, NELS(dep156), dep156, }, + { NELS(dep159), dep159, NELS(dep158), dep158, }, + { NELS(dep161), dep161, NELS(dep160), dep160, }, + { NELS(dep163), dep163, NELS(dep162), dep162, }, + { NELS(dep164), dep164, NELS(dep0), dep0, }, + { NELS(dep165), dep165, NELS(dep0), dep0, }, + { NELS(dep166), dep166, NELS(dep0), dep0, }, + { NELS(dep167), dep167, NELS(dep34), dep34, }, + { NELS(dep169), dep169, NELS(dep168), dep168, }, + { NELS(dep170), dep170, NELS(dep168), dep168, }, + { NELS(dep172), dep172, NELS(dep171), dep171, }, + { NELS(dep174), dep174, NELS(dep173), dep173, }, + { NELS(dep176), dep176, NELS(dep175), dep175, }, + { NELS(dep178), dep178, NELS(dep177), dep177, }, + { NELS(dep180), dep180, NELS(dep179), dep179, }, + { NELS(dep182), dep182, NELS(dep181), dep181, }, + { NELS(dep184), dep184, NELS(dep183), dep183, }, + { NELS(dep186), dep186, NELS(dep185), dep185, }, + { NELS(dep188), dep188, NELS(dep187), dep187, }, + { NELS(dep189), dep189, NELS(dep0), dep0, }, + { NELS(dep190), dep190, NELS(dep0), dep0, }, + { NELS(dep191), dep191, NELS(dep0), dep0, }, + { NELS(dep192), dep192, NELS(dep0), dep0, }, + { NELS(dep193), dep193, NELS(dep0), dep0, }, + { NELS(dep194), dep194, NELS(dep0), dep0, }, + { NELS(dep195), dep195, NELS(dep0), dep0, }, + { NELS(dep196), dep196, NELS(dep0), dep0, }, + { NELS(dep198), dep198, NELS(dep197), dep197, }, + { NELS(dep200), dep200, NELS(dep199), dep199, }, + { NELS(dep202), dep202, NELS(dep201), dep201, }, + { NELS(dep204), dep204, NELS(dep203), dep203, }, + { NELS(dep205), dep205, NELS(dep0), dep0, }, + { NELS(dep206), dep206, NELS(dep0), dep0, }, + { NELS(dep207), dep207, NELS(dep0), dep0, }, + { NELS(dep208), dep208, NELS(dep34), dep34, }, + { NELS(dep209), dep209, NELS(dep34), dep34, }, + { NELS(dep210), dep210, NELS(dep197), dep197, }, + { NELS(dep211), dep211, NELS(dep0), dep0, }, + { NELS(dep212), dep212, NELS(dep0), dep0, }, + { NELS(dep214), dep214, NELS(dep213), dep213, }, + { NELS(dep215), dep215, NELS(dep213), dep213, }, + { NELS(dep216), dep216, NELS(dep0), dep0, }, + { NELS(dep214), dep214, NELS(dep217), dep217, }, + { NELS(dep219), dep219, NELS(dep218), dep218, }, + { NELS(dep221), dep221, NELS(dep220), dep220, }, + { NELS(dep223), dep223, NELS(dep222), dep222, }, + { NELS(dep224), dep224, NELS(dep222), dep222, }, + { NELS(dep225), dep225, NELS(dep0), dep0, }, + { NELS(dep226), dep226, NELS(dep65), dep65, }, + { NELS(dep227), dep227, NELS(dep65), dep65, }, + { NELS(dep229), dep229, NELS(dep228), dep228, }, + { NELS(dep230), dep230, NELS(dep228), dep228, }, + { NELS(dep229), dep229, NELS(dep231), dep231, }, + { NELS(dep232), dep232, NELS(dep34), dep34, }, + { NELS(dep233), dep233, NELS(dep34), dep34, }, + { NELS(dep234), dep234, NELS(dep0), dep0, }, + { NELS(dep235), dep235, NELS(dep0), dep0, }, + { NELS(dep236), dep236, NELS(dep34), dep34, }, + { NELS(dep237), dep237, NELS(dep15), dep15, }, + { NELS(dep239), dep239, NELS(dep238), dep238, }, +}; + +static const struct ia64_completer_table +completer_table[] = { + { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 1 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 90 }, + { 0x0, 0x0, 0, 123, -1, 0, 1, 8 }, + { 0x0, 0x0, 0, 128, -1, 0, 1, 19 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, 502, -1, 0, 1, 12 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 11 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 73 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 15 }, + { 0x1, 0x1, 0, 716, -1, 13, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 35 }, + { 0x0, 0x0, 0, 142, -1, 0, 1, 31 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 31 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 46 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 42 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 80 }, + { 0x0, 0x0, 0, 144, -1, 0, 1, 31 }, + { 0x0, 0x0, 0, 146, -1, 0, 1, 31 }, + { 0x0, 0x0, 0, 533, -1, 0, 1, 31 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 26 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 37 }, + { 0x0, 0x0, 0, 419, -1, 0, 1, 35 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 79 }, + { 0x0, 0x0, 0, 78, -1, 0, 1, 126 }, + { 0x0, 0x0, 0, 79, -1, 0, 1, 126 }, + { 0x0, 0x0, 0, 80, -1, 0, 1, 137 }, + { 0x0, 0x0, 0, 218, -1, 0, 1, 142 }, + { 0x0, 0x0, 0, 220, -1, 0, 1, 144 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 81 }, + { 0x0, 0x0, 0, 81, -1, 0, 1, 42 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 2 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 69 }, + { 0x1, 0x1, 0, 205, -1, 20, 1, 69 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 70 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 71 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 72 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 74 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 88 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 89 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 91 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 92 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 93 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 94 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 99 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 100 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 101 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 102 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 103 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 104 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 105 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 108 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 109 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 110 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 111 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 112 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 113 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 114 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 115 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 148 }, + { 0x0, 0x0, 0, 712, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 509, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 717, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 13 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 86 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 85 }, + { 0x0, 0x0, 0, 474, -1, 0, 1, 132 }, + { 0x0, 0x0, 0, 476, -1, 0, 1, 132 }, + { 0x0, 0x0, 0, 473, -1, 0, 1, 132 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 84 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 122 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 120 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 121 }, + { 0x0, 0x0, 0, 432, -1, 0, 1, 135 }, + { 0x0, 0x0, 1, 76, -1, 0, 1, 14 }, + { 0x1, 0x1, 2, -1, -1, 27, 1, 14 }, + { 0x0, 0x0, 3, -1, 133, 0, 0, -1 }, + { 0x1, 0x1, 3, 85, 433, 33, 1, 128 }, + { 0x1, 0x1, 3, 86, 433, 33, 1, 128 }, + { 0x1, 0x1, 3, 113, 441, 33, 1, 139 }, + { 0x1, 0x1, 3, -1, -1, 27, 1, 42 }, + { 0x0, 0x0, 4, 510, 431, 0, 1, 134 }, + { 0x0, 0x0, 4, 511, 432, 0, 1, 135 }, + { 0x1, 0x1, 4, 435, 435, 33, 1, 131 }, + { 0x5, 0x5, 4, 109, 434, 32, 1, 126 }, + { 0x5, 0x5, 4, 110, 434, 32, 1, 126 }, + { 0x1, 0x21, 10, 479, -1, 33, 1, 5 }, + { 0x200001, 0x200001, 10, 480, -1, 12, 1, 5 }, + { 0x1, 0x1, 10, 481, -1, 33, 1, 5 }, + { 0x0, 0x0, 10, 482, -1, 0, 1, 5 }, + { 0x1, 0x1, 10, 483, -1, 12, 1, 5 }, + { 0x0, 0x0, 10, -1, 490, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 491, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 492, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 493, 0, 0, -1 }, + { 0x1000001, 0x1000001, 10, 484, -1, 12, 1, 5 }, + { 0x1, 0x1, 10, 485, -1, 36, 1, 5 }, + { 0x0, 0x0, 10, 106, 494, 0, 0, -1 }, + { 0x0, 0x0, 10, 107, 496, 0, 0, -1 }, + { 0x2, 0x3, 11, -1, -1, 37, 1, 7 }, + { 0x1, 0x1, 11, 486, -1, 12, 1, 5 }, + { 0x0, 0x0, 11, 487, -1, 0, 1, 5 }, + { 0x200001, 0x200001, 11, 488, -1, 12, 1, 5 }, + { 0x1, 0x1, 11, 489, -1, 33, 1, 5 }, + { 0x1, 0x1, 11, -1, -1, 36, 1, 7 }, + { 0x1, 0x1, 11, 495, -1, 36, 1, 5 }, + { 0x1000001, 0x1000001, 11, 497, -1, 12, 1, 5 }, + { 0x0, 0x0, 12, -1, -1, 0, 1, 16 }, + { 0x1, 0x1, 13, 111, 434, 34, 1, 126 }, + { 0x1, 0x1, 13, 112, 434, 34, 1, 126 }, + { 0x0, 0x0, 19, 438, 134, 0, 0, -1 }, + { 0x0, 0x0, 19, 274, 134, 0, 0, -1 }, + { 0x0, 0x0, 19, 445, 135, 0, 0, -1 }, + { 0x0, 0x0, 20, -1, 161, 0, 0, -1 }, + { 0x0, 0x0, 20, -1, 162, 0, 0, -1 }, + { 0x0, 0x0, 20, -1, 175, 0, 0, -1 }, + { 0x0, 0x0, 20, -1, 176, 0, 0, -1 }, + { 0x0, 0x0, 21, 140, 171, 0, 0, -1 }, + { 0x0, 0x0, 21, 141, 173, 0, 0, -1 }, + { 0x0, 0x0, 23, -1, 169, 0, 0, -1 }, + { 0x0, 0x0, 23, -1, 170, 0, 0, -1 }, + { 0x1, 0x1, 24, -1, -1, 35, 1, 8 }, + { 0x1, 0x1, 24, 230, -1, 35, 1, 8 }, + { 0x1, 0x1, 24, -1, -1, 35, 1, 9 }, + { 0x1, 0x1, 24, -1, -1, 35, 1, 10 }, + { 0x1, 0x1, 24, -1, -1, 35, 1, 17 }, + { 0x1, 0x1, 24, -1, -1, 35, 1, 19 }, + { 0x1, 0x1, 24, 246, -1, 35, 1, 19 }, + { 0x1, 0x1, 24, -1, -1, 35, 1, 20 }, + { 0x1, 0x1, 24, -1, -1, 35, 1, 21 }, + { 0x1, 0x1, 24, -1, -1, 35, 1, 22 }, + { 0x1, 0x1, 24, -1, -1, 35, 1, 23 }, + { 0x1, 0x1, 24, 404, -1, 33, 1, 78 }, + { 0x1, 0x1, 24, 405, 84, 35, 1, 131 }, + { 0x1, 0x1, 24, 406, 442, 35, 1, 141 }, + { 0x0, 0x0, 32, 155, 153, 0, 0, -1 }, + { 0x0, 0x0, 32, 158, 156, 0, 0, -1 }, + { 0x0, 0x0, 32, 163, 163, 0, 0, -1 }, + { 0x0, 0x0, 32, 164, 164, 0, 0, -1 }, + { 0x0, 0x0, 34, -1, 172, 0, 0, -1 }, + { 0x0, 0x0, 34, -1, 174, 0, 0, -1 }, + { 0x1, 0x1, 37, 523, 533, 37, 1, 31 }, + { 0x0, 0x0, 37, 524, 551, 0, 0, -1 }, + { 0x1, 0x1, 37, 525, -1, 37, 1, 31 }, + { 0x0, 0x0, 37, 527, 551, 0, 0, -1 }, + { 0x1, 0x1, 37, 528, -1, 37, 1, 31 }, + { 0x3, 0x3, 37, 222, -1, 30, 1, 136 }, + { 0x0, 0x0, 37, 308, -1, 0, 1, 97 }, + { 0x0, 0x0, 37, -1, -1, 0, 1, 106 }, + { 0x0, 0x0, 37, 312, -1, 0, 1, 118 }, + { 0x3, 0x3, 37, 223, -1, 30, 1, 146 }, + { 0x0, 0x0, 37, 313, -1, 0, 1, 42 }, + { 0x0, 0x0, 39, 177, 231, 0, 0, -1 }, + { 0x0, 0x0, 39, 178, 234, 0, 0, -1 }, + { 0x0, 0x0, 39, 179, 231, 0, 0, -1 }, + { 0x3, 0x3, 39, 180, 122, 33, 1, 8 }, + { 0x18000001, 0x18000001, 39, 181, 124, 6, 1, 9 }, + { 0x3, 0x3, 39, 182, 122, 33, 1, 8 }, + { 0x0, 0x0, 39, 183, 238, 0, 0, -1 }, + { 0x3, 0x3, 39, 184, 125, 33, 1, 10 }, + { 0x0, 0x0, 39, 185, 242, 0, 0, -1 }, + { 0x3, 0x3, 39, 186, 126, 33, 1, 17 }, + { 0x0, 0x0, 39, 187, 247, 0, 0, -1 }, + { 0x3, 0x3, 39, 188, 127, 33, 1, 19 }, + { 0x0, 0x0, 39, 189, 250, 0, 0, -1 }, + { 0x0, 0x0, 39, 190, 254, 0, 0, -1 }, + { 0x3, 0x3, 39, 191, 129, 33, 1, 20 }, + { 0x18000001, 0x18000001, 39, 192, 129, 6, 1, 20 }, + { 0x0, 0x0, 39, 193, 258, 0, 0, -1 }, + { 0x3, 0x3, 39, 194, 130, 33, 1, 21 }, + { 0x0, 0x0, 39, 195, 262, 0, 0, -1 }, + { 0x0, 0x0, 39, 196, 266, 0, 0, -1 }, + { 0x3, 0x3, 39, 197, 131, 33, 1, 22 }, + { 0x18000001, 0x18000001, 39, 198, 131, 6, 1, 22 }, + { 0x0, 0x0, 39, 199, 270, 0, 0, -1 }, + { 0x3, 0x3, 39, 200, 132, 33, 1, 23 }, + { 0x0, 0x0, 40, 661, 232, 0, 0, -1 }, + { 0x0, 0x0, 40, 662, 235, 0, 0, -1 }, + { 0x0, 0x0, 40, 314, 232, 0, 0, -1 }, + { 0x1, 0x1, 40, 663, 122, 34, 1, 8 }, + { 0x10000001, 0x10000001, 40, 664, 124, 6, 1, 9 }, + { 0x1, 0x1, 40, 315, 122, 34, 1, 8 }, + { 0x0, 0x0, 40, 665, 239, 0, 0, -1 }, + { 0x1, 0x1, 40, 666, 125, 34, 1, 10 }, + { 0x0, 0x0, 40, 667, 243, 0, 0, -1 }, + { 0x1, 0x1, 40, 668, 126, 34, 1, 17 }, + { 0x0, 0x0, 40, 669, 248, 0, 0, -1 }, + { 0x1, 0x1, 40, 670, 127, 34, 1, 19 }, + { 0x0, 0x0, 40, 671, 251, 0, 0, -1 }, + { 0x0, 0x0, 40, 672, 255, 0, 0, -1 }, + { 0x1, 0x1, 40, 673, 129, 34, 1, 20 }, + { 0x10000001, 0x10000001, 40, 674, 129, 6, 1, 20 }, + { 0x0, 0x0, 40, 675, 259, 0, 0, -1 }, + { 0x1, 0x1, 40, 676, 130, 34, 1, 21 }, + { 0x0, 0x0, 40, 677, 263, 0, 0, -1 }, + { 0x0, 0x0, 40, 678, 267, 0, 0, -1 }, + { 0x1, 0x1, 40, 679, 131, 34, 1, 22 }, + { 0x10000001, 0x10000001, 40, 680, 131, 6, 1, 22 }, + { 0x0, 0x0, 40, 681, 271, 0, 0, -1 }, + { 0x1, 0x1, 40, 682, 132, 34, 1, 23 }, + { 0x800001, 0x800001, 40, 705, 316, 4, 1, 18 }, + { 0x1, 0x1, 40, 516, 316, 4, 1, 18 }, + { 0x1, 0x1, 40, 221, 317, 4, 1, 24 }, + { 0x2, 0x3, 40, 319, 318, 20, 1, 69 }, + { 0x1, 0x1, 40, 320, 318, 21, 1, 69 }, + { 0x0, 0x0, 41, -1, -1, 0, 1, 82 }, + { 0x0, 0x0, 41, -1, -1, 0, 1, 125 }, + { 0x1, 0x1, 43, 342, 87, 38, 1, 3 }, + { 0x0, 0x0, 43, 409, 101, 0, 0, -1 }, + { 0x0, 0x0, 43, 410, 92, 0, 0, -1 }, + { 0x1, 0x1, 43, 346, 87, 38, 1, 3 }, + { 0x0, 0x0, 43, 334, 538, 0, 0, -1 }, + { 0x0, 0x0, 43, 335, 724, 0, 1, 56 }, + { 0x0, 0x0, 43, 336, 554, 0, 0, -1 }, + { 0x0, 0x0, 43, 337, -1, 0, 1, 51 }, + { 0x0, 0x0, 43, 298, -1, 0, 1, 0 }, + { 0x1, 0x1, 44, 447, 447, 30, 1, 143 }, + { 0x1, 0x1, 44, 225, 446, 30, 1, 142 }, + { 0x1, 0x1, 44, 449, 449, 30, 1, 145 }, + { 0x1, 0x1, 44, 226, 448, 30, 1, 144 }, + { 0x3, 0x3, 45, 340, 317, 3, 1, 24 }, + { 0x1, 0x1, 46, 529, -1, 30, 1, 136 }, + { 0x1, 0x1, 46, 532, -1, 30, 1, 146 }, + { 0x0, 0x0, 48, -1, -1, 0, 1, 42 }, + { 0x1, 0x1, 55, 446, 217, 31, 1, 143 }, + { 0x1, 0x1, 55, 448, 219, 31, 1, 145 }, + { 0x2, 0x3, 55, -1, -1, 27, 1, 96 }, + { 0x0, 0x0, 55, -1, -1, 0, 1, 96 }, + { 0x1, 0x1, 55, -1, -1, 28, 1, 96 }, + { 0x0, 0x0, 64, 360, 122, 0, 1, 8 }, + { 0x3, 0x3, 64, 361, 122, 33, 1, 8 }, + { 0x1, 0x1, 64, 362, 122, 34, 1, 8 }, + { 0x1, 0x1, 64, 363, 122, 33, 1, 8 }, + { 0x18000001, 0x18000001, 64, 364, 124, 6, 1, 9 }, + { 0x10000001, 0x10000001, 64, 365, 124, 6, 1, 9 }, + { 0x8000001, 0x8000001, 64, 366, 124, 6, 1, 9 }, + { 0x1, 0x1, 64, 367, 124, 6, 1, 9 }, + { 0x3, 0x3, 64, 368, 125, 33, 1, 10 }, + { 0x1, 0x1, 64, 369, 125, 34, 1, 10 }, + { 0x1, 0x1, 64, 370, 125, 33, 1, 10 }, + { 0x0, 0x0, 64, 371, 125, 0, 1, 10 }, + { 0x3, 0x3, 64, 372, 126, 33, 1, 17 }, + { 0x1, 0x1, 64, 373, 126, 34, 1, 17 }, + { 0x1, 0x1, 64, 374, 126, 33, 1, 17 }, + { 0x0, 0x0, 64, 375, 126, 0, 1, 17 }, + { 0x0, 0x0, 64, 376, 127, 0, 1, 19 }, + { 0x3, 0x3, 64, 377, 127, 33, 1, 19 }, + { 0x1, 0x1, 64, 378, 127, 34, 1, 19 }, + { 0x1, 0x1, 64, 379, 127, 33, 1, 19 }, + { 0x3, 0x3, 64, 380, 129, 33, 1, 20 }, + { 0x1, 0x1, 64, 381, 129, 34, 1, 20 }, + { 0x1, 0x1, 64, 382, 129, 33, 1, 20 }, + { 0x0, 0x0, 64, 383, 129, 0, 1, 20 }, + { 0x18000001, 0x18000001, 64, 384, 129, 6, 1, 20 }, + { 0x10000001, 0x10000001, 64, 385, 129, 6, 1, 20 }, + { 0x8000001, 0x8000001, 64, 386, 129, 6, 1, 20 }, + { 0x1, 0x1, 64, 387, 129, 6, 1, 20 }, + { 0x3, 0x3, 64, 388, 130, 33, 1, 21 }, + { 0x1, 0x1, 64, 389, 130, 34, 1, 21 }, + { 0x1, 0x1, 64, 390, 130, 33, 1, 21 }, + { 0x0, 0x0, 64, 391, 130, 0, 1, 21 }, + { 0x3, 0x3, 64, 392, 131, 33, 1, 22 }, + { 0x1, 0x1, 64, 393, 131, 34, 1, 22 }, + { 0x1, 0x1, 64, 394, 131, 33, 1, 22 }, + { 0x0, 0x0, 64, 395, 131, 0, 1, 22 }, + { 0x18000001, 0x18000001, 64, 396, 131, 6, 1, 22 }, + { 0x10000001, 0x10000001, 64, 397, 131, 6, 1, 22 }, + { 0x8000001, 0x8000001, 64, 398, 131, 6, 1, 22 }, + { 0x1, 0x1, 64, 399, 131, 6, 1, 22 }, + { 0x3, 0x3, 64, 400, 132, 33, 1, 23 }, + { 0x1, 0x1, 64, 401, 132, 34, 1, 23 }, + { 0x1, 0x1, 64, 402, 132, 33, 1, 23 }, + { 0x0, 0x0, 64, 403, 132, 0, 1, 23 }, + { 0x3, 0x3, 65, 438, 439, 33, 1, 130 }, + { 0x0, 0x0, 65, -1, 440, 0, 1, 137 }, + { 0x0, 0x0, 106, 278, 548, 0, 0, -1 }, + { 0x0, 0x0, 106, 279, 715, 0, 1, 31 }, + { 0x0, 0x0, 108, -1, 550, 0, 0, -1 }, + { 0x1, 0x1, 108, -1, 715, 27, 1, 31 }, + { 0x0, 0x0, 109, 281, -1, 0, 1, 117 }, + { 0x1, 0x1, 110, -1, -1, 27, 1, 117 }, + { 0x0, 0x0, 111, 289, 718, 0, 1, 3 }, + { 0x0, 0x0, 111, 292, 89, 0, 0, -1 }, + { 0x0, 0x0, 111, 293, 103, 0, 0, -1 }, + { 0x0, 0x0, 111, 295, 94, 0, 0, -1 }, + { 0x0, 0x0, 111, 408, 718, 0, 1, 3 }, + { 0x0, 0x0, 111, 296, 546, 0, 0, -1 }, + { 0x1, 0x9, 111, 297, 724, 33, 1, 56 }, + { 0x1, 0x1, 113, 408, 718, 37, 1, 3 }, + { 0x0, 0x0, 113, -1, 718, 0, 1, 3 }, + { 0x0, 0x0, 114, 299, 718, 0, 1, 3 }, + { 0x0, 0x0, 114, 330, 90, 0, 0, -1 }, + { 0x0, 0x0, 114, 331, 101, 0, 0, -1 }, + { 0x0, 0x0, 114, -1, 718, 0, 1, 3 }, + { 0x0, 0x0, 114, 333, 92, 0, 0, -1 }, + { 0x0, 0x0, 114, -1, 538, 0, 0, -1 }, + { 0x0, 0x0, 114, -1, 724, 0, 1, 56 }, + { 0x1, 0x1, 114, -1, -1, 27, 1, 0 }, + { 0x1, 0x1, 115, -1, 718, 37, 1, 3 }, + { 0x0, 0x0, 115, -1, 718, 0, 1, 3 }, + { 0x0, 0x0, 116, 326, -1, 0, 1, 0 }, + { 0x3, 0x3, 116, 304, -1, 34, 1, 35 }, + { 0x3, 0x3, 116, 305, -1, 34, 1, 42 }, + { 0x1, 0x1, 117, 327, -1, 35, 1, 35 }, + { 0x1, 0x1, 117, 328, -1, 35, 1, 42 }, + { 0x0, 0x0, 118, -1, -1, 0, 1, 42 }, + { 0x0, 0x0, 118, -1, -1, 0, 1, 68 }, + { 0x1, 0x1, 118, -1, -1, 27, 1, 98 }, + { 0x0, 0x0, 118, -1, -1, 0, 1, 107 }, + { 0x0, 0x0, 118, -1, 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0x9, 217, 575, -1, 33, 1, 50 }, + { 0x200001, 0x1200001, 217, 576, -1, 12, 1, 60 }, + { 0x1, 0x9, 217, 577, -1, 33, 1, 55 }, + { 0x1, 0x1, 217, 578, -1, 28, 1, 30 }, + { 0x0, 0x0, 217, 579, -1, 0, 1, 30 }, + { 0x3, 0x3, 217, 580, -1, 27, 1, 30 }, + { 0x1, 0x1, 217, 581, -1, 27, 1, 30 }, + { 0x1, 0x1, 217, 582, -1, 37, 1, 30 }, + { 0x1, 0x1, 217, -1, -1, 36, 1, 67 }, + { 0x1, 0x1, 217, 583, -1, 36, 1, 67 }, + { 0x0, 0x0, 217, 584, -1, 0, 1, 50 }, + { 0x1, 0x1, 217, 585, -1, 28, 1, 50 }, + { 0x1, 0x1, 217, 586, -1, 27, 1, 50 }, + { 0x1, 0x1, 217, 587, -1, 29, 1, 50 }, + { 0x3, 0x3, 217, 588, -1, 28, 1, 50 }, + { 0x5, 0x5, 217, 589, -1, 27, 1, 50 }, + { 0x7, 0x7, 217, 590, -1, 27, 1, 50 }, + { 0x3, 0x3, 217, 591, -1, 27, 1, 50 }, + { 0x0, 0x0, 217, 592, -1, 0, 1, 25 }, + { 0x0, 0x0, 217, 593, -1, 0, 1, 36 }, + { 0x1, 0x1, 218, 594, -1, 34, 1, 32 }, + { 0x1, 0x1, 218, 595, -1, 34, 1, 67 }, + { 0x1, 0x1, 218, 596, -1, 34, 1, 47 }, + { 0x1, 0x1, 218, 597, -1, 34, 1, 43 }, + { 0x400001, 0x400001, 218, 598, -1, 12, 1, 62 }, + { 0x1, 0x1, 218, 599, -1, 34, 1, 57 }, + { 0x600001, 0x600001, 218, 600, -1, 12, 1, 62 }, + { 0x3, 0x3, 218, 601, -1, 33, 1, 57 }, + { 0x1400001, 0x1400001, 218, 602, -1, 12, 1, 62 }, + { 0x5, 0x5, 218, 603, -1, 34, 1, 57 }, + { 0x1600001, 0x1600001, 218, 604, -1, 12, 1, 52 }, + { 0xb, 0xb, 218, 605, -1, 33, 1, 52 }, + { 0x600001, 0x1600001, 218, 606, -1, 12, 1, 62 }, + { 0x3, 0xb, 218, 607, -1, 33, 1, 57 }, + { 0x41, 0x41, 218, 608, -1, 28, 1, 32 }, + { 0x1, 0x1, 218, 609, -1, 34, 1, 32 }, + { 0x83, 0x83, 218, 610, -1, 27, 1, 32 }, + { 0x81, 0x81, 218, 611, -1, 27, 1, 32 }, + { 0x9, 0x9, 218, 612, -1, 34, 1, 32 }, + { 0x5, 0x5, 218, 613, -1, 34, 1, 67 }, + { 0x1, 0x1, 218, 614, -1, 34, 1, 52 }, + { 0x41, 0x41, 218, 615, -1, 28, 1, 52 }, + { 0x81, 0x81, 218, 616, -1, 27, 1, 52 }, + { 0x21, 0x21, 218, 617, -1, 29, 1, 52 }, + { 0x43, 0x43, 218, 618, -1, 28, 1, 52 }, + { 0x85, 0x85, 218, 619, -1, 27, 1, 52 }, + { 0x87, 0x87, 218, 620, -1, 27, 1, 52 }, + { 0x83, 0x83, 218, 621, -1, 27, 1, 52 }, + { 0x1, 0x1, 218, 622, -1, 34, 1, 27 }, + { 0x1, 0x1, 218, 623, -1, 34, 1, 38 }, + { 0x1, 0x1, 219, 624, -1, 35, 1, 33 }, + { 0x1, 0x1, 219, 625, -1, 35, 1, 67 }, + { 0x1, 0x1, 219, 626, -1, 35, 1, 48 }, + { 0x1, 0x1, 219, 627, -1, 35, 1, 44 }, + { 0x800001, 0x800001, 219, 628, -1, 12, 1, 63 }, + { 0x1, 0x1, 219, 629, -1, 35, 1, 58 }, + { 0xa00001, 0xa00001, 219, 630, -1, 12, 1, 63 }, + { 0x5, 0x5, 219, 631, -1, 33, 1, 58 }, + { 0x1800001, 0x1800001, 219, 632, -1, 12, 1, 63 }, + { 0x3, 0x3, 219, 633, -1, 35, 1, 58 }, + { 0x1a00001, 0x1a00001, 219, 634, -1, 12, 1, 53 }, + { 0xd, 0xd, 219, 635, -1, 33, 1, 53 }, + { 0xa00001, 0x1a00001, 219, 636, -1, 12, 1, 63 }, + { 0x5, 0xd, 219, 637, -1, 33, 1, 58 }, + { 0x81, 0x81, 219, 638, -1, 28, 1, 33 }, + { 0x1, 0x1, 219, 639, -1, 35, 1, 33 }, + { 0x103, 0x103, 219, 640, -1, 27, 1, 33 }, + { 0x101, 0x101, 219, 641, -1, 27, 1, 33 }, + { 0x5, 0x5, 219, 642, -1, 35, 1, 33 }, + { 0x3, 0x3, 219, 643, -1, 35, 1, 67 }, + { 0x1, 0x1, 219, 644, -1, 35, 1, 53 }, + { 0x81, 0x81, 219, 645, -1, 28, 1, 53 }, + { 0x101, 0x101, 219, 646, -1, 27, 1, 53 }, + { 0x41, 0x41, 219, 647, -1, 29, 1, 53 }, + { 0x83, 0x83, 219, 648, -1, 28, 1, 53 }, + { 0x105, 0x105, 219, 649, -1, 27, 1, 53 }, + { 0x107, 0x107, 219, 650, -1, 27, 1, 53 }, + { 0x103, 0x103, 219, 651, -1, 27, 1, 53 }, + { 0x1, 0x1, 219, 652, -1, 35, 1, 28 }, + { 0x1, 0x1, 219, 653, -1, 35, 1, 39 }, + { 0x3, 0x3, 220, -1, -1, 34, 1, 34 }, + { 0x3, 0x3, 220, -1, -1, 34, 1, 67 }, + { 0x3, 0x3, 220, -1, -1, 34, 1, 49 }, + { 0x3, 0x3, 220, -1, -1, 34, 1, 45 }, + { 0xc00001, 0xc00001, 220, -1, -1, 12, 1, 64 }, + { 0x3, 0x3, 220, 720, -1, 34, 1, 59 }, + { 0xe00001, 0xe00001, 220, -1, -1, 12, 1, 64 }, + { 0x7, 0x7, 220, 721, -1, 33, 1, 59 }, + { 0x1c00001, 0x1c00001, 220, -1, -1, 12, 1, 64 }, + { 0x7, 0x7, 220, 722, -1, 34, 1, 59 }, + { 0x1e00001, 0x1e00001, 220, -1, -1, 12, 1, 54 }, + { 0xf, 0xf, 220, 723, -1, 33, 1, 54 }, + { 0xe00001, 0x1e00001, 220, -1, -1, 12, 1, 64 }, + { 0x7, 0xf, 220, 726, -1, 33, 1, 59 }, + { 0xc1, 0xc1, 220, -1, -1, 28, 1, 34 }, + { 0x3, 0x3, 220, 713, -1, 34, 1, 34 }, + { 0x183, 0x183, 220, -1, -1, 27, 1, 34 }, + { 0x181, 0x181, 220, 714, -1, 27, 1, 34 }, + { 0xb, 0xb, 220, -1, -1, 34, 1, 34 }, + { 0x7, 0x7, 220, -1, -1, 34, 1, 67 }, + { 0x3, 0x3, 220, -1, -1, 34, 1, 54 }, + { 0xc1, 0xc1, 220, -1, -1, 28, 1, 54 }, + { 0x181, 0x181, 220, -1, -1, 27, 1, 54 }, + { 0x61, 0x61, 220, -1, -1, 29, 1, 54 }, + { 0xc3, 0xc3, 220, -1, -1, 28, 1, 54 }, + { 0x185, 0x185, 220, -1, -1, 27, 1, 54 }, + { 0x187, 0x187, 220, -1, -1, 27, 1, 54 }, + { 0x183, 0x183, 220, -1, -1, 27, 1, 54 }, + { 0x3, 0x3, 220, -1, -1, 34, 1, 29 }, + { 0x3, 0x3, 220, -1, -1, 34, 1, 40 }, + { 0x3, 0x3, 221, -1, 437, 32, 1, 129 }, + { 0x3, 0x3, 221, -1, 444, 32, 1, 140 }, + { 0x1, 0x1, 222, -1, -1, 28, 1, 35 }, + { 0x0, 0x0, 229, -1, -1, 0, 1, 136 }, + { 0x0, 0x0, 229, -1, -1, 0, 1, 146 }, + { 0x1, 0x1, 230, -1, 475, 33, 1, 133 }, + { 0x0, 0x0, 230, -1, 473, 0, 1, 132 }, + { 0x0, 0x0, 231, 683, 233, 0, 0, -1 }, + { 0x0, 0x0, 231, 684, 236, 0, 0, -1 }, + { 0x1, 0x1, 231, 685, 122, 33, 1, 8 }, + { 0x8000001, 0x8000001, 231, 686, 124, 6, 1, 9 }, + { 0x0, 0x0, 231, 687, 240, 0, 0, -1 }, + { 0x1, 0x1, 231, 688, 125, 33, 1, 10 }, + { 0x0, 0x0, 231, 689, 244, 0, 0, -1 }, + { 0x1, 0x1, 231, 690, 126, 33, 1, 17 }, + { 0x0, 0x0, 231, 691, 249, 0, 0, -1 }, + { 0x1, 0x1, 231, 692, 127, 33, 1, 19 }, + { 0x0, 0x0, 231, 693, 252, 0, 0, -1 }, + { 0x0, 0x0, 231, 694, 256, 0, 0, -1 }, + { 0x1, 0x1, 231, 695, 129, 33, 1, 20 }, + { 0x8000001, 0x8000001, 231, 696, 129, 6, 1, 20 }, + { 0x0, 0x0, 231, 697, 260, 0, 0, -1 }, + { 0x1, 0x1, 231, 698, 130, 33, 1, 21 }, + { 0x0, 0x0, 231, 699, 264, 0, 0, -1 }, + { 0x0, 0x0, 231, 700, 268, 0, 0, -1 }, + { 0x1, 0x1, 231, 701, 131, 33, 1, 22 }, + { 0x8000001, 0x8000001, 231, 702, 131, 6, 1, 22 }, + { 0x0, 0x0, 231, 703, 272, 0, 0, -1 }, + { 0x1, 0x1, 231, 704, 132, 33, 1, 23 }, + { 0x0, 0x0, 232, -1, 230, 0, 0, -1 }, + { 0x0, 0x0, 232, -1, 237, 0, 0, -1 }, + { 0x0, 0x0, 232, -1, 122, 0, 1, 8 }, + { 0x1, 0x1, 232, -1, 124, 6, 1, 9 }, + { 0x0, 0x0, 232, -1, 241, 0, 0, -1 }, + { 0x0, 0x0, 232, -1, 125, 0, 1, 10 }, + { 0x0, 0x0, 232, -1, 245, 0, 0, -1 }, + { 0x0, 0x0, 232, -1, 126, 0, 1, 17 }, + { 0x0, 0x0, 232, -1, 246, 0, 0, -1 }, + { 0x0, 0x0, 232, -1, 127, 0, 1, 19 }, + { 0x0, 0x0, 232, -1, 253, 0, 0, -1 }, + { 0x0, 0x0, 232, -1, 257, 0, 0, -1 }, + { 0x0, 0x0, 232, -1, 129, 0, 1, 20 }, + { 0x1, 0x1, 232, -1, 129, 6, 1, 20 }, + { 0x0, 0x0, 232, -1, 261, 0, 0, -1 }, + { 0x0, 0x0, 232, -1, 130, 0, 1, 21 }, + { 0x0, 0x0, 232, -1, 265, 0, 0, -1 }, + { 0x0, 0x0, 232, -1, 269, 0, 0, -1 }, + { 0x0, 0x0, 232, -1, 131, 0, 1, 22 }, + { 0x1, 0x1, 232, -1, 131, 6, 1, 22 }, + { 0x0, 0x0, 232, -1, 273, 0, 0, -1 }, + { 0x0, 0x0, 232, -1, 132, 0, 1, 23 }, + { 0x1, 0x1, 232, -1, 316, 27, 1, 18 }, + { 0x0, 0x0, 232, -1, 316, 0, 1, 18 }, + { 0x0, 0x0, 232, -1, 317, 0, 1, 24 }, + { 0x0, 0x1, 232, -1, 318, 20, 1, 69 }, + { 0x0, 0x0, 232, -1, 318, 0, 1, 69 }, + { 0x1, 0x1, 235, 731, -1, 29, 1, 0 }, + { 0x0, 0x0, 235, -1, -1, 0, 1, 0 }, + { 0x1, 0x1, 235, 732, -1, 27, 1, 0 }, + { 0x0, 0x0, 256, -1, 547, 0, 0, -1 }, + { 0x0, 0x0, 256, -1, 549, 0, 0, -1 }, + { 0x1, 0x1, 256, -1, -1, 28, 1, 31 }, + { 0x0, 0x0, 258, -1, -1, 0, 1, 0 }, + { 0x0, 0x1, 258, -1, -1, 29, 1, 0 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 4 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 66 }, + { 0x0, 0x0, 259, -1, 537, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 539, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 541, 0, 0, -1 }, + { 0x0, 0x0, 259, -1, 543, 0, 0, -1 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 61 }, + { 0x1, 0x1, 259, -1, -1, 12, 1, 51 }, + { 0x0, 0x0, 259, -1, 545, 0, 0, -1 }, + { 0x0, 0x0, 260, -1, 544, 0, 0, -1 }, + { 0x9, 0x9, 260, -1, 725, 33, 1, 51 }, + { 0x0, 0x0, 260, -1, 561, 0, 0, -1 }, + { 0x3, 0x3, 260, -1, -1, 27, 1, 51 }, + { 0x0, 0x0, 264, -1, -1, 0, 1, 0 }, + { 0x3, 0x3, 265, 733, -1, 27, 1, 0 }, + { 0x1, 0x1, 266, -1, -1, 28, 1, 0 }, + { 0x1, 0x1, 267, -1, -1, 27, 1, 95 }, + { 0x0, 0x0, 267, -1, 229, 0, 0, -1 }, + { 0x0, 0x0, 268, 738, 165, 0, 0, -1 }, + { 0x0, 0x0, 268, 739, 167, 0, 0, -1 }, + { 0x0, 0x0, 269, -1, 166, 0, 0, -1 }, + { 0x0, 0x0, 269, -1, 168, 0, 0, -1 }, + { 0x0, 0x0, 270, -1, -1, 0, 1, 42 }, + { 0x0, 0x0, 275, -1, -1, 0, 1, 35 }, + { 0x0, 0x0, 279, -1, 142, 0, 1, 31 }, + { 0x0, 0x0, 280, -1, -1, 0, 1, 73 }, + { 0x0, 0x0, 280, -1, 97, 0, 1, 3 }, + { 0x0, 0x0, 280, -1, 99, 0, 0, -1 }, +}; + +static const struct ia64_main_table +main_table[] = { + { 5, 1, 1, 0x10000000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 5, 1, 1, 0x10008000000ull, 0x1eff8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 0, }, + { 5, 7, 1, 0x0ull, 0x0ull, { 23, 65, 25, 0, 0 }, 0x0, 0, }, + { 6, 1, 1, 0x12000000000ull, 0x1e000000000ull, { 23, 65, 26, 0, 0 }, 0x0, 1, }, + { 7, 1, 1, 0x10040000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 7, 1, 1, 0x10c00000000ull, 0x1ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 0, }, + { 8, 1, 1, 0x10800000000ull, 0x1ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 1, }, + { 9, 3, 1, 0x2c00000000ull, 0x1ee00000000ull, { 23, 2, 51, 52, 53 }, 0x221, 2, }, + { 10, 1, 1, 0x10060000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 10, 1, 1, 0x10160000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, }, + { 11, 1, 1, 0x10068000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 11, 1, 1, 0x10168000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, }, + { 14, 4, 0, 0x100000000ull, 0x1eff80011ffull, { 15, 0, 0, 0, 0 }, 0x40, 3, }, + { 14, 4, 0, 0x100000000ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x0, 136, }, + { 14, 4, 0, 0x100000000ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x40, 137, }, + { 14, 4, 0, 0x108000100ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x200, 514, }, + { 14, 4, 0, 0x108000100ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x240, 515, }, + { 14, 4, 1, 0x2000000000ull, 0x1ee00001000ull, { 14, 15, 0, 0, 0 }, 0x0, 114, }, + { 14, 4, 1, 0x2000000000ull, 0x1ee00001000ull, { 14, 15, 0, 0, 0 }, 0x40, 115, }, + { 14, 4, 0, 0x8000000000ull, 0x1ee000011ffull, { 80, 0, 0, 0, 0 }, 0x40, 4, }, + { 14, 4, 0, 0x8000000000ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x0, 138, }, + { 14, 4, 0, 0x8000000000ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x40, 139, }, + { 14, 4, 0, 0x8000000080ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x210, 736, }, + { 14, 4, 0, 0x8000000080ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x250, 737, }, + { 14, 4, 0, 0x8000000140ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x30, 120, }, + { 14, 4, 0, 0x8000000140ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x70, 121, }, + { 14, 4, 0, 0x8000000180ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x230, 118, }, + { 14, 4, 0, 0x8000000180ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x270, 119, }, + { 14, 4, 1, 0xa000000000ull, 0x1ee00001000ull, { 14, 80, 0, 0, 0 }, 0x0, 116, }, + { 14, 4, 1, 0xa000000000ull, 0x1ee00001000ull, { 14, 80, 0, 0, 0 }, 0x40, 117, }, + { 15, 4, 0, 0x0ull, 0x1e1f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 108, }, + { 15, 5, 0, 0x0ull, 0x1e3f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 224, }, + { 15, 2, 0, 0x0ull, 0x1eff8000000ull, { 64, 0, 0, 0, 0 }, 0x2, 306, }, + { 15, 3, 0, 0x0ull, 0x1eff8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 355, }, + { 15, 6, 0, 0x0ull, 0x1eff8000000ull, { 68, 0, 0, 0, 0 }, 0x0, 740, }, + { 15, 7, 0, 0x0ull, 0x0ull, { 64, 0, 0, 0, 0 }, 0x0, 5, }, + { 16, 6, 0, 0x18000000000ull, 0x1ee000011ffull, { 81, 0, 0, 0, 0 }, 0x40, 4, }, + { 16, 6, 0, 0x18000000000ull, 0x1ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x0, 138, }, + { 16, 6, 0, 0x18000000000ull, 0x1ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x40, 139, }, + { 16, 6, 1, 0x1a000000000ull, 0x1ee00001000ull, { 14, 81, 0, 0, 0 }, 0x0, 116, }, + { 16, 6, 1, 0x1a000000000ull, 0x1ee00001000ull, { 14, 81, 0, 0, 0 }, 0x40, 117, }, + { 17, 4, 0, 0x4080000000ull, 0x1e9f8000018ull, { 15, 76, 0, 0, 0 }, 0x20, 202, }, + { 17, 4, 0, 0xe000000000ull, 0x1e800000018ull, { 80, 76, 0, 0, 0 }, 0x20, 203, }, + { 18, 4, 0, 0x60000000ull, 0x1e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x2c, 75, }, + { 22, 2, 0, 0x200000000ull, 0x1ee00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 519, }, + { 22, 3, 0, 0x800000000ull, 0x1ee00000000ull, { 23, 80, 0, 0, 0 }, 0x0, 77, }, + { 22, 3, 0, 0xc00000000ull, 0x1ee00000000ull, { 17, 80, 0, 0, 0 }, 0x0, 77, }, + { 22, 3, 0, 0x2200000000ull, 0x1ee00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 520, }, + { 22, 3, 0, 0x2600000000ull, 0x1ee00000000ull, { 18, 79, 0, 0, 0 }, 0x0, 521, }, + { 22, 7, 0, 0x0ull, 0x0ull, { 24, 79, 0, 0, 0 }, 0x0, 522, }, + { 25, 4, 0, 0x20000000ull, 0x1e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 6, }, + { 26, 1, 2, 0x18000000000ull, 0x1fe00001000ull, { 21, 22, 24, 25, 0 }, 0x0, 208, }, + { 26, 1, 2, 0x18000000000ull, 0x1fe00001000ull, { 22, 21, 25, 24, 0 }, 0x0, 329, }, + { 26, 1, 2, 0x18000000000ull, 0x1fe00001000ull, { 21, 22, 25, 24, 0 }, 0x0, 291, }, + { 26, 1, 2, 0x18000000000ull, 0x1fe00001000ull, { 22, 21, 24, 25, 0 }, 0x0, 282, }, + { 26, 1, 2, 0x18200000000ull, 0x1fe00001000ull, { 21, 22, 24, 25, 0 }, 0x40, 209, }, + { 26, 1, 2, 0x19000000000ull, 0x1fe00001000ull, { 21, 22, 6, 25, 0 }, 0x0, 283, }, + { 26, 1, 2, 0x19000000000ull, 0x1fe00001000ull, { 21, 22, 6, 25, 0 }, 0x40, 284, }, + { 26, 1, 2, 0x18800000000ull, 0x1ee00001000ull, { 21, 22, 54, 25, 0 }, 0x0, 208, }, + { 26, 1, 2, 0x18800000000ull, 0x1ee00001000ull, { 21, 22, 56, 25, 0 }, 0x0, 332, }, + { 26, 1, 2, 0x18800000000ull, 0x1ee00001000ull, { 22, 21, 56, 25, 0 }, 0x0, 294, }, + { 26, 1, 2, 0x18800000000ull, 0x1ee00001000ull, { 22, 21, 54, 25, 0 }, 0x0, 282, }, + { 26, 1, 2, 0x18a00000000ull, 0x1ee00001000ull, { 21, 22, 54, 25, 0 }, 0x40, 209, }, + { 26, 1, 2, 0x1a800000000ull, 0x1ee00001000ull, { 21, 22, 58, 25, 0 }, 0x0, 339, }, + { 26, 1, 2, 0x1a800000000ull, 0x1ee00001000ull, { 22, 21, 58, 25, 0 }, 0x0, 300, }, + { 26, 1, 2, 0x1c200000000ull, 0x1fe00001000ull, { 22, 21, 24, 25, 0 }, 0x40, 210, }, + { 26, 1, 2, 0x1d000000000ull, 0x1fe00001000ull, { 22, 21, 6, 25, 0 }, 0x40, 285, }, + { 26, 1, 2, 0x1ca00000000ull, 0x1ee00001000ull, { 22, 21, 54, 25, 0 }, 0x40, 210, }, + { 27, 1, 2, 0x18400000000ull, 0x1fe00001000ull, { 21, 22, 24, 25, 0 }, 0x0, 208, }, + { 27, 1, 2, 0x18400000000ull, 0x1fe00001000ull, { 22, 21, 25, 24, 0 }, 0x0, 329, }, + { 27, 1, 2, 0x18400000000ull, 0x1fe00001000ull, { 21, 22, 25, 24, 0 }, 0x0, 291, }, + { 27, 1, 2, 0x18400000000ull, 0x1fe00001000ull, { 22, 21, 24, 25, 0 }, 0x0, 282, }, + { 27, 1, 2, 0x18600000000ull, 0x1fe00001000ull, { 21, 22, 24, 25, 0 }, 0x40, 209, }, + { 27, 1, 2, 0x19400000000ull, 0x1fe00001000ull, { 21, 22, 6, 25, 0 }, 0x0, 283, }, + { 27, 1, 2, 0x19400000000ull, 0x1fe00001000ull, { 21, 22, 6, 25, 0 }, 0x40, 284, }, + { 27, 1, 2, 0x18c00000000ull, 0x1ee00001000ull, { 21, 22, 54, 25, 0 }, 0x0, 211, }, + { 27, 1, 2, 0x18c00000000ull, 0x1ee00001000ull, { 21, 22, 56, 25, 0 }, 0x0, 332, }, + { 27, 1, 2, 0x18c00000000ull, 0x1ee00001000ull, { 22, 21, 56, 25, 0 }, 0x0, 294, }, + { 27, 1, 2, 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9, 67, 0, 0, 0 }, 0x0, 37, }, + { 152, 2, 1, 0x180000000ull, 0x1eff8000000ull, { 23, 7, 0, 0, 0 }, 0x0, 8, }, + { 152, 2, 1, 0x198000000ull, 0x1eff8000000ull, { 23, 8, 0, 0, 0 }, 0x0, 38, }, + { 152, 2, 1, 0x150000000ull, 0x1eff8000000ull, { 13, 24, 0, 0, 0 }, 0x0, 310, }, + { 152, 2, 1, 0x50000000ull, 0x1eff8000000ull, { 13, 54, 0, 0, 0 }, 0x0, 310, }, + { 152, 2, 1, 0x190000000ull, 0x1eff8000000ull, { 23, 13, 0, 0, 0 }, 0x0, 311, }, + { 152, 3, 1, 0x140000000ull, 0x1eff8000000ull, { 13, 54, 0, 0, 0 }, 0x0, 358, }, + { 152, 3, 1, 0x2150000000ull, 0x1eff8000000ull, { 13, 24, 0, 0, 0 }, 0x0, 358, }, + { 152, 3, 1, 0x2110000000ull, 0x1eff8000000ull, { 23, 13, 0, 0, 0 }, 0x0, 359, }, + { 152, 3, 1, 0x2160000000ull, 0x1eff8000000ull, { 16, 24, 0, 0, 0 }, 0x8, 39, }, + { 152, 3, 1, 0x2120000000ull, 0x1eff8000000ull, { 23, 16, 0, 0, 0 }, 0x8, 40, }, + { 152, 3, 1, 0x2168000000ull, 0x1eff8000000ull, { 11, 24, 0, 0, 0 }, 0x8, 41, }, + { 152, 3, 1, 0x2148000000ull, 0x1eff8000000ull, { 12, 24, 0, 0, 0 }, 0x0, 42, }, + { 152, 3, 1, 0x2128000000ull, 0x1eff8000000ull, { 23, 10, 0, 0, 0 }, 0x8, 43, }, + { 152, 3, 1, 0x2108000000ull, 0x1eff8000000ull, { 23, 12, 0, 0, 0 }, 0x0, 44, }, + { 152, 3, 1, 0x2000000000ull, 0x1eff8000000ull, { 37, 24, 0, 0, 0 }, 0x8, 45, }, + { 152, 3, 1, 0x2008000000ull, 0x1eff8000000ull, { 28, 24, 0, 0, 0 }, 0x8, 46, }, + { 152, 3, 1, 0x2010000000ull, 0x1eff8000000ull, { 31, 24, 0, 0, 0 }, 0x8, 47, }, + { 152, 3, 1, 0x2018000000ull, 0x1eff8000000ull, { 34, 24, 0, 0, 0 }, 0x8, 48, }, + { 152, 3, 1, 0x2020000000ull, 0x1eff8000000ull, { 35, 24, 0, 0, 0 }, 0x8, 49, }, + { 152, 3, 1, 0x2028000000ull, 0x1eff8000000ull, { 36, 24, 0, 0, 0 }, 0x8, 50, }, + { 152, 3, 1, 0x2030000000ull, 0x1eff8000000ull, { 33, 24, 0, 0, 0 }, 0x8, 51, }, + { 152, 3, 1, 0x2080000000ull, 0x1eff8000000ull, { 23, 37, 0, 0, 0 }, 0x8, 52, }, + { 152, 3, 1, 0x2088000000ull, 0x1eff8000000ull, { 23, 28, 0, 0, 0 }, 0x8, 53, }, + { 152, 3, 1, 0x2090000000ull, 0x1eff8000000ull, { 23, 31, 0, 0, 0 }, 0x8, 54, }, + { 152, 3, 1, 0x2098000000ull, 0x1eff8000000ull, { 23, 34, 0, 0, 0 }, 0x8, 55, }, + { 152, 3, 1, 0x20a0000000ull, 0x1eff8000000ull, { 23, 35, 0, 0, 0 }, 0x8, 56, }, + { 152, 3, 1, 0x20a8000000ull, 0x1eff8000000ull, { 23, 36, 0, 0, 0 }, 0x0, 57, }, + { 152, 3, 1, 0x20b0000000ull, 0x1eff8000000ull, { 23, 33, 0, 0, 0 }, 0x8, 58, }, + { 152, 3, 1, 0x20b8000000ull, 0x1eff8000000ull, { 23, 27, 0, 0, 0 }, 0x0, 59, }, + { 152, 7, 1, 0x0ull, 0x0ull, { 23, 13, 0, 0, 0 }, 0x0, 60, }, + { 152, 7, 1, 0x0ull, 0x0ull, { 13, 54, 0, 0, 0 }, 0x0, 60, }, + { 152, 7, 1, 0x0ull, 0x0ull, { 13, 24, 0, 0, 0 }, 0x0, 60, }, + { 153, 6, 1, 0xc000000000ull, 0x1e000100000ull, { 23, 69, 0, 0, 0 }, 0x0, 8, }, + { 154, 2, 1, 0xeca0000000ull, 0x1fff0000000ull, { 23, 24, 73, 0, 0 }, 0x0, 0, }, + { 155, 2, 1, 0xeea0000000ull, 0x1fff0000000ull, { 23, 24, 74, 0, 0 }, 0x0, 0, }, + { 165, 4, 0, 0x4000000000ull, 0x1e1f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 108, }, + { 165, 5, 0, 0x8000000ull, 0x1e3f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 224, }, + { 165, 2, 0, 0x8000000ull, 0x1eff8000000ull, { 64, 0, 0, 0, 0 }, 0x2, 306, }, + { 165, 3, 0, 0x8000000ull, 0x1eff8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 355, }, + { 165, 6, 0, 0x8000000ull, 0x1eff8000000ull, { 68, 0, 0, 0, 0 }, 0x0, 740, }, + { 165, 7, 0, 0x0ull, 0x0ull, { 64, 0, 0, 0, 0 }, 0x0, 5, }, + { 172, 1, 1, 0x10070000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 172, 1, 1, 0x10170000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, }, + { 175, 2, 1, 0xea00000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 710, }, + { 176, 2, 1, 0xf820000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 711, }, + { 177, 1, 1, 0x10400000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 61, }, + { 178, 1, 1, 0x10600000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 61, }, + { 179, 1, 1, 0x11400000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 180, 1, 1, 0x10450000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 62, }, + { 181, 1, 1, 0x10650000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 62, }, + { 182, 1, 1, 0x10470000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 183, 1, 1, 0x10670000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 184, 1, 1, 0x10520000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 216, }, + { 185, 1, 1, 0x10720000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 216, }, + { 186, 1, 1, 0x11520000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 216, }, + { 187, 2, 1, 0xe850000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 716, }, + { 188, 2, 1, 0xea70000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 189, 2, 1, 0xe810000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 716, }, + { 190, 2, 1, 0xea30000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 191, 2, 1, 0xead0000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 324, }, + { 192, 2, 1, 0xe230000000ull, 0x1ff30000000ull, { 23, 24, 25, 41, 0 }, 0x0, 63, }, + { 193, 2, 1, 0xe690000000ull, 0x1fff0000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, }, + { 195, 3, 1, 0x21c0000000ull, 0x1eff8000000ull, { 23, 25, 24, 0, 0 }, 0x0, 507, }, + { 195, 3, 1, 0x20c0000000ull, 0x1eff8000000ull, { 23, 25, 48, 0, 0 }, 0x0, 507, }, + { 195, 3, 0, 0x2188000000ull, 0x1eff8000000ull, { 25, 48, 0, 0, 0 }, 0x0, 508, }, + { 196, 2, 1, 0xe8b0000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 197, 2, 1, 0xe240000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 197, 2, 1, 0xee50000000ull, 0x1fff0000000ull, { 23, 24, 38, 0, 0 }, 0x0, 0, }, + { 198, 2, 1, 0xf040000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 198, 2, 1, 0xfc50000000ull, 0x1fff0000000ull, { 23, 24, 38, 0, 0 }, 0x0, 0, }, + { 199, 1, 1, 0x10680000000ull, 0x1ffe0000000ull, { 23, 24, 40, 25, 0 }, 0x0, 0, }, + { 200, 2, 1, 0xe220000000ull, 0x1fff0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 63, }, + { 200, 2, 1, 0xe630000000ull, 0x1fff0000000ull, { 23, 25, 42, 0, 0 }, 0x0, 63, }, + { 201, 2, 1, 0xf020000000ull, 0x1fff0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 63, }, + { 201, 2, 1, 0xf430000000ull, 0x1fff0000000ull, { 23, 25, 42, 0, 0 }, 0x0, 63, }, + { 202, 1, 1, 0x106c0000000ull, 0x1ffe0000000ull, { 23, 24, 40, 25, 0 }, 0x0, 0, }, + { 203, 1, 1, 0x10420000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 61, }, + { 204, 1, 1, 0x10620000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 61, }, + { 205, 1, 1, 0x11420000000ull, 0x1fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 206, 3, 0, 0x2048000000ull, 0x1eff8000000ull, { 25, 24, 0, 0, 0 }, 0x8, 325, }, + { 206, 3, 0, 0x2050000000ull, 0x1eff8000000ull, { 25, 24, 0, 0, 0 }, 0xc, 280, }, + { 206, 3, 0, 0x21a0000000ull, 0x1eff8000000ull, { 25, 0, 0, 0, 0 }, 0x8, 207, }, + { 207, 3, 0, 0x2060000000ull, 0x1eff8000000ull, { 25, 24, 0, 0, 0 }, 0x8, 150, }, + { 212, 4, 0, 0x40000000ull, 0x1e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x22c, 64, }, + { 213, 3, 0, 0x38000000ull, 0x1ee78000000ull, { 66, 0, 0, 0, 0 }, 0x8, 65, }, + { 214, 3, 0, 0x28000000ull, 0x1ee78000000ull, { 66, 0, 0, 0, 0 }, 0x0, 66, }, + { 223, 3, 1, 0xc708000000ull, 0x1ffc8000000ull, { 17, 24, 0, 0, 0 }, 0x0, 151, }, + { 224, 2, 1, 0xa600000000ull, 0x1ee04000000ull, { 23, 24, 44, 0, 0 }, 0x140, 0, }, + { 224, 2, 1, 0xf240000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 225, 1, 1, 0x10080000000ull, 0x1efe0000000ull, { 23, 24, 39, 25, 0 }, 0x0, 0, }, + { 226, 1, 1, 0x100c0000000ull, 0x1efe0000000ull, { 23, 24, 39, 25, 0 }, 0x0, 0, }, + { 227, 2, 1, 0xa400000000ull, 0x1ee00002000ull, { 23, 25, 75, 0, 0 }, 0x140, 10, }, + { 227, 2, 1, 0xf220000000ull, 0x1fff0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 63, }, + { 228, 2, 1, 0xac00000000ull, 0x1ee00000000ull, { 23, 24, 25, 43, 0 }, 0x0, 0, }, + { 233, 3, 0, 0x180000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 152, }, + { 234, 3, 0, 0x30000000ull, 0x1ee78000000ull, { 66, 0, 0, 0, 0 }, 0x8, 65, }, + { 236, 3, 1, 0x8c00000000ull, 0x1fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 67, }, + { 236, 3, 1, 0xac00000000ull, 0x1eff0000000ull, { 32, 24, 60, 0, 0 }, 0x0, 67, }, + { 237, 3, 1, 0x8c40000000ull, 0x1fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 67, }, + { 237, 3, 1, 0xac40000000ull, 0x1eff0000000ull, { 32, 24, 60, 0, 0 }, 0x0, 67, }, + { 238, 3, 1, 0x8c80000000ull, 0x1fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 67, }, + { 238, 3, 1, 0xac80000000ull, 0x1eff0000000ull, { 32, 24, 60, 0, 0 }, 0x0, 67, }, + { 239, 3, 1, 0x8cc0000000ull, 0x1fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 68, }, + { 239, 3, 1, 0xacc0000000ull, 0x1eff0000000ull, { 32, 24, 60, 0, 0 }, 0x0, 68, }, + { 240, 3, 1, 0xcec0000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 660, }, + { 240, 3, 1, 0xeec0000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 660, }, + { 241, 3, 1, 0xcc40000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 69, }, + { 241, 3, 1, 0xec40000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 69, }, + { 242, 3, 1, 0xccc0000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 69, }, + { 242, 3, 1, 0xecc0000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 69, }, + { 243, 3, 1, 0xcc00000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 69, }, + { 243, 3, 1, 0xec00000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 69, }, + { 244, 3, 1, 0xcc80000000ull, 0x1fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 69, }, + { 244, 3, 1, 0xec80000000ull, 0x1eff0000000ull, { 32, 18, 60, 0, 0 }, 0x0, 69, }, + { 245, 1, 1, 0x10028000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 245, 1, 1, 0x10020000000ull, 0x1eff8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 0, }, + { 245, 1, 1, 0x10128000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, }, + { 246, 3, 0, 0x20000000ull, 0x1ee78000000ull, { 66, 0, 0, 0, 0 }, 0x0, 70, }, + { 247, 2, 1, 0xa0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, }, + { 248, 2, 1, 0xa8000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, }, + { 249, 2, 1, 0xb0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, }, + { 250, 3, 0, 0x198000000ull, 0x1eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 306, }, + { 251, 3, 1, 0x20f8000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 71, }, + { 252, 2, 2, 0xa000000000ull, 0x1fe00003000ull, { 21, 22, 25, 75, 0 }, 0x0, 477, }, + { 252, 2, 2, 0xa000000000ull, 0x1fe00003000ull, { 22, 21, 25, 75, 0 }, 0x40, 478, }, + { 253, 3, 1, 0x20d0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 72, }, + { 254, 2, 2, 0xa000002000ull, 0x1fe00003000ull, { 21, 22, 25, 0, 0 }, 0x0, 477, }, + { 254, 2, 2, 0xa000002000ull, 0x1fe00003000ull, { 22, 21, 25, 0, 0 }, 0x40, 478, }, + { 255, 3, 1, 0x20f0000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 71, }, + { 257, 3, 1, 0x20d8000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 73, }, + { 261, 2, 1, 0xe840000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 301, }, + { 262, 2, 1, 0xea40000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 301, }, + { 263, 2, 1, 0xf840000000ull, 0x1fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 301, }, + { 271, 3, 1, 0x8208000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 74, }, + { 272, 3, 1, 0x8248000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 74, }, + { 273, 3, 1, 0x8288000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 74, }, + { 274, 3, 1, 0x82c8000000ull, 0x1fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 74, }, + { 276, 5, 1, 0x1d000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 302, }, + { 276, 5, 1, 0x1d000000000ull, 0x1fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 353, }, + { 277, 5, 1, 0x1d000000000ull, 0x1fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 303, }, + { 278, 1, 1, 0x10078000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, + { 278, 1, 1, 0x10178000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 0, }, + { 281, 2, 1, 0x80000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, }, + { 282, 2, 1, 0x88000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, }, + { 283, 2, 1, 0x90000000ull, 0x1eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 0, }, +}; + +static const char dis_table[] = { +0xa0, 0xc2, 0x60, 0xa0, 0x2c, 0x80, 0xa0, 0x2a, 0x80, 0xa0, 0x1a, 0x70, +0x98, 0xb0, 0x01, 0x40, 0x90, 0x50, 0x90, 0x28, 0x24, 0x20, 0x28, 0x24, +0x20, 0x20, 0x90, 0x28, 0x24, 0x20, 0x18, 0x24, 0x20, 0x10, 0x90, 0x50, +0x90, 0x28, 0x24, 0x20, 0x00, 0x24, 0x1f, 0xf8, 0x90, 0x28, 0x24, 0x1f, +0xf0, 0x24, 0x1f, 0xe8, 0xa8, 0x0b, 0x28, 0x15, 0x00, 0x97, 0x00, 0x95, +0xa8, 0x9a, 0x98, 0x05, 0x18, 0x90, 0xf8, 0x90, 0x80, 0x90, 0x40, 0x80, +0xa4, 0x06, 0x50, 0x37, 0x13, 0x80, 0xa4, 0x2d, 0x18, 0x33, 0xfa, 0x90, +0x50, 0x90, 0x28, 0x80, 0x35, 0xac, 0x80, 0x31, 0x08, 0x81, 0x34, 0xec, +0x90, 0xe0, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x00, 0x00, 0x33, 0xdb, 0xa4, +0x1e, 0xc0, 0x33, 0xd9, 0x90, 0x38, 0xa4, 0x26, 0xd0, 0x34, 0xcf, 0xa4, +0x2d, 0xe0, 0x35, 0xb6, 0x90, 0x70, 0x90, 0x38, 0xa4, 0x2e, 0xd0, 0x35, +0xde, 0xa4, 0x28, 0xd8, 0x35, 0x23, 0x80, 0xa4, 0x2e, 0xc8, 0x35, 0xdd, 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385, 0 }, +{ 0x4, 383, 1 }, +{ 0x1, 384, 0 }, +{ 0x2, 383, 0 }, +{ 0x1, 383, 0 }, +{ 0x4, 382, 0 }, +{ 0x2, 382, 0 }, +{ 0x1, 382, 0 }, +{ 0x4, 381, 0 }, +{ 0x2, 381, 0 }, +{ 0x1, 381, 0 }, +{ 0x4, 380, 0 }, +{ 0x2, 380, 0 }, +{ 0x1, 380, 0 }, +{ 0x4, 379, 0 }, +{ 0x2, 379, 0 }, +{ 0x1, 379, 0 }, +{ 0x2, 378, 0 }, +{ 0x1, 378, 0 }, +{ 0x2, 377, 0 }, +{ 0x1, 377, 0 }, +{ 0x2, 376, 0 }, +{ 0x1, 376, 0 }, +{ 0x1, 374, 0 }, +{ 0x2, 372, 1 }, +{ 0x1, 373, 0 }, +{ 0x12, 372, 1 }, +{ 0x11, 373, 0 }, +{ 0xa, 372, 1 }, +{ 0x9, 373, 0 }, +{ 0x1a, 372, 1 }, +{ 0x7, 373, 0 }, +{ 0x6, 372, 1 }, +{ 0x5, 373, 0 }, +{ 0x5, 372, 1 }, +{ 0x12, 373, 0 }, +{ 0xd, 372, 1 }, +{ 0xe, 373, 0 }, +{ 0x3, 372, 1 }, +{ 0xa, 373, 0 }, +{ 0x2, 369, 1 }, +{ 0x1, 370, 0 }, +{ 0x12, 369, 1 }, +{ 0x11, 370, 0 }, +{ 0xa, 369, 1 }, +{ 0x9, 370, 0 }, +{ 0x1a, 369, 1 }, +{ 0x7, 370, 0 }, +{ 0x6, 369, 1 }, +{ 0x5, 370, 0 }, +{ 0x5, 369, 1 }, +{ 0x12, 370, 0 }, +{ 0xd, 369, 1 }, +{ 0xe, 370, 0 }, +{ 0x3, 369, 1 }, +{ 0xa, 370, 0 }, +{ 0x1, 368, 0 }, +{ 0x1, 363, 0 }, +{ 0x1, 362, 0 }, +{ 0x1, 361, 0 }, +{ 0x1, 360, 0 }, +{ 0x2, 359, 0 }, +{ 0x1, 359, 0 }, +{ 0x2, 358, 0 }, +{ 0x1, 358, 0 }, +{ 0x2, 357, 0 }, +{ 0x1, 357, 0 }, +{ 0x2, 356, 0 }, +{ 0x1, 356, 0 }, +{ 0x2, 355, 0 }, +{ 0x1, 355, 0 }, +{ 0x2, 354, 0 }, +{ 0x1, 354, 0 }, +{ 0x2, 353, 0 }, +{ 0x1, 353, 0 }, +{ 0x2, 352, 0 }, +{ 0x1, 352, 0 }, +{ 0x1, 351, 0 }, +{ 0x3, 351, 0 }, +{ 0x1, 350, 0 }, +{ 0x3, 350, 0 }, +{ 0x8, 349, 0 }, +{ 0x18, 349, 0 }, +{ 0x4, 349, 0 }, +{ 0xc, 349, 0 }, +{ 0x2, 349, 0 }, +{ 0x1, 349, 0 }, +{ 0x8, 348, 0 }, +{ 0x18, 348, 0 }, +{ 0x4, 348, 0 }, +{ 0xc, 348, 0 }, +{ 0x2, 348, 0 }, +{ 0x1, 348, 0 }, +{ 0x4, 347, 0 }, +{ 0xc, 347, 0 }, +{ 0x2, 347, 0 }, +{ 0x1, 347, 0 }, +{ 0x4, 346, 0 }, +{ 0xc, 346, 0 }, +{ 0x2, 346, 0 }, +{ 0x1, 346, 0 }, +{ 0x4, 345, 0 }, +{ 0xc, 345, 0 }, +{ 0x2, 345, 0 }, +{ 0x1, 345, 0 }, +{ 0x4, 344, 0 }, +{ 0xc, 344, 0 }, +{ 0x2, 344, 0 }, +{ 0x1, 344, 0 }, +{ 0x4, 343, 0 }, +{ 0xc, 343, 0 }, +{ 0x2, 343, 0 }, +{ 0x1, 343, 0 }, +{ 0x4, 342, 0 }, +{ 0xc, 342, 0 }, +{ 0x2, 342, 0 }, +{ 0x1, 342, 0 }, +{ 0x1, 341, 0 }, +{ 0x1, 339, 0 }, +{ 0x2, 338, 0 }, +{ 0x1, 338, 0 }, +{ 0x1, 336, 0 }, +{ 0x1, 335, 0 }, +{ 0x1, 334, 0 }, +{ 0x8, 332, 0 }, +{ 0x4, 332, 0 }, +{ 0x2, 332, 0 }, +{ 0x1, 332, 0 }, +{ 0x1, 331, 0 }, +{ 0x1, 330, 0 }, +{ 0x1, 329, 0 }, +{ 0x2, 328, 0 }, +{ 0x1, 328, 0 }, +{ 0x2, 326, 0 }, +{ 0x1, 326, 0 }, +{ 0x1, 325, 0 }, +{ 0x1, 324, 0 }, +{ 0x8, 323, 0 }, +{ 0x4, 323, 0 }, +{ 0x2, 323, 0 }, +{ 0x1, 323, 0 }, +{ 0x8, 322, 0 }, +{ 0x4, 322, 0 }, +{ 0x2, 322, 0 }, +{ 0x1, 322, 0 }, +{ 0x1, 321, 0 }, +{ 0x2, 320, 0 }, +{ 0x1, 320, 0 }, +{ 0x2, 319, 0 }, +{ 0x1, 319, 0 }, +{ 0x2, 318, 0 }, +{ 0x1, 318, 0 }, +{ 0x2, 317, 0 }, +{ 0x1, 317, 0 }, +{ 0x1, 316, 0 }, +{ 0x1, 315, 0 }, +{ 0x1, 314, 0 }, +{ 0x1, 313, 0 }, +{ 0x1, 312, 0 }, +{ 0x1, 311, 0 }, +{ 0x2, 308, 0 }, +{ 0x1, 308, 0 }, +{ 0x1, 307, 0 }, +{ 0x2, 306, 0 }, +{ 0x1, 306, 0 }, +{ 0x2, 305, 0 }, +{ 0x1, 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46, 0 }, +{ 0x5, 45, 0 }, +{ 0x3, 45, 0 }, +{ 0x3, 44, 0 }, +{ 0x2, 43, 0 }, +{ 0x1, 43, 0 }, +{ 0x8, 42, 0 }, +{ 0x18, 42, 0 }, +{ 0x4, 42, 0 }, +{ 0xc, 42, 0 }, +{ 0x2, 42, 0 }, +{ 0x6, 42, 0 }, +{ 0x1, 42, 0 }, +{ 0x3, 42, 0 }, +{ 0x4, 41, 0 }, +{ 0xc, 41, 0 }, +{ 0xa, 41, 0 }, +{ 0x1a, 41, 0 }, +{ 0x6, 41, 0 }, +{ 0xe, 41, 0 }, +{ 0x1, 41, 0 }, +{ 0x3, 41, 0 }, +{ 0x51, 39, 0 }, +{ 0xd1, 39, 1 }, +{ 0xc, 58, 1 }, +{ 0x6, 61, 1 }, +{ 0x3, 63, 1 }, +{ 0x3, 64, 0 }, +{ 0x31, 39, 1 }, +{ 0x11, 40, 0 }, +{ 0x71, 39, 1 }, +{ 0x31, 40, 1 }, +{ 0x4, 58, 1 }, +{ 0x2, 61, 1 }, +{ 0x1, 63, 1 }, +{ 0x1, 64, 0 }, +{ 0x29, 39, 0 }, +{ 0x69, 39, 1 }, +{ 0x28, 58, 1 }, +{ 0x5, 62, 0 }, +{ 0x19, 39, 1 }, +{ 0x9, 40, 0 }, +{ 0x39, 39, 1 }, +{ 0x19, 40, 1 }, +{ 0x5, 58, 1 }, +{ 0xa, 62, 0 }, +{ 0x15, 39, 0 }, +{ 0x35, 39, 1 }, +{ 0x3, 80, 1 }, +{ 0x3, 81, 1 }, +{ 0x3, 82, 1 }, +{ 0x3, 83, 0 }, +{ 0xd, 39, 1 }, +{ 0x5, 40, 0 }, +{ 0x1d, 39, 1 }, +{ 0xd, 40, 1 }, +{ 0x1, 80, 1 }, +{ 0x1, 81, 1 }, +{ 0x1, 82, 1 }, +{ 0x1, 83, 0 }, +{ 0xb, 39, 0 }, +{ 0x1b, 39, 1 }, +{ 0x14, 75, 1 }, +{ 0x5, 79, 0 }, +{ 0x7, 39, 1 }, +{ 0x3, 40, 0 }, +{ 0xf, 39, 1 }, +{ 0x7, 40, 1 }, +{ 0x5, 75, 1 }, +{ 0xa, 79, 0 }, +{ 0x51, 37, 1 }, +{ 0x50, 37, 0 }, +{ 0xd1, 37, 1 }, +{ 0xd0, 37, 0 }, +{ 0x31, 37, 1 }, +{ 0x30, 37, 1 }, +{ 0x11, 38, 1 }, +{ 0x10, 38, 0 }, +{ 0x71, 37, 1 }, +{ 0x70, 37, 1 }, +{ 0x31, 38, 1 }, +{ 0x30, 38, 0 }, +{ 0x29, 37, 1 }, +{ 0x28, 37, 0 }, +{ 0x69, 37, 1 }, +{ 0x68, 37, 0 }, +{ 0x19, 37, 1 }, +{ 0x18, 37, 1 }, +{ 0x9, 38, 1 }, +{ 0x8, 38, 0 }, +{ 0x39, 37, 1 }, +{ 0x38, 37, 1 }, +{ 0x19, 38, 1 }, +{ 0x18, 38, 0 }, +{ 0x15, 37, 1 }, +{ 0x14, 37, 0 }, +{ 0x35, 37, 1 }, +{ 0x34, 37, 0 }, +{ 0xd, 37, 1 }, +{ 0xc, 37, 1 }, +{ 0x5, 38, 1 }, +{ 0x4, 38, 0 }, +{ 0x1d, 37, 1 }, +{ 0x1c, 37, 1 }, +{ 0xd, 38, 1 }, +{ 0xc, 38, 0 }, +{ 0xb, 37, 1 }, +{ 0xa, 37, 0 }, +{ 0x1b, 37, 1 }, +{ 0x1a, 37, 0 }, +{ 0x7, 37, 1 }, +{ 0x6, 37, 1 }, +{ 0x3, 38, 1 }, +{ 0x2, 38, 0 }, +{ 0xf, 37, 1 }, +{ 0xe, 37, 1 }, +{ 0x7, 38, 1 }, +{ 0x6, 38, 0 }, +{ 0x8, 36, 0 }, +{ 0x18, 36, 0 }, +{ 0x2, 36, 1 }, +{ 0xc, 36, 0 }, +{ 0x1, 36, 1 }, +{ 0x4, 36, 0 }, +{ 0x1, 32, 1 }, +{ 0x1, 33, 1 }, +{ 0x1, 34, 0 }, +{ 0x1, 31, 0 }, +{ 0x1, 30, 0 }, +{ 0x51, 28, 0 }, +{ 0xd1, 28, 0 }, +{ 0x31, 28, 1 }, +{ 0x11, 29, 0 }, +{ 0x71, 28, 1 }, +{ 0x31, 29, 0 }, +{ 0x29, 28, 0 }, +{ 0x69, 28, 0 }, +{ 0x19, 28, 1 }, +{ 0x9, 29, 0 }, +{ 0x39, 28, 1 }, +{ 0x19, 29, 0 }, +{ 0x15, 28, 0 }, +{ 0x35, 28, 0 }, +{ 0xd, 28, 1 }, +{ 0x5, 29, 0 }, +{ 0x1d, 28, 1 }, +{ 0xd, 29, 0 }, +{ 0xb, 28, 0 }, +{ 0x1b, 28, 0 }, +{ 0x7, 28, 1 }, +{ 0x3, 29, 0 }, +{ 0xf, 28, 1 }, +{ 0x7, 29, 0 }, +{ 0xa2, 26, 0 }, +{ 0x1a2, 26, 0 }, +{ 0x62, 26, 1 }, +{ 0x22, 27, 0 }, +{ 0xe2, 26, 1 }, +{ 0x62, 27, 0 }, +{ 0x52, 26, 0 }, +{ 0xd2, 26, 0 }, +{ 0x32, 26, 1 }, +{ 0x12, 27, 0 }, +{ 0x72, 26, 1 }, +{ 0x32, 27, 0 }, +{ 0x2a, 26, 0 }, +{ 0x6a, 26, 0 }, +{ 0x1a, 26, 1 }, +{ 0xa, 27, 0 }, +{ 0x3a, 26, 1 }, +{ 0x1a, 27, 0 }, +{ 0x16, 26, 0 }, +{ 0x36, 26, 0 }, +{ 0xe, 26, 1 }, +{ 0x6, 27, 0 }, +{ 0x1e, 26, 1 }, +{ 0xe, 27, 0 }, +{ 0x51, 26, 0 }, +{ 0xd1, 26, 0 }, +{ 0x31, 26, 1 }, +{ 0x11, 27, 0 }, +{ 0x71, 26, 1 }, +{ 0x31, 27, 0 }, +{ 0x29, 26, 0 }, +{ 0x69, 26, 0 }, +{ 0x19, 26, 1 }, +{ 0x9, 27, 0 }, +{ 0x39, 26, 1 }, +{ 0x19, 27, 0 }, +{ 0x15, 26, 0 }, +{ 0x35, 26, 0 }, +{ 0xd, 26, 1 }, +{ 0x5, 27, 0 }, +{ 0x1d, 26, 1 }, +{ 0xd, 27, 0 }, +{ 0xb, 26, 0 }, +{ 0x1b, 26, 0 }, +{ 0x7, 26, 1 }, +{ 0x3, 27, 0 }, +{ 0xf, 26, 1 }, +{ 0x7, 27, 0 }, +{ 0x51, 24, 0 }, +{ 0xd1, 24, 0 }, +{ 0x31, 24, 1 }, +{ 0x11, 25, 0 }, +{ 0x71, 24, 1 }, +{ 0x31, 25, 0 }, +{ 0x29, 24, 0 }, +{ 0x69, 24, 0 }, +{ 0x19, 24, 1 }, +{ 0x9, 25, 0 }, +{ 0x39, 24, 1 }, +{ 0x19, 25, 0 }, +{ 0x15, 24, 0 }, +{ 0x35, 24, 0 }, +{ 0xd, 24, 1 }, +{ 0x5, 25, 0 }, +{ 0x1d, 24, 1 }, +{ 0xd, 25, 0 }, +{ 0xb, 24, 0 }, +{ 0x1b, 24, 0 }, +{ 0x7, 24, 1 }, +{ 0x3, 25, 0 }, +{ 0xf, 24, 1 }, +{ 0x7, 25, 0 }, +{ 0xa2, 22, 0 }, +{ 0x1a2, 22, 0 }, +{ 0x62, 22, 1 }, +{ 0x22, 23, 0 }, +{ 0xe2, 22, 1 }, +{ 0x62, 23, 0 }, +{ 0x52, 22, 0 }, +{ 0xd2, 22, 0 }, +{ 0x32, 22, 1 }, +{ 0x12, 23, 0 }, +{ 0x72, 22, 1 }, +{ 0x32, 23, 0 }, +{ 0x2a, 22, 0 }, +{ 0x6a, 22, 0 }, +{ 0x1a, 22, 1 }, +{ 0xa, 23, 0 }, +{ 0x3a, 22, 1 }, +{ 0x1a, 23, 0 }, +{ 0x16, 22, 0 }, +{ 0x36, 22, 0 }, +{ 0xe, 22, 1 }, +{ 0x6, 23, 0 }, +{ 0x1e, 22, 1 }, +{ 0xe, 23, 0 }, +{ 0x51, 22, 0 }, +{ 0xd1, 22, 0 }, +{ 0x31, 22, 1 }, +{ 0x11, 23, 0 }, +{ 0x71, 22, 1 }, +{ 0x31, 23, 0 }, +{ 0x29, 22, 0 }, +{ 0x69, 22, 0 }, +{ 0x19, 22, 1 }, +{ 0x9, 23, 0 }, +{ 0x39, 22, 1 }, +{ 0x19, 23, 0 }, +{ 0x15, 22, 0 }, +{ 0x35, 22, 0 }, +{ 0xd, 22, 1 }, +{ 0x5, 23, 0 }, +{ 0x1d, 22, 1 }, +{ 0xd, 23, 0 }, +{ 0xb, 22, 0 }, +{ 0x1b, 22, 0 }, +{ 0x7, 22, 1 }, +{ 0x3, 23, 0 }, +{ 0xf, 22, 1 }, +{ 0x7, 23, 0 }, +{ 0x51, 20, 1 }, +{ 0x50, 20, 0 }, +{ 0xd1, 20, 1 }, +{ 0xd0, 20, 0 }, +{ 0x31, 20, 1 }, +{ 0x30, 20, 1 }, +{ 0x11, 21, 1 }, +{ 0x10, 21, 0 }, +{ 0x71, 20, 1 }, +{ 0x70, 20, 1 }, +{ 0x31, 21, 1 }, +{ 0x30, 21, 0 }, +{ 0x29, 20, 1 }, +{ 0x28, 20, 0 }, +{ 0x69, 20, 1 }, +{ 0x68, 20, 0 }, +{ 0x19, 20, 1 }, +{ 0x18, 20, 1 }, +{ 0x9, 21, 1 }, +{ 0x8, 21, 0 }, +{ 0x39, 20, 1 }, +{ 0x38, 20, 1 }, +{ 0x19, 21, 1 }, +{ 0x18, 21, 0 }, +{ 0x15, 20, 1 }, +{ 0x14, 20, 0 }, +{ 0x35, 20, 1 }, +{ 0x34, 20, 0 }, +{ 0xd, 20, 1 }, +{ 0xc, 20, 1 }, +{ 0x5, 21, 1 }, +{ 0x4, 21, 0 }, +{ 0x1d, 20, 1 }, +{ 0x1c, 20, 1 }, +{ 0xd, 21, 1 }, +{ 0xc, 21, 0 }, +{ 0xb, 20, 1 }, +{ 0xa, 20, 0 }, +{ 0x1b, 20, 1 }, +{ 0x1a, 20, 0 }, +{ 0x7, 20, 1 }, +{ 0x6, 20, 1 }, +{ 0x3, 21, 1 }, +{ 0x2, 21, 0 }, +{ 0xf, 20, 1 }, +{ 0xe, 20, 1 }, +{ 0x7, 21, 1 }, +{ 0x6, 21, 0 }, +{ 0x8, 19, 0 }, +{ 0x18, 19, 0 }, +{ 0x2, 19, 1 }, +{ 0xc, 19, 0 }, +{ 0x1, 19, 1 }, +{ 0x4, 19, 0 }, +{ 0x51, 17, 0 }, +{ 0xd1, 17, 0 }, +{ 0x31, 17, 1 }, +{ 0x11, 18, 0 }, +{ 0x71, 17, 1 }, +{ 0x31, 18, 0 }, +{ 0x29, 17, 0 }, +{ 0x69, 17, 0 }, +{ 0x19, 17, 1 }, +{ 0x9, 18, 0 }, +{ 0x39, 17, 1 }, +{ 0x19, 18, 0 }, +{ 0x15, 17, 0 }, +{ 0x35, 17, 0 }, +{ 0xd, 17, 1 }, +{ 0x5, 18, 0 }, +{ 0x1d, 17, 1 }, +{ 0xd, 18, 0 }, +{ 0xb, 17, 0 }, +{ 0x1b, 17, 0 }, +{ 0x7, 17, 1 }, +{ 0x3, 18, 0 }, +{ 0xf, 17, 1 }, +{ 0x7, 18, 0 }, +{ 0x51, 15, 0 }, +{ 0xd1, 15, 0 }, +{ 0x31, 15, 1 }, +{ 0x11, 16, 0 }, +{ 0x71, 15, 1 }, +{ 0x31, 16, 0 }, +{ 0x29, 15, 0 }, +{ 0x69, 15, 0 }, +{ 0x19, 15, 1 }, +{ 0x9, 16, 0 }, +{ 0x39, 15, 1 }, +{ 0x19, 16, 0 }, +{ 0x15, 15, 0 }, +{ 0x35, 15, 0 }, +{ 0xd, 15, 1 }, +{ 0x5, 16, 0 }, +{ 0x1d, 15, 1 }, +{ 0xd, 16, 0 }, +{ 0xb, 15, 0 }, +{ 0x1b, 15, 0 }, +{ 0x7, 15, 1 }, +{ 0x3, 16, 0 }, +{ 0xf, 15, 1 }, +{ 0x7, 16, 0 }, +{ 0x288, 13, 0 }, +{ 0x688, 13, 0 }, +{ 0x188, 13, 1 }, +{ 0x88, 14, 0 }, +{ 0x388, 13, 1 }, +{ 0x188, 14, 0 }, +{ 0x148, 13, 0 }, +{ 0x348, 13, 0 }, +{ 0xc8, 13, 1 }, +{ 0x48, 14, 0 }, +{ 0x1c8, 13, 1 }, +{ 0xc8, 14, 0 }, +{ 0xa8, 13, 0 }, +{ 0x1a8, 13, 0 }, +{ 0x68, 13, 1 }, +{ 0x28, 14, 0 }, +{ 0xe8, 13, 1 }, +{ 0x68, 14, 0 }, +{ 0x58, 13, 0 }, +{ 0xd8, 13, 0 }, +{ 0x38, 13, 1 }, +{ 0x18, 14, 0 }, +{ 0x78, 13, 1 }, +{ 0x38, 14, 0 }, +{ 0x51, 13, 1 }, +{ 0xa0, 13, 0 }, +{ 0xd1, 13, 1 }, +{ 0x1a0, 13, 0 }, +{ 0x31, 13, 1 }, +{ 0x60, 13, 1 }, +{ 0x11, 14, 1 }, +{ 0x20, 14, 0 }, +{ 0x71, 13, 1 }, +{ 0xe0, 13, 1 }, +{ 0x31, 14, 1 }, +{ 0x60, 14, 0 }, +{ 0x29, 13, 1 }, +{ 0x50, 13, 0 }, +{ 0x69, 13, 1 }, +{ 0xd0, 13, 0 }, +{ 0x19, 13, 1 }, +{ 0x30, 13, 1 }, +{ 0x9, 14, 1 }, +{ 0x10, 14, 0 }, +{ 0x39, 13, 1 }, +{ 0x70, 13, 1 }, +{ 0x19, 14, 1 }, +{ 0x30, 14, 0 }, +{ 0x15, 13, 1 }, +{ 0x14, 13, 0 }, +{ 0x35, 13, 1 }, +{ 0x34, 13, 0 }, +{ 0xd, 13, 1 }, +{ 0xc, 13, 1 }, +{ 0x5, 14, 1 }, +{ 0x4, 14, 0 }, +{ 0x1d, 13, 1 }, +{ 0x1c, 13, 1 }, +{ 0xd, 14, 1 }, +{ 0xc, 14, 0 }, +{ 0xb, 13, 1 }, +{ 0xa, 13, 0 }, +{ 0x1b, 13, 1 }, +{ 0x1a, 13, 0 }, +{ 0x7, 13, 1 }, +{ 0x6, 13, 1 }, +{ 0x3, 14, 1 }, +{ 0x2, 14, 0 }, +{ 0xf, 13, 1 }, +{ 0xe, 13, 1 }, +{ 0x7, 14, 1 }, +{ 0x6, 14, 0 }, +{ 0x8, 12, 0 }, +{ 0x18, 12, 0 }, +{ 0x2, 12, 1 }, +{ 0xc, 12, 0 }, +{ 0x1, 12, 1 }, +{ 0x4, 12, 0 }, +{ 0x1, 11, 0 }, +{ 0x1, 10, 0 }, +{ 0x1, 9, 0 }, +{ 0x1, 8, 0 }, +{ 0x1, 7, 0 }, +{ 0x1, 6, 0 }, +{ 0x1, 5, 0 }, +{ 0x1, 4, 0 }, +{ 0x1, 3, 0 }, +{ 0x1, 1, 0 }, +{ 0x1, 0, 0 }, +}; + diff --git a/opcodes/ia64-asmtab.h b/opcodes/ia64-asmtab.h new file mode 100644 index 0000000..2bbdee3 --- /dev/null +++ b/opcodes/ia64-asmtab.h @@ -0,0 +1,145 @@ +/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables. + Copyright (C) 1999 Free Software Foundation, Inc. + Contributed by Bob Manson of Cygnus Support + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef IA64_ASMTAB_H +#define IA64_ASMTAB_H + +#include "opcode/ia64.h" + +/* The primary opcode table is made up of the following: */ +struct ia64_main_table +{ + /* The entry in the string table that corresponds to the name of this + opcode. */ + unsigned short name_index; + + /* The type of opcode; corresponds to the TYPE field in + struct ia64_opcode. */ + unsigned char opcode_type; + + /* The number of outputs for this opcode. */ + unsigned char num_outputs; + + /* The base insn value for this opcode. It may be modified by completers. */ + ia64_insn opcode; + + /* The mask of valid bits in OPCODE. Zeros indicate operand fields. */ + ia64_insn mask; + + /* The operands of this instruction. Corresponds to the OPERANDS field + in struct ia64_opcode. */ + unsigned char operands[5]; + + /* The flags for this instruction. Corresponds to the FLAGS field in + struct ia64_opcode. */ + short flags; + + /* The tree of completers for this instruction; this is an offset into + completer_table. */ + short completers; +}; + +/* Each instruction has a set of possible "completers", or additional + suffixes that can alter the instruction's behavior, and which has + potentially different dependencies. + + The completer entries modify certain bits in the instruction opcode. + Which bits are to be modified are marked by the BITS, MASK and + OFFSET fields. The completer entry may also note dependencies for the + opcode. + + These completers are arranged in a DAG; the pointers are indexes + into the completer_table array. The completer DAG is searched by + find_completer () and ia64_find_matching_opcode (). + + Note that each completer needs to be applied in turn, so that if we + have the instruction + cmp.lt.unc + the completer entries for both "lt" and "unc" would need to be applied + to the opcode's value. + + Some instructions do not require any completers; these contain an + empty completer entry. Instructions that require a completer do + not contain an empty entry. + + Terminal completers (those completers that validly complete an + instruction) are marked by having the TERMINAL_COMPLETER flag set. + + Only dependencies listed in the terminal completer for an opcode are + considered to apply to that opcode instance. */ + +struct ia64_completer_table +{ + /* The bit value that this completer sets. */ + unsigned int bits; + + /* And its mask. 1s are bits that are to be modified in the + instruction. */ + unsigned int mask; + + /* The entry in the string table that corresponds to the name of this + completer. */ + unsigned short name_index; + + /* An alternative completer, or -1 if this is the end of the chain. */ + short alternative; + + /* A pointer to the DAG of completers that can potentially follow + this one, or -1. */ + short subentries; + + /* The bit offset in the instruction where BITS and MASK should be + applied. */ + unsigned char offset : 7; + + unsigned char terminal_completer : 1; + + /* Index into the dependency list table */ + short dependencies; +}; + +/* This contains sufficient information for the disassembler to resolve + the complete name of the original instruction. */ +struct ia64_dis_names +{ + /* COMPLETER_INDEX represents the tree of completers that make up + the instruction. The LSB represents the top of the tree for the + specified instruction. + + A 0 bit indicates to go to the next alternate completer via the + alternative field; a 1 bit indicates that the current completer + is part of the instruction, and to go down the subentries index. + We know we've reached the final completer when we run out of 1 + bits. + + There is always at least one 1 bit. */ + unsigned int completer_index : 20; + + /* The index in the main_table[] array for the instruction. */ + unsigned short insn_index : 11; + + /* If set, the next entry in this table is an alternate possibility + for this instruction encoding. Which one to use is determined by + the instruction type and other factors (see opcode_verify ()). */ + unsigned int next_flag : 1; +}; + +#endif diff --git a/opcodes/ia64-dis.c b/opcodes/ia64-dis.c new file mode 100644 index 0000000..7a68597 --- /dev/null +++ b/opcodes/ia64-dis.c @@ -0,0 +1,264 @@ +/* ia64-dis.c -- Disassemble ia64 instructions + Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include +#include + +#include "dis-asm.h" +#include "opcode/ia64.h" + +#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0]))) + +/* Disassemble ia64 instruction. */ + +/* Return the instruction type for OPCODE found in unit UNIT. */ + +static enum ia64_insn_type +unit_to_type (ia64_insn opcode, enum ia64_unit unit) +{ + enum ia64_insn_type type; + int op; + + op = IA64_OP (opcode); + + if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M)) + { + type = IA64_TYPE_A; + } + else + { + switch (unit) + { + case IA64_UNIT_I: + type = IA64_TYPE_I; break; + case IA64_UNIT_M: + type = IA64_TYPE_M; break; + case IA64_UNIT_B: + type = IA64_TYPE_B; break; + case IA64_UNIT_F: + type = IA64_TYPE_F; break; + case IA64_UNIT_L: + case IA64_UNIT_X: + type = IA64_TYPE_X; break; + default: + type = -1; + } + } + return type; +} + +int +print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info) +{ + ia64_insn t0, t1, slot[3], template, s_bit, insn; + int slotnum, j, status, need_comma, retval, slot_multiplier; + const struct ia64_operand *odesc; + const struct ia64_opcode *idesc; + const char *err, *str, *tname; + BFD_HOST_U_64_BIT value; + bfd_byte bundle[16]; + enum ia64_unit unit; + char regname[16]; + + if (info->bytes_per_line == 0) + info->bytes_per_line = 6; + info->display_endian = info->endian; + + slot_multiplier = info->bytes_per_line; + retval = slot_multiplier; + + slotnum = (((long) memaddr) & 0xf) / slot_multiplier; + if (slotnum > 2) + return -1; + + memaddr -= (memaddr & 0xf); + status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + /* bundles are always in little-endian byte order */ + t0 = bfd_getl64 (bundle); + t1 = bfd_getl64 (bundle + 8); + s_bit = t0 & 1; + template = (t0 >> 1) & 0xf; + slot[0] = (t0 >> 5) & 0x1ffffffffffLL; + slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); + slot[2] = (t1 >> 23) & 0x1ffffffffffLL; + + tname = ia64_templ_desc[template].name; + if (slotnum == 0) + (*info->fprintf_func) (info->stream, "[%s] ", tname); + else + (*info->fprintf_func) (info->stream, " ", tname); + + unit = ia64_templ_desc[template].exec_unit[slotnum]; + + if (template == 2 && slotnum == 1) + { + /* skip L slot in MLI template: */ + slotnum = 2; + retval += slot_multiplier; + } + + insn = slot[slotnum]; + + if (unit == IA64_UNIT_NIL) + goto decoding_failed; + + idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit)); + if (idesc == NULL) + goto decoding_failed; + + /* print predicate, if any: */ + + if ((idesc->flags & IA64_OPCODE_NO_PRED) + || (insn & 0x3f) == 0) + (*info->fprintf_func) (info->stream, " "); + else + (*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f)); + + /* now the actual instruction: */ + + (*info->fprintf_func) (info->stream, "%s", idesc->name); + if (idesc->operands[0]) + (*info->fprintf_func) (info->stream, " "); + + need_comma = 0; + for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j) + { + odesc = elf64_ia64_operands + idesc->operands[j]; + + if (need_comma) + (*info->fprintf_func) (info->stream, ","); + + if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) + { + /* special case of 64 bit immediate load: */ + value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7) + | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21) + | (slot[1] << 22) | (((insn >> 36) & 0x1) << 63); + } + else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) + { + /* 62-bit immediate for nop.x/break.x */ + value = ((slot[1] & 0x1ffffffffffLL) << 21) + | (((insn >> 36) & 0x1) << 20) + | ((insn >> 6) & 0xfffff); + } + else + { + err = (*odesc->extract) (odesc, insn, &value); + if (err) + { + (*info->fprintf_func) (info->stream, "%s", err); + goto done; + } + } + + switch (odesc->class) + { + case IA64_OPND_CLASS_CST: + (*info->fprintf_func) (info->stream, "%s", odesc->str); + break; + + case IA64_OPND_CLASS_REG: + if (odesc->str[0] == 'a' && odesc->str[1] == 'r') + { + switch (value) + { + case 0: case 1: case 2: case 3: + case 4: case 5: case 6: case 7: + sprintf (regname, "ar.k%u", (unsigned int) value); + break; + case 16: strcpy (regname, "ar.rsc"); break; + case 17: strcpy (regname, "ar.bsp"); break; + case 18: strcpy (regname, "ar.bspstore"); break; + case 19: strcpy (regname, "ar.rnat"); break; + case 32: strcpy (regname, "ar.ccv"); break; + case 36: strcpy (regname, "ar.unat"); break; + case 40: strcpy (regname, "ar.fpsr"); break; + case 44: strcpy (regname, "ar.itc"); break; + case 64: strcpy (regname, "ar.pfs"); break; + case 65: strcpy (regname, "ar.lc"); break; + case 66: strcpy (regname, "ar.ec"); break; + default: + sprintf (regname, "ar%u", (unsigned int) value); + break; + } + (*info->fprintf_func) (info->stream, "%s", regname); + } + else + (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value); + break; + + case IA64_OPND_CLASS_IND: + (*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value); + break; + + case IA64_OPND_CLASS_ABS: + str = 0; + if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4) + switch (value) + { + case 0x0: str = "@brcst"; break; + case 0x8: str = "@mix"; break; + case 0x9: str = "@shuf"; break; + case 0xa: str = "@alt"; break; + case 0xb: str = "@rev"; break; + } + + if (str) + (*info->fprintf_func) (info->stream, "%s", str); + else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED) + (*info->fprintf_func) (info->stream, "%lld", value); + else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED) + (*info->fprintf_func) (info->stream, "%llu", value); + else + (*info->fprintf_func) (info->stream, "0x%llx", value); + break; + + case IA64_OPND_CLASS_REL: + (*info->print_address_func) (memaddr + value, info); + break; + } + + need_comma = 1; + if (j + 1 == idesc->num_outputs) + { + (*info->fprintf_func) (info->stream, "="); + need_comma = 0; + } + } + if (slotnum + 1 == ia64_templ_desc[template].group_boundary + || ((slotnum == 2) && s_bit)) + (*info->fprintf_func) (info->stream, ";;"); + + done: + if (slotnum == 2) + retval += 16 - 3*slot_multiplier; + return retval; + + decoding_failed: + (*info->fprintf_func) (info->stream, " data8 %#011llx", insn); + goto done; +} diff --git a/opcodes/ia64-gen.c b/opcodes/ia64-gen.c new file mode 100644 index 0000000..093d686 --- /dev/null +++ b/opcodes/ia64-gen.c @@ -0,0 +1,2723 @@ +/* ia64-gen.c -- Generate a shrunk set of opcode tables + Copyright (c) 1999 Free Software Foundation, Inc. + Written by Bob Manson, Cygnus Solutions, + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +/* While the ia64-opc-* set of opcode tables are easy to maintain, + they waste a tremendous amount of space. ia64-gen rearranges the + instructions into a directed acyclic graph (DAG) of instruction opcodes and + their possible completers, as well as compacting the set of strings used. + + The disassembler table consists of a state machine that does + branching based on the bits of the opcode being disassembled. The + state encodings have been chosen to minimize the amount of space + required. + + The resource table is constructed based on some text dependency tables, + which are also easier to maintain than the final representation. + +*/ + +#include +#include + +#include "ansidecl.h" +#include "libiberty.h" +#include "sysdep.h" +#include "ia64-opc.h" +#include "ia64-opc-a.c" +#include "ia64-opc-i.c" +#include "ia64-opc-m.c" +#include "ia64-opc-b.c" +#include "ia64-opc-f.c" +#include "ia64-opc-x.c" +#include "ia64-opc-d.c" + +int debug = 0; + +#define tmalloc(X) (X *) xmalloc (sizeof (X)) + +/* The main opcode table entry. Each entry is a unique combination of + name and flags (no two entries in the table compare as being equal + via opcodes_eq). */ +struct main_entry +{ + /* The base name of this opcode. The names of its completers are + appended to it to generate the full instruction name. */ + struct string_entry *name; + /* The base opcode entry. Which one to use is a fairly arbitrary choice; + it uses the first one passed to add_opcode_entry. */ + struct ia64_opcode *opcode; + /* The list of completers that can be applied to this opcode. */ + struct completer_entry *completers; + /* Next entry in the chain. */ + struct main_entry *next; +} *maintable; + +/* The set of possible completers for an opcode. */ +struct completer_entry +{ + /* This entry's index in the ia64_completer_table[] array. */ + int num; + + /* The name of the completer. */ + struct string_entry *name; + + /* This entry's parent. */ + struct completer_entry *parent; + + /* Set if this is a terminal completer (occurs at the end of an + opcode). */ + int is_terminal; + + /* An alternative completer. */ + struct completer_entry *alternative; + + /* Additional completers that can be appended to this one. */ + struct completer_entry *addl_entries; + + /* Before compute_completer_bits () is invoked, this contains the actual + instruction opcode for this combination of opcode and completers. + Afterwards, it contains those bits that are different from its + parent opcode. */ + ia64_insn bits; + + /* Bits set to 1 correspond to those bits in this completer's opcode + that are different from its parent completer's opcode (or from + the base opcode if the entry is the root of the opcode's completer + list). This field is filled in by compute_completer_bits (). */ + ia64_insn mask; + + /* Index into the opcode dependency list, or -1 if none */ + int dependencies; +}; + +/* One entry in the disassembler name table. */ +struct disent +{ + /* The index into the ia64_name_dis array for this entry. */ + int ournum; + + /* The index into the main_table[] array. */ + int insn; + + /* The completer_index value for this entry. */ + int completer_index; + + /* How many other entries share this decode. */ + int nextcnt; + + /* The next entry sharing the same decode. */ + struct disent *nexte; + + /* The next entry in the name list. */ + struct disent *next_ent; +} *disinsntable = NULL; + +/* A state machine that will eventually be used to generate the + disassembler table. */ +struct bittree +{ + struct disent *disent; + struct bittree *bits[3]; + int bits_to_skip; + int skip_flag; +} *bittree; + +/* The string table contains all opcodes and completers sorted in + alphabetical order. */ + +/* One entry in the string table. */ +struct string_entry +{ + /* The index in the ia64_strings[] array for this entry. */ + int num; + /* And the string. */ + char *s; +} **string_table = NULL; +int strtablen = 0; +int strtabtotlen = 0; + + +/* resource dependency entries */ +struct rdep +{ + char *name; /* resource name */ + unsigned + mode:2, /* RAW, WAW, or WAR */ + semantics:3; /* dependency semantics */ + char *extra; /* additional semantics info */ + int nchks; + int total_chks; /* total #of terminal insns */ + int *chks; /* insn classes which read (RAW), write + (WAW), or write (WAR) this rsrc */ // + int *chknotes; /* dependency notes for each class */ + int nregs; + int total_regs; /* total #of terminal insns */ + int *regs; /* insn class which write (RAW), write2 + (WAW), or read (WAR) this rsrc */ + int *regnotes; /* dependency notes for each class */ + + int waw_special; /* special WAW dependency note */ +} **rdeps = NULL; + +static int rdepslen = 0; +static int rdepstotlen = 0; + +/* array of all instruction classes */ +struct iclass +{ + char *name; /* instruction class name */ + int is_class; /* is a class, not a terminal */ + int nsubs; + int *subs; /* other classes within this class */ + int nxsubs; + int xsubs[4]; /* exclusions */ + char *comment; /* optional comment */ + int note; /* optional note */ + int terminal_resolved; /* did we match this with anything? */ + int orphan; /* detect class orphans */ +} **ics = NULL; + +static int iclen = 0; +static int ictotlen = 0; + +/* an opcode dependency (chk/reg pair of dependency lists) */ +struct opdep +{ + int chk; /* index into dlists */ + int reg; /* index into dlists */ +} **opdeps; + +static int opdeplen = 0; +static int opdeptotlen = 0; + +/* a generic list of dependencies w/notes encoded. these may be shared. */ +struct deplist +{ + int len; + unsigned short *deps; +} **dlists; + +static int dlistlen = 0; +static int dlisttotlen = 0; + +/* add NAME to the resource table, where TYPE is RAW or WAW */ +static struct rdep * +insert_resource (const char *name, enum ia64_dependency_mode type) +{ + if (rdepslen == rdepstotlen) + { + rdepstotlen += 20; + rdeps = (struct rdep **) + xrealloc (rdeps, sizeof(struct rdep **) * rdepstotlen); + } + rdeps[rdepslen] = tmalloc(struct rdep); + memset((void *)rdeps[rdepslen], 0, sizeof(struct rdep)); + rdeps[rdepslen]->name = xstrdup (name); + rdeps[rdepslen]->mode = type; + rdeps[rdepslen]->waw_special = 0; + + return rdeps[rdepslen++]; +} + +/* are the lists of dependency indexes equivalent? */ +static int +deplist_equals (struct deplist *d1, struct deplist *d2) +{ + int i; + + if (d1->len != d2->len) + return 0; + + for (i=0;i < d1->len;i++) + { + if (d1->deps[i] != d2->deps[i]) + return 0; + } + + return 1; +} + +/* add the list of dependencies to the list of dependency lists */ +static short +insert_deplist(int count, unsigned short *deps) +{ + /* sort the list, then see if an equivalent list exists already. + this results in a much smaller set of dependency lists + */ + struct deplist *list; + char set[0x10000]; + int i; + + memset ((void *)set, 0, sizeof(set)); + for (i=0;i < count;i++) + set[deps[i]] = 1; + count = 0; + for (i=0;i < sizeof(set);i++) + if (set[i]) + ++count; + + list = tmalloc(struct deplist); + list->len = count; + list->deps = (unsigned short *)malloc (sizeof(unsigned short) * count); + for (i=0, count=0;i < sizeof(set);i++) + { + if (set[i]) + { + list->deps[count++] = i; + } + } + + /* does this list exist already? */ + for (i=0;i < dlistlen;i++) + { + if (deplist_equals (list, dlists[i])) + { + free (list->deps); + free (list); + return i; + } + } + + if (dlistlen == dlisttotlen) + { + dlisttotlen += 20; + dlists = (struct deplist **) + xrealloc (dlists, sizeof(struct deplist **) * dlisttotlen); + } + dlists[dlistlen] = list; + + return dlistlen++; +} + +/* add the given pair of dependency lists to the opcode dependency list */ +static short +insert_dependencies (int nchks, unsigned short *chks, + int nregs, unsigned short *regs) +{ + struct opdep *pair; + int i; + int regind = -1; + int chkind = -1; + + if (nregs > 0) + regind = insert_deplist (nregs, regs); + if (nchks > 0) + chkind = insert_deplist (nchks, chks); + + for (i=0;i < opdeplen;i++) + { + if (opdeps[i]->chk == chkind + && opdeps[i]->reg == regind) + return i; + } + pair = tmalloc(struct opdep); + pair->chk = chkind; + pair->reg = regind; + + if (opdeplen == opdeptotlen) + { + opdeptotlen += 20; + opdeps = (struct opdep **) + xrealloc (opdeps, sizeof(struct opdep **) * opdeptotlen); + } + opdeps[opdeplen] = pair; + + return opdeplen++; +} + +static void +mark_used (struct iclass *ic, int clear_terminals) +{ + int i; + + ic->orphan = 0; + if (clear_terminals) + ic->terminal_resolved = 1; + + for (i=0;i < ic->nsubs;i++) + { + mark_used (ics[ic->subs[i]], clear_terminals); + } + for (i=0;i < ic->nxsubs;i++) + { + mark_used (ics[ic->xsubs[i]], clear_terminals); + } +} + +/* look up an instruction class; if CREATE make a new one if none found; + returns the index into the insn class array */ +static int +fetch_insn_class(const char *full_name, int create) +{ + char *name; + char *notestr; + char *xsect; + char *comment; + int i, note = 0; + int ind; + int is_class = 0; + + if (strncmp (full_name, "IC:", 3) == 0) + { + name = xstrdup (full_name + 3); + is_class = 1; + } + else + name = xstrdup (full_name); + + if ((xsect = strchr(name, '\\')) != NULL) + is_class = 1; + if ((comment = strchr(name, '[')) != NULL) + is_class = 1; + if ((notestr = strchr(name, '+')) != NULL) + { + char *nextnotestr; + is_class = 1; + note = atoi (notestr + 1); + if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) + { + if (strcmp (notestr, "+1+13") == 0) + note = 13; + else if (!xsect || nextnotestr < xsect) + fprintf (stderr, "Warning: multiple note %s not handled\n", + notestr); + } + } + + /* if it's a composite class, leave the notes and comments in place so that + we have a unique name for the composite class */ + if (!xsect) + { + if (notestr) + *notestr = 0; + if (comment) + *comment = 0; + } + + for (i=0;i < iclen;i++) + if (strcmp(name, ics[i]->name) == 0 + && ((comment == NULL && ics[i]->comment == NULL) + || (comment != NULL && ics[i]->comment != NULL + && strncmp (ics[i]->comment, comment, + strlen (ics[i]->comment)) == 0)) + && note == ics[i]->note) + return i; + + if (!create) + return -1; + + /* doesn't exist, so make a new one */ + if (iclen == ictotlen) + { + ictotlen += 20; + ics = (struct iclass **) + xrealloc(ics, (ictotlen)*sizeof(struct iclass *)); + } + ind = iclen++; + ics[ind] = tmalloc(struct iclass); + memset((void *)ics[ind], 0, sizeof(struct iclass)); + ics[ind]->name = xstrdup(name); + ics[ind]->is_class = is_class; + ics[ind]->orphan = 1; + + if (comment) + { + ics[ind]->comment = xstrdup (comment + 1); + ics[ind]->comment[strlen(ics[ind]->comment)-1] = 0; + } + if (notestr) + ics[ind]->note = note; + + /* if it's a composite class, there's a comment or note, look for an + existing class or terminal with the same name. */ + if ((xsect || comment || notestr) && is_class) + { + // first, populate with the class we're based on + char *subname = name; + if (xsect) + *xsect = 0; + else if (comment) + *comment = 0; + else if (notestr) + *notestr = 0; + ics[ind]->nsubs = 1; + ics[ind]->subs = tmalloc(int); + ics[ind]->subs[0] = fetch_insn_class (subname, 1);; + } + + while (xsect) + { + char *subname = xsect + 1; + xsect = strchr (subname, '\\'); + if (xsect) + *xsect = 0; + ics[ind]->xsubs[ics[ind]->nxsubs] = fetch_insn_class (subname,1); + ics[ind]->nxsubs++; + } + free (name); + + return ind; +} + +/* for sorting a class's sub-class list only; make sure classes appear before + terminals */ +static int +sub_compare (const void *e1, const void *e2) +{ + struct iclass *ic1 = ics[*(int *)e1]; + struct iclass *ic2 = ics[*(int *)e2]; + + if (ic1->is_class) + { + if (!ic2->is_class) + return -1; + } + else if (ic2->is_class) + return 1; + + return strcmp (ic1->name, ic2->name); +} + +static void +load_insn_classes() +{ + FILE *fp = fopen("ia64-ic.tbl", "r"); + char buf[2048]; + + /* discard first line */ + fgets (buf, sizeof(buf), fp); + + while (!feof(fp)) + { + int iclass; + char *name; + char *tmp; + + if (fgets (buf, sizeof(buf), fp) == NULL) + break; + + while (isspace(buf[strlen(buf)-1])) + buf[strlen(buf)-1] = '\0'; + + name = tmp = buf; + while (*tmp != ';') + { + ++tmp; + if (tmp == buf + sizeof(buf)) + abort (); + } + *tmp++ = '\0'; + + iclass = fetch_insn_class(name, 1); + ics[iclass]->is_class = 1; + + if (strcmp (name, "none") == 0) + { + ics[iclass]->is_class = 0; + ics[iclass]->terminal_resolved = 1; + continue; + } + + /* for this class, record all sub-classes */ + while (*tmp) + { + char *subname; + int sub; + + while (*tmp && isspace(*tmp)) + { + ++tmp; + if (tmp == buf + sizeof(buf)) + abort(); + } + subname = tmp; + while (*tmp && *tmp != ',') + { + ++tmp; + if (tmp == buf + sizeof(buf)) + abort(); + } + if (*tmp == ',') + *tmp++ = '\0'; + + ics[iclass]->subs = (int *) + xrealloc((void *)ics[iclass]->subs, + (ics[iclass]->nsubs+1)*sizeof(int)); + + sub = fetch_insn_class(subname, 1); + ics[iclass]->subs = (int *) + xrealloc(ics[iclass]->subs, (ics[iclass]->nsubs+1)*sizeof(int)); + ics[iclass]->subs[ics[iclass]->nsubs++] = sub; + } + /* make sure classes come before terminals */ + qsort ((void *)ics[iclass]->subs, + ics[iclass]->nsubs, sizeof(int), sub_compare); + } + fclose(fp); + + if (debug) + { + printf ("%d classes\n", iclen); + } +} + +/* extract the insn classes from the given line */ +static void +parse_resource_users(ref, usersp, nusersp, notesp) + char *ref; + int **usersp; + int *nusersp; + int **notesp; +{ + int c; + char *line = xstrdup (ref); + char *tmp = line; + int *users = *usersp; + int count = *nusersp; + int *notes = *notesp; + + c = *tmp; + while (c != 0) + { + char *notestr; + int note; + char *xsect; + int iclass; + int create = 0; + char *name; + + while (isspace(*tmp)) + ++tmp; + name = tmp; + while (*tmp && *tmp != ',') + ++tmp; + c = *tmp; + *tmp++ = '\0'; + + xsect = strchr(name, '\\'); + if ((notestr = strstr(name, "+")) != NULL) + { + char *nextnotestr; + note = atoi (notestr + 1); + if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) + { + /* note 13 always implies note 1 */ + if (strcmp (notestr, "+1+13") == 0) + note = 13; + else if (!xsect || nextnotestr < xsect) + fprintf (stderr, "Warning: multiple note %s not handled\n", + notestr); + } + if (!xsect) + *notestr = '\0'; + } + else + note = 0; + + /* All classes are created when the insn class table is parsed; + Individual instructions might not appear until the dependency tables + are read. Only create new classes if it's *not* an insn class, + or if it's a composite class (which wouldn't necessarily be in the IC + table). + */ + if (strncmp(name, "IC:", 3) != 0 || xsect != NULL) + create = 1; + + iclass = fetch_insn_class(name, create); + if (iclass != -1) + { + users = (int *) + xrealloc ((void *)users,(count+1)*sizeof(int)); + notes = (int *) + xrealloc ((void *)notes,(count+1)*sizeof(int)); + notes[count] = note; + users[count++] = iclass; + mark_used (ics[iclass], 0); + } + else + { + if (debug) + printf("Class %s not found\n", name); + } + } + /* update the return values */ + *usersp = users; + *nusersp = count; + *notesp = notes; + + free (line); +} + +static int +parse_semantics (char *sem) +{ + if (strcmp (sem, "none") == 0) + return IA64_DVS_NONE; + else if (strcmp (sem, "implied") == 0) + return IA64_DVS_IMPLIED; + else if (strcmp (sem, "impliedF") == 0) + return IA64_DVS_IMPLIEDF; + else if (strcmp (sem, "data") == 0) + return IA64_DVS_DATA; + else if (strcmp (sem, "instr") == 0) + return IA64_DVS_INSTR; + else if (strcmp (sem, "specific") == 0) + return IA64_DVS_SPECIFIC; + else + return IA64_DVS_OTHER; +} + +static void +add_dep (const char *name, const char *chk, const char *reg, + int semantics, int mode, char *extra, int flag) +{ + struct rdep *rs; + + rs = insert_resource (name, mode); + parse_resource_users (chk, &rs->chks, &rs->nchks, + &rs->chknotes); + parse_resource_users (reg, &rs->regs, &rs->nregs, + &rs->regnotes); + rs->semantics = semantics; + rs->extra = extra; + rs->waw_special = flag; +} + +static void +load_depfile (const char *filename, enum ia64_dependency_mode mode) +{ + FILE *fp = fopen(filename, "r"); + char buf[1024]; + + fgets(buf, sizeof(buf), fp); + while (!feof(fp)) + { + char *name, *tmp; + int semantics; + char *extra; + char *regp, *chkp; + + if (fgets (buf, sizeof(buf), fp) == NULL) + break; + + while (isspace(buf[strlen(buf)-1])) + buf[strlen(buf)-1] = '\0'; + + name = tmp = buf; + while (*tmp != ';') + ++tmp; + *tmp++ = '\0'; + + while (isspace (*tmp)) + ++tmp; + regp = tmp; + tmp = strchr (tmp, ';'); + if (!tmp) + abort (); + *tmp++ = 0; + while (isspace (*tmp)) + ++tmp; + chkp = tmp; + tmp = strchr (tmp, ';'); + if (!tmp) + abort (); + *tmp++ = 0; + while (isspace (*tmp)) + ++tmp; + semantics = parse_semantics (tmp); + extra = semantics == IA64_DVS_OTHER ? xstrdup (tmp) : NULL; + + /* For WAW entries, if the chks and regs differ, we need to enter the + entries in both positions so that the tables will be parsed properly, + without a lot of extra work */ + if (mode == IA64_DV_WAW && strcmp (regp, chkp) != 0) + { + add_dep (name, chkp, regp, semantics, mode, extra, 0); + add_dep (name, regp, chkp, semantics, mode, extra, 1); + } + else + { + add_dep (name, chkp, regp, semantics, mode, extra, 0); + } + } + fclose(fp); +} + +static void +load_dependencies() +{ + load_depfile ("ia64-raw.tbl", IA64_DV_RAW); + load_depfile ("ia64-waw.tbl", IA64_DV_WAW); + load_depfile ("ia64-war.tbl", IA64_DV_WAR); + + if (debug) + printf ("%d RAW/WAW/WAR dependencies\n", rdepslen); +} + +/* is the given operand an indirect register file operand? */ +static int +irf_operand (int op, const char *field) +{ + if (!field) + { + return op == IA64_OPND_RR_R3 || op == IA64_OPND_DBR_R3 + || op == IA64_OPND_IBR_R3 || op == IA64_OPND_PKR_R3 + || op == IA64_OPND_PMC_R3 || op == IA64_OPND_PMD_R3 + || op == IA64_OPND_MSR_R3 || op == IA64_OPND_CPUID_R3; + } + else + { + return ((op == IA64_OPND_RR_R3 && strstr (field, "rr")) + || (op == IA64_OPND_DBR_R3 && strstr (field, "dbr")) + || (op == IA64_OPND_IBR_R3 && strstr (field, "ibr")) + || (op == IA64_OPND_PKR_R3 && strstr (field, "pkr")) + || (op == IA64_OPND_PMC_R3 && strstr (field, "pmc")) + || (op == IA64_OPND_PMD_R3 && strstr (field, "pmd")) + || (op == IA64_OPND_MSR_R3 && strstr (field, "msr")) + || (op == IA64_OPND_CPUID_R3 && strstr (field, "cpuid"))); + } +} + +/* handle mov_ar, mov_br, mov_cr, mov_indirect, mov_ip, mov_pr, mov_psr, and + mov_um insn classes */ +static int +in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic, + const char *format, const char *field) +{ + int plain_mov = strcmp (idesc->name, "mov") == 0; + + if (!format) + return 0; + + switch (ic->name[4]) + { + default: + abort (); + case 'a': + { + int i = strcmp (idesc->name, "mov.i") == 0; + int m = strcmp (idesc->name, "mov.m") == 0; + int i2627 = i && idesc->operands[0] == IA64_OPND_AR3; + int i28 = i && idesc->operands[1] == IA64_OPND_AR3; + int m2930 = m && idesc->operands[0] == IA64_OPND_AR3; + int m31 = m && idesc->operands[1] == IA64_OPND_AR3; + int pseudo0 = plain_mov && idesc->operands[1] == IA64_OPND_AR3; + int pseudo1 = plain_mov && idesc->operands[0] == IA64_OPND_AR3; + + /* IC:mov ar */ + if (i2627) + return strstr (format, "I26") || strstr (format, "I27"); + if (i28) + return strstr (format, "I28") != NULL; + if (m2930) + return strstr (format, "M29") || strstr (format, "M30"); + if (m31) + return strstr (format, "M31") != NULL; + if (pseudo0 || pseudo1) + return 1; + } + break; + case 'b': + { + int i21 = idesc->operands[0] == IA64_OPND_B1; + int i22 = plain_mov && idesc->operands[1] == IA64_OPND_B2; + if (i22) + return strstr (format, "I22") != NULL; + if (i21) + return strstr (format, "I21") != NULL; + } + break; + case 'c': + { + int m32 = plain_mov && idesc->operands[0] == IA64_OPND_CR3; + int m33 = plain_mov && idesc->operands[1] == IA64_OPND_CR3; + if (m32) + return strstr (format, "M32") != NULL; + if (m33) + return strstr (format, "M33") != NULL; + } + break; + case 'i': + if (ic->name[5] == 'n') + { + int m42 = plain_mov && irf_operand (idesc->operands[0], field); + int m43 = plain_mov && irf_operand (idesc->operands[1], field); + if (m42) + return strstr (format, "M42") != NULL; + if (m43) + return strstr (format, "M43") != NULL; + } + else if (ic->name[5] == 'p') + { + return idesc->operands[1] == IA64_OPND_IP; + } + else + abort (); + break; + case 'p': + if (ic->name[5] == 'r') + { + int i25 = plain_mov && idesc->operands[1] == IA64_OPND_PR; + int i23 = plain_mov && idesc->operands[0] == IA64_OPND_PR; + int i24 = plain_mov && idesc->operands[0] == IA64_OPND_PR_ROT; + if (i23) + return strstr (format, "I23") != NULL; + if (i24) + return strstr (format, "I24") != NULL; + if (i25) + return strstr (format, "I25") != NULL; + } + else if (ic->name[5] == 's') + { + int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_L; + int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR; + if (m35) + return strstr (format, "M35") != NULL; + if (m36) + return strstr (format, "M36") != NULL; + } + else + abort (); + break; + case 'u': + { + int m35 = plain_mov && idesc->operands[0] == IA64_OPND_PSR_UM; + int m36 = plain_mov && idesc->operands[1] == IA64_OPND_PSR_UM; + if (m35) + return strstr (format, "M35") != NULL; + if (m36) + return strstr (format, "M36") != NULL; + } + break; + } + return 0; +} + + +/* is the given opcode in the given insn class? */ +static int +in_iclass(struct ia64_opcode *idesc, struct iclass *ic, + const char *format, const char *field, int *notep) +{ + int i; + int resolved = 0; + + if (ic->comment) + { + if (!strncmp (ic->comment, "Format", 6)) + { + /* assume that the first format seen is the most restrictive, and + only keep a later one if it looks like it's more restrictive. */ + if (format) + { + if (strlen (ic->comment) < strlen (format)) + { + fprintf (stderr, "Warning: most recent format '%s'\n" + "appears more restrictive than '%s'\n", + ic->comment, format); + format = ic->comment; + } + } + else + format = ic->comment; + } + else if (!strncmp (ic->comment, "Field", 5)) + { + if (field) + fprintf (stderr, "Overlapping field %s->%s\n", + ic->comment, field); + field = ic->comment; + } + } + + /* an insn class matches anything that is the same followed by completers, + except when the absence and presence of completers constitutes different + instructions */ + if (ic->nsubs == 0 && ic->nxsubs == 0) + { + int is_mov = strncmp (idesc->name, "mov", 3) == 0; + int plain_mov = strcmp (idesc->name, "mov") == 0; + int len = strlen(ic->name); + + resolved = ((strncmp (ic->name, idesc->name, len) == 0) + && (idesc->name[len] == '\0' + || idesc->name[len] == '.')); + + /* all break and nop variations must match exactly */ + if (resolved && + (strcmp (ic->name, "break") == 0 + || strcmp (ic->name, "nop") == 0)) + resolved = strcmp (ic->name, idesc->name) == 0; + + /* assume restrictions in the FORMAT/FIELD negate resolution, + unless specifically allowed by clauses in this block */ + if (resolved && field) + { + /* check Field(sf)==sN against opcode sN */ + if (strstr(field, "(sf)==") != NULL) + { + char *sf; + if ((sf = strstr (idesc->name, ".s")) != 0) + { + resolved = strcmp (sf + 1, strstr (field, "==") + 2) == 0; + } + } + /* check Field(lftype)==XXX */ + else if (strstr (field, "(lftype)") != NULL) + { + if (strstr (idesc->name, "fault") != NULL) + resolved = strstr (field, "fault") != NULL; + else + resolved = strstr (field, "fault") == NULL; + } + /* handle Field(ctype)==XXX */ + else if (strstr (field, "(ctype)") != NULL) + { + if (strstr (idesc->name, "or.andcm")) + resolved = strstr (field, "or.andcm") != NULL; + else if (strstr (idesc->name, "and.orcm")) + resolved = strstr (field, "and.orcm") != NULL; + else if (strstr (idesc->name, "orcm")) + resolved = strstr (field, "or orcm") != NULL; + else if (strstr (idesc->name, "or")) + resolved = strstr (field, "or orcm") != NULL; + else if (strstr (idesc->name, "andcm")) + resolved = strstr (field, "and andcm") != NULL; + else if (strstr (idesc->name, "and")) + resolved = strstr (field, "and andcm") != NULL; + else if (strstr (idesc->name, "unc")) + resolved = strstr (field, "unc") != NULL; + else + resolved = strcmp (field, "Field(ctype)==") == 0; + } + } + if (resolved && format) + { + if (strncmp (idesc->name, "dep", 3) == 0 + && strstr (format, "I13") != NULL) + resolved = idesc->operands[1] == IA64_OPND_IMM8; + else if (strncmp (idesc->name, "chk", 3) == 0 + && strstr (format, "M21") != NULL) + resolved = idesc->operands[0] == IA64_OPND_F2; + else if (strncmp (idesc->name, "lfetch", 6) == 0) + resolved = (strstr (format, "M14 M15") != NULL + && (idesc->operands[1] == IA64_OPND_R2 + || idesc->operands[1] == IA64_OPND_IMM9b)); + else if (strncmp (idesc->name, "br.call", 7) == 0 + && strstr (format, "B5") != NULL) + resolved = idesc->operands[1] == IA64_OPND_B2; + else if (strncmp (idesc->name, "br.call", 7) == 0 + && strstr (format, "B3") != NULL) + resolved = idesc->operands[1] == IA64_OPND_TGT25c; + else if (strncmp (idesc->name, "brp", 3) == 0 + && strstr (format, "B7") != NULL) + resolved = idesc->operands[0] == IA64_OPND_B2; + else if (strcmp (ic->name, "invala") == 0) + resolved = strcmp (idesc->name, ic->name) == 0; + else + resolved = 0; + } + + /* misc brl variations ('.cond' is optional); + plain brl matches brl.cond */ + if (!resolved + && (strcmp (idesc->name, "brl") == 0 + || strncmp (idesc->name, "brl.", 4) == 0) + && strcmp (ic->name, "brl.cond") == 0) + { + resolved = 1; + } + + /* misc br variations ('.cond' is optional) */ + if (!resolved + && (strcmp (idesc->name, "br") == 0 + || strncmp (idesc->name, "br.", 3) == 0) + && strcmp (ic->name, "br.cond") == 0) + { + if (format) + resolved = (strstr (format, "B4") != NULL + && idesc->operands[0] == IA64_OPND_B2) + || (strstr (format, "B1") != NULL + && idesc->operands[0] == IA64_OPND_TGT25c); + else + resolved = 1; + } + + /* probe variations */ + if (!resolved && strncmp (idesc->name, "probe", 5) == 0) + { + resolved = strcmp (ic->name, "probe") == 0 + && !((strstr (idesc->name, "fault") != NULL) + ^ (format && strstr (format, "M40") != NULL)); + } + /* mov variations */ + if (!resolved && is_mov) + { + if (plain_mov) + { + /* mov alias for fmerge */ + if (strcmp (ic->name, "fmerge") == 0) + { + resolved = idesc->operands[0] == IA64_OPND_F1 + && idesc->operands[1] == IA64_OPND_F3; + } + /* mov alias for adds (r3 or imm14) */ + else if (strcmp (ic->name, "adds") == 0) + { + resolved = (idesc->operands[0] == IA64_OPND_R1 + && (idesc->operands[1] == IA64_OPND_R3 + || (idesc->operands[1] == IA64_OPND_IMM14))); + } + /* mov alias for addl */ + else if (strcmp (ic->name, "addl") == 0) + { + resolved = idesc->operands[0] == IA64_OPND_R1 + && idesc->operands[1] == IA64_OPND_IMM22; + } + } + /* some variants of mov and mov.[im] */ + if (!resolved && strncmp (ic->name, "mov_", 4) == 0) + { + resolved = in_iclass_mov_x (idesc, ic, format, field); + } + } + + /* keep track of this so we can flag any insn classes which aren't + mapped onto at least one real insn */ + if (resolved) + { + ic->terminal_resolved = 1; + } + } + else for (i=0;i < ic->nsubs;i++) + { + if (in_iclass(idesc, ics[ic->subs[i]], format, field, notep)) + { + int j; + for (j=0;j < ic->nxsubs;j++) + { + if (in_iclass(idesc, ics[ic->xsubs[j]], NULL, NULL, NULL)) + return 0; + } + if (debug > 1) + printf ("%s is in IC %s\n", + idesc->name, ic->name); + resolved = 1; + break; + } + } + + /* If it's in this IC, add the IC note (if any) to the insn */ + if (resolved) + { + if (ic->note && notep) + { + if (*notep && *notep != ic->note) + { + fprintf (stderr, "Warning: overwriting note %d with note %d" + "(IC:%s)\n", + *notep, ic->note, ic->name); + } + *notep = ic->note; + } + } + + return resolved; +} + + +static int +lookup_regindex (const char *name, int specifier) +{ + switch (specifier) + { + case IA64_RS_ARX: + if (strstr (name, "[RSC]")) + return 16; + if (strstr (name, "[BSP]")) + return 17; + else if (strstr (name, "[BSPSTORE]")) + return 18; + else if (strstr (name, "[RNAT]")) + return 19; + else if (strstr (name, "[CCV]")) + return 32; + else if (strstr (name, "[ITC]")) + return 44; + else if (strstr (name, "[PFS]")) + return 64; + else if (strstr (name, "[LC]")) + return 65; + else if (strstr (name, "[EC]")) + return 66; + abort (); + case IA64_RS_CRX: + if (strstr (name, "[DCR]")) + return 0; + else if (strstr (name, "[ITM]")) + return 1; + else if (strstr (name, "[IVA]")) + return 2; + else if (strstr (name, "[PTA]")) + return 8; + else if (strstr (name, "[GPTA]")) + return 9; + else if (strstr (name, "[IPSR]")) + return 16; + else if (strstr (name, "[ISR]")) + return 17; + else if (strstr (name, "[IIP]")) + return 19; + else if (strstr (name, "[IFA]")) + return 20; + else if (strstr (name, "[ITIR]")) + return 21; + else if (strstr (name, "[IIPA]")) + return 22; + else if (strstr (name, "[IFS]")) + return 23; + else if (strstr (name, "[IIM]")) + return 24; + else if (strstr (name, "[IHA]")) + return 25; + else if (strstr (name, "[LID]")) + return 64; + else if (strstr (name, "[IVR]")) + return 65; + else if (strstr (name, "[TPR]")) + return 66; + else if (strstr (name, "[EOI]")) + return 67; + else if (strstr (name, "[ITV]")) + return 72; + else if (strstr (name, "[PMV]")) + return 73; + else if (strstr (name, "[CMCV]")) + return 74; + abort (); + case IA64_RS_PSR: + if (strstr (name, ".be")) + return 1; + else if (strstr (name, ".up")) + return 2; + else if (strstr (name, ".ac")) + return 3; + else if (strstr (name, ".mfl")) + return 4; + else if (strstr (name, ".mfh")) + return 5; + else if (strstr (name, ".ic")) + return 13; + else if (strstr (name, ".i")) + return 14; + else if (strstr (name, ".pk")) + return 15; + else if (strstr (name, ".dt")) + return 17; + else if (strstr (name, ".dfl")) + return 18; + else if (strstr (name, ".dfh")) + return 19; + else if (strstr (name, ".sp")) + return 20; + else if (strstr (name, ".pp")) + return 21; + else if (strstr (name, ".di")) + return 22; + else if (strstr (name, ".si")) + return 23; + else if (strstr (name, ".db")) + return 24; + else if (strstr (name, ".lp")) + return 25; + else if (strstr (name, ".tb")) + return 26; + else if (strstr (name, ".rt")) + return 27; + else if (strstr (name, ".cpl")) + return 32; + else if (strstr (name, ".rs")) + return 34; + else if (strstr (name, ".mc")) + return 35; + else if (strstr (name, ".it")) + return 36; + else if (strstr (name, ".id")) + return 37; + else if (strstr (name, ".da")) + return 38; + else if (strstr (name, ".dd")) + return 39; + else if (strstr (name, ".ss")) + return 40; + else if (strstr (name, ".ri")) + return 41; + else if (strstr (name, ".ed")) + return 43; + else if (strstr (name, ".bn")) + return 44; + else if (strstr (name, ".ia")) + return 45; + else + abort (); + default: + break; + } + return REG_NONE; +} + +static int +lookup_specifier (const char *name) +{ + if (strchr (name, '%')) + { + if (strstr (name, "AR[K%]") != NULL) + return IA64_RS_AR_K; + if (strstr (name, "AR[UNAT]") != NULL) + return IA64_RS_AR_UNAT; + if (strstr (name, "AR%, % in 8") != NULL) + return IA64_RS_AR; + if (strstr (name, "AR%, % in 48") != NULL) + return IA64_RS_ARb; + if (strstr (name, "BR%") != NULL) + return IA64_RS_BR; + if (strstr (name, "CR[IRR%]") != NULL) + return IA64_RS_CR_IRR; + if (strstr (name, "CR[LRR%]") != NULL) + return IA64_RS_CR_LRR; + if (strstr (name, "CR%") != NULL) + return IA64_RS_CR; + if (strstr (name, "FR%, % in 0") != NULL) + return IA64_RS_FR; + if (strstr (name, "FR%, % in 2") != NULL) + return IA64_RS_FRb; + if (strstr (name, "GR%") != NULL) + return IA64_RS_GR; + if (strstr (name, "PR%") != NULL) + return IA64_RS_PR; + + fprintf (stderr, "Warning! Don't know how to specify %% dependency %s\n", + name); + } + else if (strchr (name, '#')) + { + if (strstr (name, "CPUID#") != NULL) + return IA64_RS_CPUID; + if (strstr (name, "DBR#") != NULL) + return IA64_RS_DBR; + if (strstr (name, "IBR#") != NULL) + return IA64_RS_IBR; + if (strstr (name, "MSR#") != NULL) + return IA64_RS_MSR; + if (strstr (name, "PKR#") != NULL) + return IA64_RS_PKR; + if (strstr (name, "PMC#") != NULL) + return IA64_RS_PMC; + if (strstr (name, "PMD#") != NULL) + return IA64_RS_PMD; + if (strstr (name, "RR#") != NULL) + return IA64_RS_RR; + + fprintf (stderr, "Warning! Don't know how to specify # dependency %s\n", + name); + } + else if (strncmp (name, "AR[FPSR]", 8) == 0) + return IA64_RS_AR_FPSR; + else if (strncmp (name, "AR[", 3) == 0) + return IA64_RS_ARX; + else if (strncmp (name, "CR[", 3) == 0) + return IA64_RS_CRX; + else if (strncmp (name, "PSR.", 4) == 0) + return IA64_RS_PSR; + else if (strcmp (name, "InService*") == 0) + return IA64_RS_INSERVICE; + else if (strcmp (name, "GR0") == 0) + return IA64_RS_GR0; + else if (strcmp (name, "CFM") == 0) + return IA64_RS_CFM; + else if (strcmp (name, "PR63") == 0) + return IA64_RS_PR63; + else if (strcmp (name, "RSE") == 0) + return IA64_RS_RSE; + + return IA64_RS_ANY; +} + +void +print_dependency_table () +{ + int i, j; + + if (debug) + { + for (i=0;i < iclen;i++) + { + if (ics[i]->is_class) + { + if (!ics[i]->nsubs) + { + fprintf (stderr, "Warning: IC:%s", ics[i]->name); + if (ics[i]->comment) + fprintf (stderr, "[%s]", ics[i]->comment); + fprintf (stderr, " has no terminals or sub-classes\n"); + } + } + else + { + if (!ics[i]->terminal_resolved && !ics[i]->orphan) + { + fprintf(stderr, "Warning: no insns mapped directly to " + "terminal IC %s", ics[i]->name); + if (ics[i]->comment) + fprintf(stderr, "[%s] ", ics[i]->comment); + fprintf(stderr, "\n"); + } + } + } + + for (i=0;i < iclen;i++) + { + if (ics[i]->orphan) + { + mark_used (ics[i], 1); + fprintf (stderr, "Warning: class %s is defined but not used\n", + ics[i]->name); + } + } + + if (debug > 1) for (i=0;i < rdepslen;i++) + { + static const char *mode_str[] = { "RAW", "WAW", "WAR" }; + if (rdeps[i]->total_chks == 0) + { + fprintf (stderr, "Warning: rsrc %s (%s) has no chks%s\n", + rdeps[i]->name, mode_str[rdeps[i]->mode], + rdeps[i]->total_regs ? "" : " or regs"); + } + else if (rdeps[i]->total_regs == 0) + { + fprintf (stderr, "Warning: rsrc %s (%s) has no regs\n", + rdeps[i]->name, mode_str[rdeps[i]->mode]); + } + } + } + + /* the dependencies themselves */ + printf ("static const struct ia64_dependency\ndependencies[] = {\n"); + for (i=0;i < rdepslen;i++) + { + /* '%', '#', AR[], CR[], or PSR. indicates we need to specify the actual + resource used */ + int specifier = lookup_specifier (rdeps[i]->name); + int regindex = lookup_regindex (rdeps[i]->name, specifier); + + printf (" { \"%s\", %d, %d, %d, %d, ", + rdeps[i]->name, specifier, + (int)rdeps[i]->mode, (int)rdeps[i]->semantics, regindex); + if (rdeps[i]->semantics == IA64_DVS_OTHER) + printf ("\"%s\", ", rdeps[i]->extra); + printf("},\n"); + } + printf ("};\n\n"); + + /* and dependency lists */ + for (i=0;i < dlistlen;i++) + { + int len = 2; + printf ("static const short dep%d[] = {\n ", i); + for (j=0;j < dlists[i]->len; j++) + { + len += printf ("%d, ", dlists[i]->deps[j]); + if (len > 75) + { + printf("\n "); + len = 2; + } + } + printf ("\n};\n\n"); + } + + /* and opcode dependency list */ + printf ("#define NELS(X) (sizeof(X)/sizeof(X[0]))\n"); + printf ("static const struct ia64_opcode_dependency\n"); + printf ("op_dependencies[] = {\n"); + for (i=0;i < opdeplen;i++) + { + printf (" { "); + if (opdeps[i]->chk == -1) + printf ("0, NULL, "); + else + printf ("NELS(dep%d), dep%d, ", opdeps[i]->chk, opdeps[i]->chk); + if (opdeps[i]->reg == -1) + printf ("0, NULL, "); + else + printf ("NELS(dep%d), dep%d, ", opdeps[i]->reg, opdeps[i]->reg); + printf ("},\n"); + } + printf ("};\n\n"); +} + + +/* Add STR to the string table. */ + +static struct string_entry * +insert_string (str) + char *str; +{ + int start = 0, end = strtablen; + int i, x; + + if (strtablen == strtabtotlen) + { + strtabtotlen += 20; + string_table = (struct string_entry **) + xrealloc (string_table, + sizeof (struct string_entry **) * strtabtotlen); + } + + if (strtablen == 0) + { + strtablen = 1; + string_table[0] = tmalloc (struct string_entry); + string_table[0]->s = xstrdup (str); + string_table[0]->num = 0; + return string_table[0]; + } + + if (strcmp (str, string_table[strtablen - 1]->s) > 0) + { + i = end; + } + else if (strcmp (str, string_table[0]->s) < 0) + { + i = 0; + } + else + { + while (1) + { + int c; + + i = (start + end) / 2; + c = strcmp (str, string_table[i]->s); + if (c < 0) + { + end = i - 1; + } + else if (c == 0) + { + return string_table[i]; + } + else + { + start = i + 1; + } + if (start > end) + { + break; + } + } + } + for (; i > 0 && i < strtablen; i--) + { + if (strcmp (str, string_table[i - 1]->s) > 0) + { + break; + } + } + for (; i < strtablen; i++) + { + if (strcmp (str, string_table[i]->s) < 0) + { + break; + } + } + for (x = strtablen - 1; x >= i; x--) + { + string_table[x + 1] = string_table[x]; + string_table[x + 1]->num = x + 1; + } + string_table[i] = tmalloc (struct string_entry); + string_table[i]->s = xstrdup (str); + string_table[i]->num = i; + strtablen++; + return string_table[i]; +} + +struct bittree * +make_bittree_entry () +{ + struct bittree *res = tmalloc (struct bittree); + + res->disent = NULL; + res->bits[0] = NULL; + res->bits[1] = NULL; + res->bits[2] = NULL; + res->skip_flag = 0; + res->bits_to_skip = 0; + return res; +} + +struct disent * +add_dis_table_ent (which, insn, completer_index) + struct disent *which; + int insn; + int completer_index; +{ + int ci = 0; + struct disent *ent; + + if (which != NULL) + { + ent = which; + + ent->nextcnt++; + while (ent->nexte != NULL) + { + ent = ent->nexte; + } + ent = (ent->nexte = tmalloc (struct disent)); + } + else + { + ent = tmalloc (struct disent); + ent->next_ent = disinsntable; + disinsntable = ent; + which = ent; + } + ent->nextcnt = 0; + ent->nexte = NULL; + ent->insn = insn; + while (completer_index != 1) + { + ci = (ci << 1) | (completer_index & 1); + completer_index >>= 1; + } + ent->completer_index = ci; + return which; +} + +void +finish_distable () +{ + struct disent *ent = disinsntable; + struct disent *prev = ent; + + ent->ournum = 32768; + while ((ent = ent->next_ent) != NULL) + { + ent->ournum = prev->ournum + prev->nextcnt + 1; + prev = ent; + } +} + +void +insert_bit_table_ent (curr_ent, bit, opcode, mask, opcodenum, completer_index) + struct bittree *curr_ent; + int bit; + ia64_insn opcode; + ia64_insn mask; + int opcodenum; + int completer_index; +{ + ia64_insn m; + int b; + struct bittree *next; + + if (bit == -1) + { + struct disent *nent = add_dis_table_ent (curr_ent->disent, opcodenum, + completer_index); + curr_ent->disent = nent; + return; + } + + m = ((ia64_insn) 1) << bit; + + if (mask & m) + { + b = (opcode & m) ? 1 : 0; + } + else + { + b = 2; + } + next = curr_ent->bits[b]; + if (next == NULL) + { + next = make_bittree_entry (); + curr_ent->bits[b] = next; + } + insert_bit_table_ent (next, bit - 1, opcode, mask, opcodenum, + completer_index); +} + +void +add_dis_entry (first, opcode, mask, opcodenum, ent, completer_index) + int first; + ia64_insn opcode; + ia64_insn mask; + int opcodenum; + struct completer_entry *ent; + int completer_index; +{ + if (completer_index & (1 << 20)) + { + abort (); + } + while (ent != NULL) + { + ia64_insn newopcode = (opcode & (~ ent->mask)) | ent->bits; + add_dis_entry (first, newopcode, mask, opcodenum, ent->addl_entries, + (completer_index << 1) | 1); + if (ent->is_terminal) + { + insert_bit_table_ent (bittree, 40, newopcode, mask, opcodenum, + (completer_index << 1) | 1); + } + completer_index <<= 1; + ent = ent->alternative; + } +} + +/* This optimization pass combines multiple "don't care" nodes. */ +void +compact_distree (ent) + struct bittree *ent; +{ +#define IS_SKIP(ent) \ + ((ent->bits[2] !=NULL) \ + && (ent->bits[0] == NULL && ent->bits[1] == NULL && ent->skip_flag == 0)) + + int bitcnt = 0; + struct bittree *nent = ent; + int x; + + while (IS_SKIP (nent)) + { + bitcnt++; + nent = nent->bits[2]; + } + + if (bitcnt) + { + struct bittree *next = ent->bits[2]; + + ent->bits[0] = nent->bits[0]; + ent->bits[1] = nent->bits[1]; + ent->bits[2] = nent->bits[2]; + ent->disent = nent->disent; + ent->skip_flag = 1; + ent->bits_to_skip = bitcnt; + while (next != nent) + { + struct bittree *b = next; + next = next->bits[2]; + free (b); + } + free (nent); + } + + for (x = 0; x < 3; x++) + { + struct bittree *i = ent->bits[x]; + if (i != NULL) + { + compact_distree (i); + } + } +} + +static unsigned char *insn_list; +static int insn_list_len = 0; +static int tot_insn_list_len = 0; + +/* Generate the disassembler state machine corresponding to the tree + in ENT. */ +void +gen_dis_table (ent) + struct bittree *ent; +{ + int x; + int our_offset = insn_list_len; + int bitsused = 5; + int totbits = bitsused; + int needed_bytes; + int zero_count = 0; + int zero_dest = 0; /* initialize this with 0 to keep gcc quiet... */ + + /* If this is a terminal entry, there's no point in skipping any + bits. */ + if (ent->skip_flag && ent->bits[0] == NULL && ent->bits[1] == NULL && + ent->bits[2] == NULL) + { + if (ent->disent == NULL) + { + abort (); + } + else + { + ent->skip_flag = 0; + } + } + + /* Calculate the amount of space needed for this entry, or at least + a conservatively large approximation. */ + if (ent->skip_flag) + { + totbits += 5; + } + for (x = 1; x < 3; x++) + { + if (ent->bits[x] != NULL) + { + totbits += 16; + } + } + + if (ent->disent != NULL) + { + if (ent->bits[2] != NULL) + { + abort (); + } + totbits += 16; + } + + /* Now allocate the space. */ + needed_bytes = (totbits + 7) / 8; + if ((needed_bytes + insn_list_len) > tot_insn_list_len) + { + tot_insn_list_len += 256; + insn_list = (char *) xrealloc (insn_list, tot_insn_list_len); + } + our_offset = insn_list_len; + insn_list_len += needed_bytes; + memset (insn_list + our_offset, 0, needed_bytes); + + /* Encode the skip entry by setting bit 6 set in the state op field, + and store the # of bits to skip immediately after. */ + if (ent->skip_flag) + { + bitsused += 5; + insn_list[our_offset + 0] |= 0x40 | ((ent->bits_to_skip >> 2) & 0xf); + insn_list[our_offset + 1] |= ((ent->bits_to_skip & 3) << 6); + } + +#define IS_ONLY_IFZERO(ENT) \ + ((ENT)->bits[0] != NULL && (ENT)->bits[1] == NULL && (ENT)->bits[2] == NULL \ + && (ENT)->disent == NULL && (ENT)->skip_flag == 0) + + /* Store an "if (bit is zero)" instruction by setting bit 7 in the + state op field. */ + + if (ent->bits[0] != NULL) + { + struct bittree *nent = ent->bits[0]; + zero_count = 0; + + insn_list[our_offset] |= 0x80; + + /* We can encode sequences of multiple "if (bit is zero)" tests + by storing the # of zero bits to check in the lower 3 bits of + the instruction. However, this only applies if the state + solely tests for a zero bit. */ + + if (IS_ONLY_IFZERO (ent)) + { + while (IS_ONLY_IFZERO (nent) && zero_count < 7) + { + nent = nent->bits[0]; + zero_count++; + } + + insn_list[our_offset + 0] |= zero_count; + } + zero_dest = insn_list_len; + gen_dis_table (nent); + } + + /* Now store the remaining tests. We also handle a sole "termination + entry" by storing it as an "any bit" test. */ + + for (x = 1; x < 3; x++) + { + if (ent->bits[x] != NULL || (x == 2 && ent->disent != NULL)) + { + struct bittree *i = ent->bits[x]; + int idest; + int currbits = 15; + + if (i != NULL) + { + /* If the instruction being branched to only consists of + a termination entry, use the termination entry as the + place to branch to instead. */ + if (i->bits[0] == NULL && i->bits[1] == NULL + && i->bits[2] == NULL && i->disent != NULL) + { + idest = i->disent->ournum; + i = NULL; + } + else + { + idest = insn_list_len - our_offset; + } + } + else + { + idest = ent->disent->ournum; + } + + /* If the destination offset for the if (bit is 1) test is less + than 256 bytes away, we can store it as 8-bits instead of 16; + the instruction has bit 5 set for the 16-bit address, and bit + 4 for the 8-bit address. Since we've already allocated 16 + bits for the address we need to deallocate the space. + + Note that branchings within the table are relative, and + there are no branches that branch past our instruction yet + so we do not need to adjust any other offsets. */ + + if (x == 1) + { + if (idest <= 256) + { + int start = our_offset + bitsused / 8 + 1; + + memmove (insn_list + start, + insn_list + start + 1, + insn_list_len - (start + 1)); + currbits = 7; + totbits -= 8; + needed_bytes--; + insn_list_len--; + insn_list[our_offset] |= 0x10; + idest--; + } + else + { + insn_list[our_offset] |= 0x20; + } + } + else + { + /* An instruction which solely consists of a termination + marker and whose disassembly name index is < 4096 + can be stored in 16 bits. The encoding is slightly + odd; the upper 4 bits of the instruction are 0x3, and + bit 3 loses its normal meaning. */ + + if (ent->bits[0] == NULL && ent->bits[1] == NULL + && ent->bits[2] == NULL && ent->skip_flag == 0 + && ent->disent != NULL + && ent->disent->ournum < (32768 + 4096)) + { + int start = our_offset + bitsused / 8 + 1; + + memmove (insn_list + start, + insn_list + start + 1, + insn_list_len - (start + 1)); + currbits = 11; + totbits -= 5; + bitsused--; + needed_bytes--; + insn_list_len--; + insn_list[our_offset] |= 0x30; + idest &= ~32768; + } + else + { + insn_list[our_offset] |= 0x08; + } + } + if (debug) + { + int id = idest; + + if (i == NULL) + { + id |= 32768; + } + else if (! (id & 32768)) + { + id += our_offset; + } + if (x == 1) + { + printf ("%d: if (1) goto %d\n", our_offset, id); + } + else + { + printf ("%d: try %d\n", our_offset, id); + } + } + + /* Store the address of the entry being branched to. */ + while (currbits >= 0) + { + char *byte = insn_list + our_offset + bitsused / 8; + + if (idest & (1 << currbits)) + { + *byte |= (1 << (7 - (bitsused % 8))); + } + bitsused++; + currbits--; + } + + /* Now generate the states for the entry being branched to. */ + if (i != NULL) + { + gen_dis_table (i); + } + + } + } + if (debug) + { + if (ent->skip_flag) + { + printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip); + } + + if (ent->bits[0] != NULL) + { + printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1, + zero_dest); + } + } + if (bitsused != totbits) + { + abort (); + } +} + +void +print_dis_table () +{ + int x; + struct disent *cent = disinsntable; + + printf ("static const char dis_table[] = {\n"); + for (x = 0; x < insn_list_len; x++) + { + if ((x > 0) && ((x % 12) == 0)) + { + printf ("\n"); + } + printf ("0x%02x, ", insn_list[x]); + } + printf ("\n};\n\n"); + + printf ("static const struct ia64_dis_names ia64_dis_names[] = {\n"); + while (cent != NULL) + { + struct disent *ent = cent; + + while (ent != NULL) + { + printf ("{ 0x%x, %d, %d },\n", ent->completer_index, + ent->insn, + (ent->nexte != NULL ? 1 : 0)); + ent = ent->nexte; + } + cent = cent->next_ent; + } + printf ("};\n\n"); +} + +void +generate_disassembler () +{ + int mainnum = 0; + struct main_entry *ptr = maintable; + + bittree = make_bittree_entry (); + + while (ptr != NULL) + { + if (ptr->opcode->type != IA64_TYPE_DYN) + { + add_dis_entry (bittree, + ptr->opcode->opcode, ptr->opcode->mask, mainnum, + ptr->completers, 1); + } + mainnum++; + ptr = ptr->next; + } + + compact_distree (bittree); + finish_distable (); + gen_dis_table (bittree); + + print_dis_table (); +} + +void +print_string_table () +{ + int x; + char lbuf[80], buf[80]; + int blen = 0; + + printf ("static const char *ia64_strings[] = {\n"); + lbuf[0] = '\0'; + for (x = 0; x < strtablen; x++) + { + int len; + + if (strlen (string_table[x]->s) > 75) + { + abort (); + } + sprintf (buf, " \"%s\",", string_table[x]->s); + len = strlen (buf); + if ((blen + len) > 75) + { + printf (" %s\n", lbuf); + lbuf[0] = '\0'; + blen = 0; + } + strcat (lbuf, buf); + blen += len; + } + if (blen > 0) + { + printf (" %s\n", lbuf); + } + printf ("};\n\n"); +} + +static struct completer_entry **glist; +static int glistlen = 0; +static int glisttotlen = 0; + +/* If the completer trees ENT1 and ENT2 are equal, return 1. */ + +int +completer_entries_eq (ent1, ent2) + struct completer_entry *ent1, *ent2; +{ + while (ent1 != NULL && ent2 != NULL) + { + if (ent1->name->num != ent2->name->num + || ent1->bits != ent2->bits + || ent1->mask != ent2->mask + || ent1->is_terminal != ent2->is_terminal + || ent1->dependencies != ent2->dependencies) + { + return 0; + } + if (! completer_entries_eq (ent1->addl_entries, ent2->addl_entries)) + { + return 0; + } + ent1 = ent1->alternative; + ent2 = ent2->alternative; + } + return ent1 == ent2; +} + +/* Insert ENT into the global list of completers and return it. If an + equivalent entry (according to completer_entries_eq) already exists, + it is returned instead. */ +struct completer_entry * +insert_gclist (ent) + struct completer_entry *ent; +{ + if (ent != NULL) + { + int i; + int x; + int start = 0, end; + + ent->addl_entries = insert_gclist (ent->addl_entries); + ent->alternative = insert_gclist (ent->alternative); + + i = glistlen / 2; + end = glistlen; + + if (glisttotlen == glistlen) + { + glisttotlen += 20; + glist = (struct completer_entry **) + xrealloc (glist, sizeof (struct completer_entry *) * glisttotlen); + } + + if (glistlen == 0) + { + glist[0] = ent; + glistlen = 1; + return ent; + } + + if (ent->name->num < glist[0]->name->num) + { + i = 0; + } + else if (ent->name->num > glist[end - 1]->name->num) + { + i = end; + } + else + { + int c; + + while (1) + { + i = (start + end) / 2; + c = ent->name->num - glist[i]->name->num; + if (c < 0) + { + end = i - 1; + } + else if (c == 0) + { + while (i > 0 + && ent->name->num == glist[i - 1]->name->num) + { + i--; + } + break; + } + else + { + start = i + 1; + } + if (start > end) + { + break; + } + } + if (c == 0) + { + while (i < glistlen) + { + if (ent->name->num != glist[i]->name->num) + { + break; + } + if (completer_entries_eq (ent, glist[i])) + { + return glist[i]; + } + i++; + } + } + } + for (; i > 0 && i < glistlen; i--) + { + if (ent->name->num >= glist[i - 1]->name->num) + { + break; + } + } + for (; i < glistlen; i++) + { + if (ent->name->num < glist[i]->name->num) + { + break; + } + } + for (x = glistlen - 1; x >= i; x--) + { + glist[x + 1] = glist[x]; + } + glist[i] = ent; + glistlen++; + } + return ent; +} + +static int +get_prefix_len (name) + const char *name; +{ + char *c; + + if (name[0] == '\0') + { + return 0; + } + + c = strchr (name, '.'); + if (c != NULL) + { + return c - name; + } + else + { + return strlen (name); + } +} + +static void +compute_completer_bits (ment, ent) + struct main_entry *ment; + struct completer_entry *ent; +{ + while (ent != NULL) + { + compute_completer_bits (ment, ent->addl_entries); + + if (ent->is_terminal) + { + ia64_insn mask = 0; + ia64_insn our_bits = ent->bits; + struct completer_entry *p = ent->parent; + ia64_insn p_bits; + int x; + + while (p != NULL && ! p->is_terminal) + { + p = p->parent; + } + + if (p != NULL) + { + p_bits = p->bits; + } + else + { + p_bits = ment->opcode->opcode; + } + + for (x = 0; x < 64; x++) + { + ia64_insn m = ((ia64_insn) 1) << x; + if ((p_bits & m) != (our_bits & m)) + { + mask |= m; + } + else + { + our_bits &= ~m; + } + } + ent->bits = our_bits; + ent->mask = mask; + } + else + { + ent->bits = 0; + ent->mask = 0; + } + + ent = ent->alternative; + } +} + +/* Find identical completer trees that are used in different + instructions and collapse their entries. */ +void +collapse_redundant_completers () +{ + struct main_entry *ptr; + int x; + + for (ptr = maintable; ptr != NULL; ptr = ptr->next) + { + if (ptr->completers == NULL) + { + abort (); + } + compute_completer_bits (ptr, ptr->completers); + ptr->completers = insert_gclist (ptr->completers); + } + + /* The table has been finalized, now number the indexes. */ + for (x = 0; x < glistlen; x++) + { + glist[x]->num = x; + } +} + + +/* attach two lists of dependencies to each opcode. + 1) all resources which, when already marked in use, conflict with this + opcode (chks) + 2) all resources which must be marked in use when this opcode is used + (regs) +*/ +int +insert_opcode_dependencies (opc, cmp) + struct ia64_opcode *opc; + struct completer_entry *cmp; +{ + /* note all resources which point to this opcode. rfi has the most chks + (79) and cmpxchng has the most regs (54) so 100 here should be enough */ + int i; + int nregs = 0; + unsigned short regs[256]; + int nchks = 0; + unsigned short chks[256]; + /* flag insns for which no class matched; there should be none */ + int no_class_found = 1; + + for (i=0;i < rdepslen;i++) + { + struct rdep *rs = rdeps[i]; + int j; + + if (strcmp (opc->name, "cmp.eq.and") == 0 + && strncmp (rs->name, "PR%", 3) == 0 + && rs->mode == 1) + no_class_found = 99; + + for (j=0; j < rs->nregs;j++) + { + int ic_note = 0; + + if (in_iclass (opc, ics[rs->regs[j]], NULL, NULL, &ic_note)) + { + /* We can ignore ic_note 11 for non PR resources */ + if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) + ic_note = 0; + + if (ic_note != 0 && rs->regnotes[j] != 0 + && ic_note != rs->regnotes[j] + && !(ic_note == 11 && rs->regnotes[j] == 1)) + fprintf (stderr, "Warning: IC note %d in opcode %s (IC:%s)" + " conflicts with resource %s note %d\n", + ic_note, opc->name, ics[rs->regs[j]]->name, + rs->name, rs->regnotes[j]); + /* Instruction class notes override resource notes. + So far, only note 11 applies to an IC instead of a resource, + and note 11 implies note 1. + */ + if (ic_note) + regs[nregs++] = RDEP(ic_note, i); + else + regs[nregs++] = RDEP(rs->regnotes[j], i); + no_class_found = 0; + ++rs->total_regs; + } + } + for (j=0;j < rs->nchks;j++) + { + int ic_note = 0; + + if (in_iclass (opc, ics[rs->chks[j]], NULL, NULL, &ic_note)) + { + /* We can ignore ic_note 11 for non PR resources */ + if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) + ic_note = 0; + + if (ic_note != 0 && rs->chknotes[j] != 0 + && ic_note != rs->chknotes[j] + && !(ic_note == 11 && rs->chknotes[j] == 1)) + fprintf (stderr, "Warning: IC note %d for opcode %s (IC:%s)" + " conflicts with resource %s note %d\n", + ic_note, opc->name, ics[rs->chks[j]]->name, + rs->name, rs->chknotes[j]); + if (ic_note) + chks[nchks++] = RDEP(ic_note, i); + else + chks[nchks++] = RDEP(rs->chknotes[j], i); + no_class_found = 0; + ++rs->total_chks; + } + } + } + + if (no_class_found) + fprintf (stderr, "Warning: opcode %s has no class (ops %d %d %d)\n", + opc->name, + opc->operands[0], opc->operands[1], opc->operands[2]); + + return insert_dependencies (nchks, chks, nregs, regs); +} + +void +insert_completer_entry (opc, tabent) + struct ia64_opcode *opc; + struct main_entry *tabent; +{ + struct completer_entry **ptr = &tabent->completers; + struct completer_entry *parent = NULL; + char pcopy[129], *prefix; + int at_end = 0; + + if (strlen (opc->name) > 128) + { + abort (); + } + strcpy (pcopy, opc->name); + prefix = pcopy + get_prefix_len (pcopy); + if (prefix[0] != '\0') + { + prefix++; + } + + while (! at_end) + { + int need_new_ent = 1; + int plen = get_prefix_len (prefix); + struct string_entry *sent; + + at_end = (prefix[plen] == '\0'); + prefix[plen] = '\0'; + sent = insert_string (prefix); + + while (*ptr != NULL) + { + int cmpres = sent->num - (*ptr)->name->num; + + if (cmpres == 0) + { + need_new_ent = 0; + break; + } + else if (cmpres < 0) + { + break; + } + else + { + ptr = &((*ptr)->alternative); + } + } + if (need_new_ent) + { + struct completer_entry *nent = tmalloc (struct completer_entry); + nent->name = sent; + nent->parent = parent; + nent->addl_entries = NULL; + nent->alternative = *ptr; + *ptr = nent; + nent->is_terminal = 0; + nent->dependencies = -1; + } + + if (! at_end) + { + parent = *ptr; + ptr = &((*ptr)->addl_entries); + prefix += plen + 1; + } + } + + if ((*ptr)->is_terminal) + { + abort (); + } + + (*ptr)->is_terminal = 1; + (*ptr)->mask = (ia64_insn)-1; + (*ptr)->bits = opc->opcode; + + (*ptr)->dependencies = insert_opcode_dependencies (opc, *ptr); +} + +void +print_completer_entry (ent) + struct completer_entry *ent; +{ + int moffset = 0; + ia64_insn mask = ent->mask, bits = ent->bits; + + if (mask != 0) + { + while (! (mask & 1)) + { + moffset++; + mask = mask >> 1; + bits = bits >> 1; + } + if (bits & 0xffffffff00000000LL) + { + abort (); + } + } + + printf (" { 0x%x, 0x%x, %d, %d, %d, %d, %d, %d },\n", + (int)bits, + (int)mask, + ent->name->num, + ent->alternative != NULL ? ent->alternative->num : -1, + ent->addl_entries != NULL ? ent->addl_entries->num : -1, + moffset, + ent->is_terminal ? 1 : 0, + ent->dependencies); +} + +void +print_completer_table () +{ + int x; + + printf ("static const struct ia64_completer_table\ncompleter_table[] = {\n"); + for (x = 0; x < glistlen; x++) + { + print_completer_entry (glist[x]); + } + printf ("};\n\n"); +} + +int +opcodes_eq (opc1, opc2) + struct ia64_opcode *opc1; + struct ia64_opcode *opc2; +{ + int x; + int plen1, plen2; + + if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type) + || (opc1->num_outputs != opc2->num_outputs) + || (opc1->flags != opc2->flags)) + { + return 0; + } + for (x = 0; x < 5; x++) + { + if (opc1->operands[x] != opc2->operands[x]) + { + return 0; + } + } + plen1 = get_prefix_len (opc1->name); + plen2 = get_prefix_len (opc2->name); + if (plen1 == plen2 && (memcmp (opc1->name, opc2->name, plen1) == 0)) + { + return 1; + } + return 0; +} + +void +add_opcode_entry (opc) + struct ia64_opcode *opc; +{ + struct main_entry **place; + struct string_entry *name; + char prefix[129]; + int found_it = 0; + + if (strlen (opc->name) > 128) + { + abort (); + } + place = &maintable; + strcpy (prefix, opc->name); + prefix[get_prefix_len (prefix)] = '\0'; + name = insert_string (prefix); + + /* Walk the list of opcode table entries. If it's a new + instruction, allocate and fill in a new entry. */ + + while (*place != NULL) + { + if ((*place)->name->num == name->num + && opcodes_eq ((*place)->opcode, opc)) + { + found_it = 1; + break; + } + if ((*place)->name->num > name->num) + { + break; + } + place = &((*place)->next); + } + if (! found_it) + { + struct main_entry *nent = tmalloc (struct main_entry); + + nent->name = name; + nent->opcode = opc; + nent->next = *place; + nent->completers = 0; + *place = nent; + } + insert_completer_entry (opc, *place); +} + +void +print_main_table () +{ + struct main_entry *ptr = maintable; + + printf ("static const struct ia64_main_table\nmain_table[] = {\n"); + while (ptr != NULL) + { + printf (" { %d, %d, %d, 0x%llxull, 0x%llxull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n", + ptr->name->num, + ptr->opcode->type, + ptr->opcode->num_outputs, + ptr->opcode->opcode, + ptr->opcode->mask, + ptr->opcode->operands[0], + ptr->opcode->operands[1], + ptr->opcode->operands[2], + ptr->opcode->operands[3], + ptr->opcode->operands[4], + ptr->opcode->flags, + ptr->completers->num); + + ptr = ptr->next; + } + printf ("};\n\n"); +} + +void +shrink (table) + struct ia64_opcode *table; +{ + int curr_opcode; + + for (curr_opcode = 0; table[curr_opcode].name != NULL; curr_opcode++) + { + add_opcode_entry (table + curr_opcode); + } +} + +int +main (int argc, char **argv) +{ + if (argc > 1) + { + debug = 1; + } + + load_insn_classes(); + load_dependencies(); + + shrink (ia64_opcodes_a); + shrink (ia64_opcodes_b); + shrink (ia64_opcodes_f); + shrink (ia64_opcodes_i); + shrink (ia64_opcodes_m); + shrink (ia64_opcodes_x); + shrink (ia64_opcodes_d); + + collapse_redundant_completers (); + + printf ("/* This file is automatically generated by ia64-gen. Do not edit! */\n"); + print_string_table (); + print_dependency_table (); + print_completer_table (); + print_main_table (); + + generate_disassembler (); + + exit (0); +} diff --git a/opcodes/ia64-ic.tbl b/opcodes/ia64-ic.tbl new file mode 100644 index 0000000..021194a --- /dev/null +++ b/opcodes/ia64-ic.tbl @@ -0,0 +1,205 @@ +Class; Events/Instructions +all; IC:predicatable-instructions, IC:unpredicatable-instructions +branches; IC:indirect-brs, IC:ip-rel-brs +cfm-readers; IC:fr-readers, IC:fr-writers, IC:gr-readers, IC:gr-writers, IC:mod-sched-brs, IC:predicatable-instructions, IC:pr-writers, alloc, br.call, brl.call, br.ret, cover, loadrs, rfi, IC:chk-a, invala.e +chk-a; chk.a.clr, chk.a.nc +cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8 +czx; czx1, czx2 +fcmp-s0; fcmp[Field(sf)==s0] +fcmp-s1; fcmp[Field(sf)==s1] +fcmp-s2; fcmp[Field(sf)==s2] +fcmp-s3; fcmp[Field(sf)==s3] +fetchadd; fetchadd4, fetchadd8 +fp-arith; fadd, famax, famin, fcvt.fx, fcvt.fxu, fcvt.xuf, fma, fmax, fmin, fmpy, fms, fnma, fnmpy, fnorm, fpamax, fpamin, fpcvt.fx, fpcvt.fxu, fpma, fpmax, fpmin, fpmpy, fpms, fpnma, fpnmpy, fprcpa, fprsqrta, frcpa, frsqrta, fsub +fp-arith-s0; IC:fp-arith[Field(sf)==s0] +fp-arith-s1; IC:fp-arith[Field(sf)==s1] +fp-arith-s2; IC:fp-arith[Field(sf)==s2] +fp-arith-s3; IC:fp-arith[Field(sf)==s3] +fp-non-arith; fabs, fand, fandcm, fclass, fcvt.xf, fmerge, fmix, fneg, fnegabs, for, fpabs, fpmerge, fpack, fpneg, fpnegabs, fselect, fswap, fsxt, fxor, xma +fpcmp-s0; fpcmp[Field(sf)==s0] +fpcmp-s1; fpcmp[Field(sf)==s1] +fpcmp-s2; fpcmp[Field(sf)==s2] +fpcmp-s3; fpcmp[Field(sf)==s3] +fr-readers; IC:fp-arith, IC:fp-non-arith, IC:pr-writers-fp, chk.s[Format in {M21}], getf +fr-writers; IC:fp-arith, IC:fp-non-arith\fclass, IC:mem-readers-fp +gr-readers; IC:gr-readers-writers, IC:mem-readers, IC:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC:mov-to-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-to-PR-allreg, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:probe-all, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, setf, tbit, tnat +gr-readers-writers; IC:mov-from-IND, add, addl, addp4, adds, and, andcm, IC:czx, dep\dep[Format in {I13}], extr, IC:mem-readers-int, IC:ld-all-postinc, IC:lfetch-postinc, IC:mix, IC:mux, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-nofault, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, shl, shladd, shladdp4, shr, shrp, IC:st-postinc, sub, IC:sxt, tak, thash, tpa, ttag, IC:unpack, xor, IC:zxt +gr-writers; alloc, dep, getf, IC:gr-readers-writers, IC:mem-readers-int, IC:mov-from-AR, IC:mov-from-BR, IC:mov-from-CR, IC:mov-from-PR, IC:mov-immediate, IC:mov-from-PSR, IC:mov-from-PSR-um, IC:mov-ip, movl +indirect-brp; brp[Format in {B7}] +indirect-brs; br.call[Format in {B5}], br.cond[Format in {B4}], br.ia, br.ret +invala-all; invala[Format in {M24}], invala.e +ip-rel-brs; IC:mod-sched-brs, br.call[Format in {B3}], brl.call, brl.cond, br.cond[Format in {B1}], br.cloop +ld; ld1, ld2, ld4, ld8, ld8.fill +ld-a; ld1.a, ld2.a, ld4.a, ld8.a +ld-all-postinc; IC:ld[Format in {M2 M3}], IC:ldfp[Format in {M12}], IC:ldf[Format in {M7 M8}] +ld-c; IC:ld-c-nc, IC:ld-c-clr +ld-c-clr; ld1.c.clr, ld2.c.clr, ld4.c.clr, ld8.c.clr, IC:ld-c-clr-acq +ld-c-clr-acq; ld1.c.clr.acq, ld2.c.clr.acq, ld4.c.clr.acq, ld8.c.clr.acq +ld-c-nc; ld1.c.nc, ld2.c.nc, ld4.c.nc, ld8.c.nc +ld-s; ld1.s, ld2.s, ld4.s, ld8.s +ld-sa; ld1.sa, ld2.sa, ld4.sa, ld8.sa +ldf; ldfs, ldfd, ldfe, ldf8, ldf.fill +ldf-a; ldfs.a, ldfd.a, ldfe.a, ldf8.a +ldf-c; IC:ldf-c-nc, IC:ldf-c-clr +ldf-c-clr; ldfs.c.clr, ldfd.c.clr, ldfe.c.clr, ldf8.c.clr +ldf-c-nc; ldfs.c.nc, ldfd.c.nc, ldfe.c.nc, ldf8.c.nc +ldf-s; ldfs.s, ldfd.s, ldfe.s, ldf8.s +ldf-sa; ldfs.sa, ldfd.sa, ldfe.sa, ldf8.sa +ldfp; ldfps, ldfpd, ldfp8 +ldfp-a; ldfps.a, ldfpd.a, ldfp8.a +ldfp-c; IC:ldfp-c-nc, IC:ldfp-c-clr +ldfp-c-clr; ldfps.c.clr, ldfpd.c.clr, ldfp8.c.clr +ldfp-c-nc; ldfps.c.nc, ldfpd.c.nc, ldfp8.c.nc +ldfp-s; ldfps.s, ldfpd.s, ldfp8.s +ldfp-sa; ldfps.sa, ldfpd.sa, ldfp8.sa +lfetch-all; lfetch +lfetch-fault; lfetch[Field(lftype)==fault] +lfetch-nofault; lfetch[Field(lftype)==] +lfetch-postinc; lfetch[Format in {M14 M15}] +mem-readers; IC:mem-readers-fp, IC:mem-readers-int +mem-readers-alat; IC:ld-a, IC:ldf-a, IC:ldfp-a, IC:ld-sa, IC:ldf-sa, IC:ldfp-sa, IC:ld-c, IC:ldf-c, IC:ldfp-c +mem-readers-fp; IC:ldf, IC:ldfp +mem-readers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:ld +mem-readers-spec; IC:ld-s, IC:ld-sa, IC:ldf-s, IC:ldf-sa, IC:ldfp-s, IC:ldfp-sa +mem-writers; IC:mem-writers-fp, IC:mem-writers-int +mem-writers-fp; IC:stf +mem-writers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:st +mix; mix1, mix2, mix4 +mod-sched-brs; br.cexit, br.ctop, br.wexit, br.wtop +mod-sched-brs-counted; br.cexit, br.cloop, br.ctop +mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM +mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP] +mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE] +mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV] +mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) == EC] +mov-from-AR-FPSR; IC:mov-from-AR-M[Field(ar3) == FPSR] +mov-from-AR-I; mov_ar[Format in {I28}] +mov-from-AR-ig; IC:mov-from-AR-IM[Field(ar3) in {48-63 112-127}] +mov-from-AR-IM; mov_ar[Format in {I28 M31}] +mov-from-AR-ITC; IC:mov-from-AR-M[Field(ar3) == ITC] +mov-from-AR-K; IC:mov-from-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}] +mov-from-AR-LC; IC:mov-from-AR-I[Field(ar3) == LC] +mov-from-AR-M; mov_ar[Format in {M31}] +mov-from-AR-PFS; IC:mov-from-AR-I[Field(ar3) == PFS] +mov-from-AR-RNAT; IC:mov-from-AR-M[Field(ar3) == RNAT] +mov-from-AR-RSC; IC:mov-from-AR-M[Field(ar3) == RSC] +mov-from-AR-rv; IC:none +mov-from-AR-UNAT; IC:mov-from-AR-M[Field(ar3) == UNAT] +mov-from-BR; mov_br[Format in {I22}] +mov-from-CR; mov_cr[Format in {M33}] +mov-from-CR-CMCV; IC:mov-from-CR[Field(cr3) == CMCV] +mov-from-CR-DCR; IC:mov-from-CR[Field(cr3) == DCR] +mov-from-CR-EOI; IC:mov-from-CR[Field(cr3) == EOI] +mov-from-CR-GPTA; IC:mov-from-CR[Field(cr3) == GPTA] +mov-from-CR-IFA; IC:mov-from-CR[Field(cr3) == IFA] +mov-from-CR-IFS; IC:mov-from-CR[Field(cr3) == IFS] +mov-from-CR-IHA; IC:mov-from-CR[Field(cr3) == IHA] +mov-from-CR-IIM; IC:mov-from-CR[Field(cr3) == IIM] +mov-from-CR-IIP; IC:mov-from-CR[Field(cr3) == IIP] +mov-from-CR-IIPA; IC:mov-from-CR[Field(cr3) == IIPA] +mov-from-CR-IPSR; IC:mov-from-CR[Field(cr3) == IPSR] +mov-from-CR-IRR; IC:mov-from-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}] +mov-from-CR-ISR; IC:mov-from-CR[Field(cr3) == ISR] +mov-from-CR-ITIR; IC:mov-from-CR[Field(cr3) == ITIR] +mov-from-CR-ITM; IC:mov-from-CR[Field(cr3) == ITM] +mov-from-CR-ITV; IC:mov-from-CR[Field(cr3) == ITV] +mov-from-CR-IVA; IC:mov-from-CR[Field(cr3) == IVA] +mov-from-CR-IVR; IC:mov-from-CR[Field(cr3) == IVR] +mov-from-CR-LID; IC:mov-from-CR[Field(cr3) == LID] +mov-from-CR-LRR; IC:mov-from-CR[Field(cr3) in {LRR0 LRR1}] +mov-from-CR-PMV; IC:mov-from-CR[Field(cr3) == PMV] +mov-from-CR-PTA; IC:mov-from-CR[Field(cr3) == PTA] +mov-from-CR-rv; IC:none +mov-from-CR-TPR; IC:mov-from-CR[Field(cr3) == TPR] +mov-from-IND; mov_indirect[Format in {M43}] +mov-from-IND-CPUID; IC:mov-from-IND[Field(ireg) == cpuid] +mov-from-IND-DBR; IC:mov-from-IND[Field(ireg) == dbr] +mov-from-IND-IBR; IC:mov-from-IND[Field(ireg) == ibr] +mov-from-IND-MSR; IC:mov-from-IND[Field(ireg) == msr] +mov-from-IND-PKR; IC:mov-from-IND[Field(ireg) == pkr] +mov-from-IND-PMC; IC:mov-from-IND[Field(ireg) == pmc] +mov-from-IND-PMD; IC:mov-from-IND[Field(ireg) == pmd] +mov-from-IND-priv; IC:mov-from-IND[Field(ireg) in {dbr ibr msr pkr pmc rr}] +mov-from-IND-RR; IC:mov-from-IND[Field(ireg) == rr] +mov-from-PR; mov_pr[Format in {I25}] +mov-from-PSR; mov_psr[Format in {M36}] +mov-from-PSR-um; mov_um[Format in {M36}] +mov-immediate; addl[Format in {A5}] +mov-ip; mov_ip[Format in {I25}] +mov-to-AR; IC:mov-to-AR-M, IC:mov-to-AR-I +mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) == BSP] +mov-to-AR-BSPSTORE; IC:mov-to-AR-M[Field(ar3) == BSPSTORE] +mov-to-AR-CCV; IC:mov-to-AR-M[Field(ar3) == CCV] +mov-to-AR-EC; IC:mov-to-AR-I[Field(ar3) == EC] +mov-to-AR-FPSR; IC:mov-to-AR-M[Field(ar3) == FPSR] +mov-to-AR-gr; IC:mov-to-AR-M[Format in {M29}], IC:mov-to-AR-I[Format in {I26}] +mov-to-AR-I; mov_ar[Format in {I26 I27}] +mov-to-AR-ig; IC:mov-to-AR-IM[Field(ar3) in {48-63 112-127}] +mov-to-AR-IM; mov_ar[Format in {I26 I27 M29 M30}] +mov-to-AR-ITC; IC:mov-to-AR-M[Field(ar3) == ITC] +mov-to-AR-K; IC:mov-to-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}] +mov-to-AR-LC; IC:mov-to-AR-I[Field(ar3) == LC] +mov-to-AR-M; mov_ar[Format in {M29 M30}] +mov-to-AR-PFS; IC:mov-to-AR-I[Field(ar3) == PFS] +mov-to-AR-RNAT; IC:mov-to-AR-M[Field(ar3) == RNAT] +mov-to-AR-RSC; IC:mov-to-AR-M[Field(ar3) == RSC] +mov-to-AR-UNAT; IC:mov-to-AR-M[Field(ar3) == UNAT] +mov-to-BR; mov_br[Format in {I21}] +mov-to-CR; mov_cr[Format in {M32}] +mov-to-CR-CMCV; IC:mov-to-CR[Field(cr3) == CMCV] +mov-to-CR-DCR; IC:mov-to-CR[Field(cr3) == DCR] +mov-to-CR-EOI; IC:mov-to-CR[Field(cr3) == EOI] +mov-to-CR-GPTA; IC:mov-to-CR[Field(cr3) == GPTA] +mov-to-CR-IFA; IC:mov-to-CR[Field(cr3) == IFA] +mov-to-CR-IFS; IC:mov-to-CR[Field(cr3) == IFS] +mov-to-CR-IHA; IC:mov-to-CR[Field(cr3) == IHA] +mov-to-CR-IIM; IC:mov-to-CR[Field(cr3) == IIM] +mov-to-CR-IIP; IC:mov-to-CR[Field(cr3) == IIP] +mov-to-CR-IIPA; IC:mov-to-CR[Field(cr3) == IIPA] +mov-to-CR-IPSR; IC:mov-to-CR[Field(cr3) == IPSR] +mov-to-CR-IRR; IC:mov-to-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}] +mov-to-CR-ISR; IC:mov-to-CR[Field(cr3) == ISR] +mov-to-CR-ITIR; IC:mov-to-CR[Field(cr3) == ITIR] +mov-to-CR-ITM; IC:mov-to-CR[Field(cr3) == ITM] +mov-to-CR-ITV; IC:mov-to-CR[Field(cr3) == ITV] +mov-to-CR-IVA; IC:mov-to-CR[Field(cr3) == IVA] +mov-to-CR-IVR; IC:mov-to-CR[Field(cr3) == IVR] +mov-to-CR-LID; IC:mov-to-CR[Field(cr3) == LID] +mov-to-CR-LRR; IC:mov-to-CR[Field(cr3) in {LRR0 LRR1}] +mov-to-CR-PMV; IC:mov-to-CR[Field(cr3) == PMV] +mov-to-CR-PTA; IC:mov-to-CR[Field(cr3) == PTA] +mov-to-CR-TPR; IC:mov-to-CR[Field(cr3) == TPR] +mov-to-IND; mov_indirect[Format in {M42}] +mov-to-IND-CPUID; IC:mov-to-IND[Field(ireg) == cpuid] +mov-to-IND-DBR; IC:mov-to-IND[Field(ireg) == dbr] +mov-to-IND-IBR; IC:mov-to-IND[Field(ireg) == ibr] +mov-to-IND-MSR; IC:mov-to-IND[Field(ireg) == msr] +mov-to-IND-PKR; IC:mov-to-IND[Field(ireg) == pkr] +mov-to-IND-PMC; IC:mov-to-IND[Field(ireg) == pmc] +mov-to-IND-PMD; IC:mov-to-IND[Field(ireg) == pmd] +mov-to-IND-priv; IC:mov-to-IND +mov-to-IND-RR; IC:mov-to-IND[Field(ireg) == rr] +mov-to-PR; IC:mov-to-PR-allreg, IC:mov-to-PR-rotreg +mov-to-PR-allreg; mov_pr[Format in {I23}] +mov-to-PR-rotreg; mov_pr[Format in {I24}] +mov-to-PSR-l; mov_psr[Format in {M35}] +mov-to-PSR-um; mov_um[Format in {M35}] +mux; mux1, mux2 +none; - +pack; pack2, pack4 +padd; padd1, padd2, padd4 +pavg; pavg1, pavg2 +pavgsub; pavgsub1, pavgsub2 +pcmp; pcmp1, pcmp2, pcmp4 +pmax; pmax1, pmax2 +pmin; pmin1, pmin2 +pmpy; pmpy2 +pmpyshr; pmpyshr2 +pr-and-writers; IC:pr-gen-writers-int[Field(ctype) in {and andcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}] +pr-gen-writers-fp; fclass, fcmp +pr-gen-writers-int; cmp, cmp4, tbit, tnat +pr-norm-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==] +pr-norm-writers-int; IC:pr-gen-writers-int[Field(ctype)==] +pr-or-writers; IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}] +pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, break, nop.b, nop, IC:ReservedBQP +pr-readers-nobr-nomovpr; add, addp4, and, andcm, break.f, break.i, break.m, break.x, break, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-immediate, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, nop, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, \ No newline at end of file diff --git a/opcodes/ia64-opc-a.c b/opcodes/ia64-opc-a.c new file mode 100644 index 0000000..8df8029 --- /dev/null +++ b/opcodes/ia64-opc-a.c @@ -0,0 +1,364 @@ +/* ia64-opc-a.c -- IA-64 `A' opcode table. + Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define A IA64_TYPE_A, 1 +#define A2 IA64_TYPE_A, 2 + +/* instruction bit fields: */ +#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bImm14(x) ((((ia64_insn) (((x) >> 0) & 0x7f)) << 13) | \ + (((ia64_insn) (((x) >> 7) & 0x3f)) << 27) | \ + (((ia64_insn) (((x) >> 13) & 0x01)) << 36)) +#define bR3a(x) (((ia64_insn) ((x) & 0x7f)) << 20) +#define bR3b(x) (((ia64_insn) ((x) & 0x3)) << 20) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 27) +#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 29) +#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) + +/* instruction bit masks: */ +#define mC bC (-1) +#define mImm14 bImm14 (-1) +#define mR3a bR3a (-1) +#define mR3b bR3b (-1) +#define mTa bTa (-1) +#define mTb bTb (-1) +#define mVe bVe (-1) +#define mX bX (-1) +#define mX2 bX2 (-1) +#define mX2a bX2a (-1) +#define mX2b bX2b (-1) +#define mX4 bX4 (-1) +#define mZa bZa (-1) +#define mZb bZb (-1) + +#define OpR3b(a,b) (bOp (a) | bR3b (b)), (mOp | mR3b) +#define OpX2aVe(a,b,c) (bOp (a) | bX2a (b) | bVe (c)), \ + (mOp | mX2a | mVe) +#define OpX2aVeR3a(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \ + (mOp | mX2a | mVe | mR3a) +#define OpX2aVeImm14(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \ + (mOp | mX2a | mVe | mImm14) +#define OpX2aVeX4(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \ + (mOp | mX2a | mVe | mX4) +#define OpX2aVeX4X2b(a,b,c,d,e) \ + (bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \ + (mOp | mX2a | mVe | mX4 | mX2b) +#define OpX2TbTaC(a,b,c,d,e) \ + (bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \ + (mOp | mX2 | mTb | mTa | mC) +#define OpX2TaC(a,b,c,d) (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \ + (mOp | mX2 | mTa | mC) +#define OpX2aZaZbX4(a,b,c,d,e) \ + (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \ + (mOp | mX2a | mZa | mZb | mX4) +#define OpX2aZaZbX4X2b(a,b,c,d,e,f) \ + (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \ + (mOp | mX2a | mZa | mZb | mX4 | mX2b) + +struct ia64_opcode ia64_opcodes_a[] = + { + /* A-type instruction encodings (sorted according to major opcode) */ + + {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}}, + {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}}, + {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}}, + {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}}, + {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}}, + {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}}, + {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}}, + {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}}, + {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}}, + {"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}}, + {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}}, + {"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}}, + {"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}}, + {"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}}, + {"mov", A, OpX2aVeR3a (8, 2, 0, 0), {R1, IMM14}, PSEUDO}, + {"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}}, + {"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}}, + {"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}}, + {"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}}, + {"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}}, + {"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}}, + {"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}}, + {"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}}, + {"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}}, + {"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}}, + {"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}}, + {"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}}, + {"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}}, + {"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}}, + {"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}}, + {"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}}, + {"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}}, + {"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}}, + {"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}}, + {"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}}, + {"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}}, + {"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}}, + {"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}}, + {"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}}, + {"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}}, + {"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}}, + {"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}}, + {"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}}, + {"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}}, + {"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}}, + {"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}}, + {"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}}, + {"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}}, + {"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}}, + + {"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO}, + {"addl", A, Op (9), {R1, IMM22, R3_2}}, + + {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}}, + {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}}, + {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}}, + {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}}, + {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, + {"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, + {"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}}, + {"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}}, + {"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}}, + {"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}}, + {"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, + {"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, + {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}}, + {"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}}, + {"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}}, + {"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}}, + {"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}}, + {"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}}, + {"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}}, + {"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}}, + {"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}}, + {"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}}, + {"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}}, + {"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}}, + {"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, + {"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, + {"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}}, + {"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}}, + {"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}}, + {"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}}, + {"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, + {"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, + {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, + {"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}}, + {"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}}, + {"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}}, + {"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}}, + {"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}}, + {"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}}, + {"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}}, + {"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}}, + {"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}}, + {"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}}, + {"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}}, + {"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}}, + {"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, + {"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO}, + {"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO}, + {"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}}, + {"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}}, + {"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}}, + {"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}}, + {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}}, + {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO}, + {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}}, + {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO}, + {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}}, + {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}}, + {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}}, + {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}}, + {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO}, + {"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO}, + {"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO}, + {"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}}, + {"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}}, + {"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}}, + {"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}}, + {"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3}}, + {"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO}, + {"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3}}, + {"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO}, + + {0} + }; + +#undef A +#undef A2 +#undef bC +#undef bImm14 +#undef bR3a +#undef bR3b +#undef bTa +#undef bTb +#undef bVe +#undef bX +#undef bX2 +#undef bX2a +#undef bX2b +#undef bX4 +#undef bZa +#undef bZb +#undef mC +#undef mImm14 +#undef mR3a +#undef mR3b +#undef mTa +#undef mTb +#undef mVe +#undef mX +#undef mX2 +#undef mX2a +#undef mX2b +#undef mX4 +#undef mZa +#undef mZb +#undef OpR3a +#undef OpR3b +#undef OpX2aVe +#undef OpX2aVeImm14 +#undef OpX2aVeX4 +#undef OpX2aVeX4X2b +#undef OpX2TbTaC +#undef OpX2TaC +#undef OpX2aZaZbX4 +#undef OpX2aZaZbX4X2b diff --git a/opcodes/ia64-opc-b.c b/opcodes/ia64-opc-b.c new file mode 100644 index 0000000..5277663 --- /dev/null +++ b/opcodes/ia64-opc-b.c @@ -0,0 +1,486 @@ +/* ia64-opc-b.c -- IA-64 `B' opcode table. + Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define B0 IA64_TYPE_B, 0 +#define B IA64_TYPE_B, 1 + +/* instruction bit fields: */ +#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) +#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) +#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) +#define bWhb(x) (((ia64_insn) ((x) & 0x3)) << 3) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) + +#define mBtype bBtype (-1) +#define mD bD (-1) +#define mIh bIh (-1) +#define mPa bPa (-1) +#define mPr bPr (-1) +#define mWha bWha (-1) +#define mWhb bWhb (-1) +#define mX6 bX6 (-1) + +#define OpX6(a,b) (bOp (a) | bX6 (b)), (mOp | mX6) +#define OpPaWhaD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) +#define OpBtypePaWhaD(a,b,c,d,e) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ + (mOp | mBtype | mPa | mWha | mD) +#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ + (mOp | mBtype | mPa | mWha | mD | mPr) +#define OpX6BtypePaWhaD(a,b,c,d,e,f) \ + (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f)), \ + (mOp | mX6 | mBtype | mPa | mWha | mD) +#define OpX6BtypePaWhaDPr(a,b,c,d,e,f,g) \ + (bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f) | bPr (g)), \ + (mOp | mX6 | mBtype | mPa | mWha | mD | mPr) +#define OpIhWhb(a,b,c) \ + (bOp (a) | bIh (b) | bWhb (c)), \ + (mOp | mIh | mWhb) +#define OpX6IhWhb(a,b,c,d) \ + (bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \ + (mOp | mX6 | mIh | mWhb) + +struct ia64_opcode ia64_opcodes_b[] = + { + /* B-type instruction encodings (sorted according to major opcode) */ + +#define BR(a,b) \ + B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO + {"br.few", BR (0, 0)}, + {"br", BR (0, 0)}, + {"br.few.clr", BR (0, 1)}, + {"br.clr", BR (0, 1)}, + {"br.many", BR (1, 0)}, + {"br.many.clr", BR (1, 1)}, +#undef BR + +#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2} + {"br.cond.sptk.few", BR (0x20, 0, 0, 0, 0)}, + {"br.cond.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO}, + {"br.cond.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, + {"br.cond.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO}, + {"br.cond.spnt.few", BR (0x20, 0, 0, 1, 0)}, + {"br.cond.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO}, + {"br.cond.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, + {"br.cond.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO}, + {"br.cond.dptk.few", BR (0x20, 0, 0, 2, 0)}, + {"br.cond.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO}, + {"br.cond.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, + {"br.cond.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO}, + {"br.cond.dpnt.few", BR (0x20, 0, 0, 3, 0)}, + {"br.cond.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO}, + {"br.cond.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, + {"br.cond.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO}, + {"br.cond.sptk.many", BR (0x20, 0, 1, 0, 0)}, + {"br.cond.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, + {"br.cond.spnt.many", BR (0x20, 0, 1, 1, 0)}, + {"br.cond.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, + {"br.cond.dptk.many", BR (0x20, 0, 1, 2, 0)}, + {"br.cond.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, + {"br.cond.dpnt.many", BR (0x20, 0, 1, 3, 0)}, + {"br.cond.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, + {"br.sptk.few", BR (0x20, 0, 0, 0, 0)}, + {"br.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO}, + {"br.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, + {"br.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO}, + {"br.spnt.few", BR (0x20, 0, 0, 1, 0)}, + {"br.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO}, + {"br.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, + {"br.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO}, + {"br.dptk.few", BR (0x20, 0, 0, 2, 0)}, + {"br.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO}, + {"br.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, + {"br.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO}, + {"br.dpnt.few", BR (0x20, 0, 0, 3, 0)}, + {"br.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO}, + {"br.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, + {"br.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO}, + {"br.sptk.many", BR (0x20, 0, 1, 0, 0)}, + {"br.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, + {"br.spnt.many", BR (0x20, 0, 1, 1, 0)}, + {"br.spnt.many.clr", BR (0x20, 0, 1, 1, 1)}, + {"br.dptk.many", BR (0x20, 0, 1, 2, 0)}, + {"br.dptk.many.clr", BR (0x20, 0, 1, 2, 1)}, + {"br.dpnt.many", BR (0x20, 0, 1, 3, 0)}, + {"br.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, + {"br.ia.sptk.few", BR (0x20, 1, 0, 0, 0)}, + {"br.ia.sptk", BR (0x20, 1, 0, 0, 0), PSEUDO}, + {"br.ia.sptk.few.clr", BR (0x20, 1, 0, 0, 1)}, + {"br.ia.sptk.clr", BR (0x20, 1, 0, 0, 1), PSEUDO}, + {"br.ia.spnt.few", BR (0x20, 1, 0, 1, 0)}, + {"br.ia.spnt", BR (0x20, 1, 0, 1, 0), PSEUDO}, + {"br.ia.spnt.few.clr", BR (0x20, 1, 0, 1, 1)}, + {"br.ia.spnt.clr", BR (0x20, 1, 0, 1, 1), PSEUDO}, + {"br.ia.dptk.few", BR (0x20, 1, 0, 2, 0)}, + {"br.ia.dptk", BR (0x20, 1, 0, 2, 0), PSEUDO}, + {"br.ia.dptk.few.clr", BR (0x20, 1, 0, 2, 1)}, + {"br.ia.dptk.clr", BR (0x20, 1, 0, 2, 1), PSEUDO}, + {"br.ia.dpnt.few", BR (0x20, 1, 0, 3, 0)}, + {"br.ia.dpnt", BR (0x20, 1, 0, 3, 0), PSEUDO}, + {"br.ia.dpnt.few.clr", BR (0x20, 1, 0, 3, 1)}, + {"br.ia.dpnt.clr", BR (0x20, 1, 0, 3, 1), PSEUDO}, + {"br.ia.sptk.many", BR (0x20, 1, 1, 0, 0)}, + {"br.ia.sptk.many.clr", BR (0x20, 1, 1, 0, 1)}, + {"br.ia.spnt.many", BR (0x20, 1, 1, 1, 0)}, + {"br.ia.spnt.many.clr", BR (0x20, 1, 1, 1, 1)}, + {"br.ia.dptk.many", BR (0x20, 1, 1, 2, 0)}, + {"br.ia.dptk.many.clr", BR (0x20, 1, 1, 2, 1)}, + {"br.ia.dpnt.many", BR (0x20, 1, 1, 3, 0)}, + {"br.ia.dpnt.many.clr", BR (0x20, 1, 1, 3, 1)}, + {"br.ret.sptk.few", BR (0x21, 4, 0, 0, 0), MOD_RRBS}, + {"br.ret.sptk", BR (0x21, 4, 0, 0, 0), PSEUDO | MOD_RRBS}, + {"br.ret.sptk.few.clr", BR (0x21, 4, 0, 0, 1), MOD_RRBS}, + {"br.ret.sptk.clr", BR (0x21, 4, 0, 0, 1), PSEUDO | MOD_RRBS}, + {"br.ret.spnt.few", BR (0x21, 4, 0, 1, 0), MOD_RRBS}, + {"br.ret.spnt", BR (0x21, 4, 0, 1, 0), PSEUDO | MOD_RRBS}, + {"br.ret.spnt.few.clr", BR (0x21, 4, 0, 1, 1), MOD_RRBS}, + {"br.ret.spnt.clr", BR (0x21, 4, 0, 1, 1), PSEUDO | MOD_RRBS}, + {"br.ret.dptk.few", BR (0x21, 4, 0, 2, 0), MOD_RRBS}, + {"br.ret.dptk", BR (0x21, 4, 0, 2, 0), PSEUDO | MOD_RRBS}, + {"br.ret.dptk.few.clr", BR (0x21, 4, 0, 2, 1), MOD_RRBS}, + {"br.ret.dptk.clr", BR (0x21, 4, 0, 2, 1), PSEUDO | MOD_RRBS}, + {"br.ret.dpnt.few", BR (0x21, 4, 0, 3, 0), MOD_RRBS}, + {"br.ret.dpnt", BR (0x21, 4, 0, 3, 0), PSEUDO | MOD_RRBS}, + {"br.ret.dpnt.few.clr", BR (0x21, 4, 0, 3, 1), MOD_RRBS}, + {"br.ret.dpnt.clr", BR (0x21, 4, 0, 3, 1), PSEUDO | MOD_RRBS}, + {"br.ret.sptk.many", BR (0x21, 4, 1, 0, 0), MOD_RRBS}, + {"br.ret.sptk.many.clr", BR (0x21, 4, 1, 0, 1), MOD_RRBS}, + {"br.ret.spnt.many", BR (0x21, 4, 1, 1, 0), MOD_RRBS}, + {"br.ret.spnt.many.clr", BR (0x21, 4, 1, 1, 1), MOD_RRBS}, + {"br.ret.dptk.many", BR (0x21, 4, 1, 2, 0), MOD_RRBS}, + {"br.ret.dptk.many.clr", BR (0x21, 4, 1, 2, 1), MOD_RRBS}, + {"br.ret.dpnt.many", BR (0x21, 4, 1, 3, 0), MOD_RRBS}, + {"br.ret.dpnt.many.clr", BR (0x21, 4, 1, 3, 1), MOD_RRBS}, +#undef BR + + {"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS}, + {"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS}, + {"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS}, + {"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS}, + {"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV}, + {"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV}, + {"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED}, + + {"break.b", B0, OpX6 (0, 0x00), {IMMU21}}, + + {"br.call.sptk.few", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}}, + {"br.call.sptk", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}, PSEUDO}, + {"br.call.sptk.few.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}}, + {"br.call.sptk.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}, PSEUDO}, + {"br.call.spnt.few", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}}, + {"br.call.spnt", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}, PSEUDO}, + {"br.call.spnt.few.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}}, + {"br.call.spnt.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}, PSEUDO}, + {"br.call.dptk.few", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}}, + {"br.call.dptk", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}, PSEUDO}, + {"br.call.dptk.few.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}}, + {"br.call.dptk.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}, PSEUDO}, + {"br.call.dpnt.few", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}}, + {"br.call.dpnt", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}, PSEUDO}, + {"br.call.dpnt.few.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}}, + {"br.call.dpnt.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}, PSEUDO}, + {"br.call.sptk.many", B, OpPaWhaD (1, 1, 0, 0), {B1, B2}}, + {"br.call.sptk.many.clr", B, OpPaWhaD (1, 1, 0, 1), {B1, B2}}, + {"br.call.spnt.many", B, OpPaWhaD (1, 1, 1, 0), {B1, B2}}, + {"br.call.spnt.many.clr", B, OpPaWhaD (1, 1, 1, 1), {B1, B2}}, + {"br.call.dptk.many", B, OpPaWhaD (1, 1, 2, 0), {B1, B2}}, + {"br.call.dptk.many.clr", B, OpPaWhaD (1, 1, 2, 1), {B1, B2}}, + {"br.call.dpnt.many", B, OpPaWhaD (1, 1, 3, 0), {B1, B2}}, + {"br.call.dpnt.many.clr", B, OpPaWhaD (1, 1, 3, 1), {B1, B2}}, + +#define BRP(a,b,c) \ + B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED + {"brp.sptk", BRP (0x10, 0, 0)}, + {"brp.dptk", BRP (0x10, 0, 2)}, + {"brp.sptk.imp", BRP (0x10, 1, 0)}, + {"brp.dptk.imp", BRP (0x10, 1, 2)}, + {"brp.ret.sptk", BRP (0x11, 0, 0)}, + {"brp.ret.dptk", BRP (0x11, 0, 2)}, + {"brp.ret.sptk.imp", BRP (0x11, 1, 0)}, + {"brp.ret.dptk.imp", BRP (0x11, 1, 2)}, +#undef BRP + + {"nop.b", B0, OpX6 (2, 0x00), {IMMU21}}, + +#define BR(a,b) \ + B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO + {"br.few", BR (0, 0)}, + {"br", BR (0, 0)}, + {"br.few.clr", BR (0, 1)}, + {"br.clr", BR (0, 1)}, + {"br.many", BR (1, 0)}, + {"br.many.clr", BR (1, 1)}, +#undef BR + + {"br.cond.sptk.few", B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}}, + {"br.cond.sptk", B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}, PSEUDO}, + {"br.cond.sptk.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}}, + {"br.cond.sptk.clr", B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}, PSEUDO}, + {"br.cond.spnt.few", B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}}, + {"br.cond.spnt", B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}, PSEUDO}, + {"br.cond.spnt.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}}, + {"br.cond.spnt.clr", B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}, PSEUDO}, + {"br.cond.dptk.few", B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}}, + {"br.cond.dptk", B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}, PSEUDO}, + {"br.cond.dptk.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}}, + {"br.cond.dptk.clr", B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}, PSEUDO}, + {"br.cond.dpnt.few", B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}}, + {"br.cond.dpnt", B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}, PSEUDO}, + {"br.cond.dpnt.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}}, + {"br.cond.dpnt.clr", B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}, PSEUDO}, + {"br.cond.sptk.many", B0, OpBtypePaWhaD (4, 0, 1, 0, 0), {TGT25c}}, + {"br.cond.sptk.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 0, 1), {TGT25c}}, + {"br.cond.spnt.many", B0, OpBtypePaWhaD (4, 0, 1, 1, 0), {TGT25c}}, + {"br.cond.spnt.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 1, 1), {TGT25c}}, + {"br.cond.dptk.many", B0, OpBtypePaWhaD (4, 0, 1, 2, 0), {TGT25c}}, + {"br.cond.dptk.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 2, 1), {TGT25c}}, + {"br.cond.dpnt.many", B0, OpBtypePaWhaD (4, 0, 1, 3, 0), {TGT25c}}, + {"br.cond.dpnt.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 3, 1), {TGT25c}}, + {"br.sptk.few", B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}}, + {"br.sptk", B0, OpBtypePaWhaD (4, 0, 0, 0, 0), {TGT25c}, PSEUDO}, + {"br.sptk.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}}, + {"br.sptk.clr", B0, OpBtypePaWhaD (4, 0, 0, 0, 1), {TGT25c}, PSEUDO}, + {"br.spnt.few", B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}}, + {"br.spnt", B0, OpBtypePaWhaD (4, 0, 0, 1, 0), {TGT25c}, PSEUDO}, + {"br.spnt.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}}, + {"br.spnt.clr", B0, OpBtypePaWhaD (4, 0, 0, 1, 1), {TGT25c}, PSEUDO}, + {"br.dptk.few", B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}}, + {"br.dptk", B0, OpBtypePaWhaD (4, 0, 0, 2, 0), {TGT25c}, PSEUDO}, + {"br.dptk.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}}, + {"br.dptk.clr", B0, OpBtypePaWhaD (4, 0, 0, 2, 1), {TGT25c}, PSEUDO}, + {"br.dpnt.few", B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}}, + {"br.dpnt", B0, OpBtypePaWhaD (4, 0, 0, 3, 0), {TGT25c}, PSEUDO}, + {"br.dpnt.few.clr", B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}}, + {"br.dpnt.clr", B0, OpBtypePaWhaD (4, 0, 0, 3, 1), {TGT25c}, PSEUDO}, + {"br.sptk.many", B0, OpBtypePaWhaD (4, 0, 1, 0, 0), {TGT25c}}, + {"br.sptk.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 0, 1), {TGT25c}}, + {"br.spnt.many", B0, OpBtypePaWhaD (4, 0, 1, 1, 0), {TGT25c}}, + {"br.spnt.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 1, 1), {TGT25c}}, + {"br.dptk.many", B0, OpBtypePaWhaD (4, 0, 1, 2, 0), {TGT25c}}, + {"br.dptk.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 2, 1), {TGT25c}}, + {"br.dpnt.many", B0, OpBtypePaWhaD (4, 0, 1, 3, 0), {TGT25c}}, + {"br.dpnt.many.clr", B0, OpBtypePaWhaD (4, 0, 1, 3, 1), {TGT25c}}, + +#define BR(a,b,c,d) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 + {"br.wexit.sptk.few", BR (2, 0, 0, 0) | MOD_RRBS}, + {"br.wexit.sptk", BR (2, 0, 0, 0) | PSEUDO | MOD_RRBS}, + {"br.wexit.sptk.few.clr", BR (2, 0, 0, 1) | MOD_RRBS}, + {"br.wexit.sptk.clr", BR (2, 0, 0, 1) | PSEUDO | MOD_RRBS}, + {"br.wexit.spnt.few", BR (2, 0, 1, 0) | MOD_RRBS}, + {"br.wexit.spnt", BR (2, 0, 1, 0) | PSEUDO | MOD_RRBS}, + {"br.wexit.spnt.few.clr", BR (2, 0, 1, 1) | MOD_RRBS}, + {"br.wexit.spnt.clr", BR (2, 0, 1, 1) | PSEUDO | MOD_RRBS}, + {"br.wexit.dptk.few", BR (2, 0, 2, 0) | MOD_RRBS}, + {"br.wexit.dptk", BR (2, 0, 2, 0) | PSEUDO | MOD_RRBS}, + {"br.wexit.dptk.few.clr", BR (2, 0, 2, 1) | MOD_RRBS}, + {"br.wexit.dptk.clr", BR (2, 0, 2, 1) | PSEUDO | MOD_RRBS}, + {"br.wexit.dpnt.few", BR (2, 0, 3, 0) | MOD_RRBS}, + {"br.wexit.dpnt", BR (2, 0, 3, 0) | PSEUDO | MOD_RRBS}, + {"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1) | MOD_RRBS}, + {"br.wexit.dpnt.clr", BR (2, 0, 3, 1) | PSEUDO | MOD_RRBS}, + {"br.wexit.sptk.many", BR (2, 1, 0, 0) | MOD_RRBS}, + {"br.wexit.sptk.many.clr", BR (2, 1, 0, 1) | MOD_RRBS}, + {"br.wexit.spnt.many", BR (2, 1, 1, 0) | MOD_RRBS}, + {"br.wexit.spnt.many.clr", BR (2, 1, 1, 1) | MOD_RRBS}, + {"br.wexit.dptk.many", BR (2, 1, 2, 0) | MOD_RRBS}, + {"br.wexit.dptk.many.clr", BR (2, 1, 2, 1) | MOD_RRBS}, + {"br.wexit.dpnt.many", BR (2, 1, 3, 0) | MOD_RRBS}, + {"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1) | MOD_RRBS}, + {"br.wtop.sptk.few", BR (3, 0, 0, 0) | MOD_RRBS}, + {"br.wtop.sptk", BR (3, 0, 0, 0) | PSEUDO | MOD_RRBS}, + {"br.wtop.sptk.few.clr", BR (3, 0, 0, 1) | MOD_RRBS}, + {"br.wtop.sptk.clr", BR (3, 0, 0, 1) | PSEUDO | MOD_RRBS}, + {"br.wtop.spnt.few", BR (3, 0, 1, 0) | MOD_RRBS}, + {"br.wtop.spnt", BR (3, 0, 1, 0) | PSEUDO | MOD_RRBS}, + {"br.wtop.spnt.few.clr", BR (3, 0, 1, 1) | MOD_RRBS}, + {"br.wtop.spnt.clr", BR (3, 0, 1, 1) | PSEUDO | MOD_RRBS}, + {"br.wtop.dptk.few", BR (3, 0, 2, 0) | MOD_RRBS}, + {"br.wtop.dptk", BR (3, 0, 2, 0) | PSEUDO | MOD_RRBS}, + {"br.wtop.dptk.few.clr", BR (3, 0, 2, 1) | MOD_RRBS}, + {"br.wtop.dptk.clr", BR (3, 0, 2, 1) | PSEUDO | MOD_RRBS}, + {"br.wtop.dpnt.few", BR (3, 0, 3, 0) | MOD_RRBS}, + {"br.wtop.dpnt", BR (3, 0, 3, 0) | PSEUDO | MOD_RRBS}, + {"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1) | MOD_RRBS}, + {"br.wtop.dpnt.clr", BR (3, 0, 3, 1) | PSEUDO | MOD_RRBS}, + {"br.wtop.sptk.many", BR (3, 1, 0, 0) | MOD_RRBS}, + {"br.wtop.sptk.many.clr", BR (3, 1, 0, 1) | MOD_RRBS}, + {"br.wtop.spnt.many", BR (3, 1, 1, 0) | MOD_RRBS}, + {"br.wtop.spnt.many.clr", BR (3, 1, 1, 1) | MOD_RRBS}, + {"br.wtop.dptk.many", BR (3, 1, 2, 0) | MOD_RRBS}, + {"br.wtop.dptk.many.clr", BR (3, 1, 2, 1) | MOD_RRBS}, + {"br.wtop.dpnt.many", BR (3, 1, 3, 0) | MOD_RRBS}, + {"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1) | MOD_RRBS}, + +#undef BR +#define BR(a,b,c,d) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED + {"br.cloop.sptk.few", BR (5, 0, 0, 0)}, + {"br.cloop.sptk", BR (5, 0, 0, 0) | PSEUDO}, + {"br.cloop.sptk.few.clr", BR (5, 0, 0, 1)}, + {"br.cloop.sptk.clr", BR (5, 0, 0, 1) | PSEUDO}, + {"br.cloop.spnt.few", BR (5, 0, 1, 0)}, + {"br.cloop.spnt", BR (5, 0, 1, 0) | PSEUDO}, + {"br.cloop.spnt.few.clr", BR (5, 0, 1, 1)}, + {"br.cloop.spnt.clr", BR (5, 0, 1, 1) | PSEUDO}, + {"br.cloop.dptk.few", BR (5, 0, 2, 0)}, + {"br.cloop.dptk", BR (5, 0, 2, 0) | PSEUDO}, + {"br.cloop.dptk.few.clr", BR (5, 0, 2, 1)}, + {"br.cloop.dptk.clr", BR (5, 0, 2, 1) | PSEUDO}, + {"br.cloop.dpnt.few", BR (5, 0, 3, 0)}, + {"br.cloop.dpnt", BR (5, 0, 3, 0) | PSEUDO}, + {"br.cloop.dpnt.few.clr", BR (5, 0, 3, 1)}, + {"br.cloop.dpnt.clr", BR (5, 0, 3, 1) | PSEUDO}, + {"br.cloop.sptk.many", BR (5, 1, 0, 0)}, + {"br.cloop.sptk.many.clr", BR (5, 1, 0, 1)}, + {"br.cloop.spnt.many", BR (5, 1, 1, 0)}, + {"br.cloop.spnt.many.clr", BR (5, 1, 1, 1)}, + {"br.cloop.dptk.many", BR (5, 1, 2, 0)}, + {"br.cloop.dptk.many.clr", BR (5, 1, 2, 1)}, + {"br.cloop.dpnt.many", BR (5, 1, 3, 0)}, + {"br.cloop.dpnt.many.clr", BR (5, 1, 3, 1)}, + {"br.cexit.sptk.few", BR (6, 0, 0, 0) | MOD_RRBS}, + {"br.cexit.sptk", BR (6, 0, 0, 0) | PSEUDO | MOD_RRBS}, + {"br.cexit.sptk.few.clr", BR (6, 0, 0, 1) | MOD_RRBS}, + {"br.cexit.sptk.clr", BR (6, 0, 0, 1) | PSEUDO | MOD_RRBS}, + {"br.cexit.spnt.few", BR (6, 0, 1, 0) | MOD_RRBS}, + {"br.cexit.spnt", BR (6, 0, 1, 0) | PSEUDO | MOD_RRBS}, + {"br.cexit.spnt.few.clr", BR (6, 0, 1, 1) | MOD_RRBS}, + {"br.cexit.spnt.clr", BR (6, 0, 1, 1) | PSEUDO | MOD_RRBS}, + {"br.cexit.dptk.few", BR (6, 0, 2, 0) | MOD_RRBS}, + {"br.cexit.dptk", BR (6, 0, 2, 0) | PSEUDO | MOD_RRBS}, + {"br.cexit.dptk.few.clr", BR (6, 0, 2, 1) | MOD_RRBS}, + {"br.cexit.dptk.clr", BR (6, 0, 2, 1) | PSEUDO | MOD_RRBS}, + {"br.cexit.dpnt.few", BR (6, 0, 3, 0) | MOD_RRBS}, + {"br.cexit.dpnt", BR (6, 0, 3, 0) | PSEUDO | MOD_RRBS}, + {"br.cexit.dpnt.few.clr", BR (6, 0, 3, 1) | MOD_RRBS}, + {"br.cexit.dpnt.clr", BR (6, 0, 3, 1) | PSEUDO | MOD_RRBS}, + {"br.cexit.sptk.many", BR (6, 1, 0, 0) | MOD_RRBS}, + {"br.cexit.sptk.many.clr", BR (6, 1, 0, 1) | MOD_RRBS}, + {"br.cexit.spnt.many", BR (6, 1, 1, 0) | MOD_RRBS}, + {"br.cexit.spnt.many.clr", BR (6, 1, 1, 1) | MOD_RRBS}, + {"br.cexit.dptk.many", BR (6, 1, 2, 0) | MOD_RRBS}, + {"br.cexit.dptk.many.clr", BR (6, 1, 2, 1) | MOD_RRBS}, + {"br.cexit.dpnt.many", BR (6, 1, 3, 0) | MOD_RRBS}, + {"br.cexit.dpnt.many.clr", BR (6, 1, 3, 1) | MOD_RRBS}, + {"br.ctop.sptk.few", BR (7, 0, 0, 0) | MOD_RRBS}, + {"br.ctop.sptk", BR (7, 0, 0, 0) | PSEUDO | MOD_RRBS}, + {"br.ctop.sptk.few.clr", BR (7, 0, 0, 1) | MOD_RRBS}, + {"br.ctop.sptk.clr", BR (7, 0, 0, 1) | PSEUDO | MOD_RRBS}, + {"br.ctop.spnt.few", BR (7, 0, 1, 0) | MOD_RRBS}, + {"br.ctop.spnt", BR (7, 0, 1, 0) | PSEUDO | MOD_RRBS}, + {"br.ctop.spnt.few.clr", BR (7, 0, 1, 1) | MOD_RRBS}, + {"br.ctop.spnt.clr", BR (7, 0, 1, 1) | PSEUDO | MOD_RRBS}, + {"br.ctop.dptk.few", BR (7, 0, 2, 0) | MOD_RRBS}, + {"br.ctop.dptk", BR (7, 0, 2, 0) | PSEUDO | MOD_RRBS}, + {"br.ctop.dptk.few.clr", BR (7, 0, 2, 1) | MOD_RRBS}, + {"br.ctop.dptk.clr", BR (7, 0, 2, 1) | PSEUDO | MOD_RRBS}, + {"br.ctop.dpnt.few", BR (7, 0, 3, 0) | MOD_RRBS}, + {"br.ctop.dpnt", BR (7, 0, 3, 0) | PSEUDO | MOD_RRBS}, + {"br.ctop.dpnt.few.clr", BR (7, 0, 3, 1) | MOD_RRBS}, + {"br.ctop.dpnt.clr", BR (7, 0, 3, 1) | PSEUDO | MOD_RRBS}, + {"br.ctop.sptk.many", BR (7, 1, 0, 0) | MOD_RRBS}, + {"br.ctop.sptk.many.clr", BR (7, 1, 0, 1) | MOD_RRBS}, + {"br.ctop.spnt.many", BR (7, 1, 1, 0) | MOD_RRBS}, + {"br.ctop.spnt.many.clr", BR (7, 1, 1, 1) | MOD_RRBS}, + {"br.ctop.dptk.many", BR (7, 1, 2, 0) | MOD_RRBS}, + {"br.ctop.dptk.many.clr", BR (7, 1, 2, 1) | MOD_RRBS}, + {"br.ctop.dpnt.many", BR (7, 1, 3, 0) | MOD_RRBS}, + {"br.ctop.dpnt.many.clr", BR (7, 1, 3, 1) | MOD_RRBS}, + +#undef BR +#define BR(a,b,c,d) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 + {"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}}, + {"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO}, + {"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}}, + {"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO}, + {"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}}, + {"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO}, + {"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}}, + {"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO}, + {"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}}, + {"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO}, + {"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}}, + {"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO}, + {"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}}, + {"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO}, + {"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}}, + {"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO}, + {"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}}, + {"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}}, + {"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}}, + {"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}}, + {"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}}, + {"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}}, + {"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}}, + {"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}}, +#undef BR + + /* branch predict */ +#define BRP(a,b) \ + B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED + {"brp.sptk", BRP (0, 0)}, + {"brp.loop", BRP (0, 1)}, + {"brp.dptk", BRP (0, 2)}, + {"brp.exit", BRP (0, 3)}, + {"brp.sptk.imp", BRP (1, 0)}, + {"brp.loop.imp", BRP (1, 1)}, + {"brp.dptk.imp", BRP (1, 2)}, + {"brp.exit.imp", BRP (1, 3)}, +#undef BRP + + {0} + }; + +#undef B0 +#undef B +#undef bBtype +#undef bD +#undef bIh +#undef bPa +#undef bPr +#undef bWha +#undef bWhb +#undef bX6 +#undef mBtype +#undef mD +#undef mIh +#undef mPa +#undef mPr +#undef mWha +#undef mWhb +#undef mX6 +#undef OpX6 +#undef OpPaWhaD +#undef OpBtypePaWhaD +#undef OpBtypePaWhaDPr +#undef OpX6BtypePaWhaD +#undef OpX6BtypePaWhaDPr +#undef OpIhWhb +#undef OpX6IhWhb diff --git a/opcodes/ia64-opc-d.c b/opcodes/ia64-opc-d.c new file mode 100644 index 0000000..6021d3b --- /dev/null +++ b/opcodes/ia64-opc-d.c @@ -0,0 +1,12 @@ +struct ia64_opcode ia64_opcodes_d[] = + { + {"add", IA64_TYPE_DYN, 1, 0, 0, + {IA64_OPND_R1, IA64_OPND_IMM22, IA64_OPND_R3}}, + {"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}}, + {"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}}, + {"nop", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}}, + {0} + }; diff --git a/opcodes/ia64-opc-f.c b/opcodes/ia64-opc-f.c new file mode 100644 index 0000000..5b9af51 --- /dev/null +++ b/opcodes/ia64-opc-f.c @@ -0,0 +1,625 @@ +/* ia64-opc-f.c -- IA-64 `F' opcode table. + Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define f0 IA64_TYPE_F, 0 +#define f IA64_TYPE_F, 1 +#define f2 IA64_TYPE_F, 2 + +#define bF2(x) (((ia64_insn) ((x) & 0x7f)) << 13) +#define bF4(x) (((ia64_insn) ((x) & 0x7f)) << 27) +#define bQ(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bRa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bRb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bSf(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bXa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) + +#define mF2 bF2 (-1) +#define mF4 bF4 (-1) +#define mQ bQ (-1) +#define mRa bRa (-1) +#define mRb bRb (-1) +#define mSf bSf (-1) +#define mTa bTa (-1) +#define mXa bXa (-1) +#define mXb bXb (-1) +#define mX2 bX2 (-1) +#define mX6 bX6 (-1) + +#define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa) +#define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf) +#define OpXaSfF2(a,b,c,d) \ + (bOp (a) | bXa (b) | bSf (c) | bF2 (d)), (mOp | mXa | mSf | mF2) +#define OpXaSfF4(a,b,c,d) \ + (bOp (a) | bXa (b) | bSf (c) | bF4 (d)), (mOp | mXa | mSf | mF4) +#define OpXaSfF2F4(a,b,c,d,e) \ + (bOp (a) | bXa (b) | bSf (c) | bF2 (d) | bF4 (e)), \ + (mOp | mXa | mSf | mF2 | mF4) +#define OpXaX2(a,b,c) (bOp (a) | bXa (b) | bX2 (c)), (mOp | mXa | mX2) +#define OpXaX2F2(a,b,c,d) \ + (bOp (a) | bXa (b) | bX2 (c) | bF2 (d)), (mOp | mXa | mX2 | mF2) +#define OpRaRbTaSf(a,b,c,d,e) \ + (bOp (a) | bRa (b) | bRb (c) | bTa (d) | bSf (e)), \ + (mOp | mRa | mRb | mTa | mSf) +#define OpTa(a,b) (bOp (a) | bTa (b)), (mOp | mTa) +#define OpXbQSf(a,b,c,d) \ + (bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf) +#define OpXbX6(a,b,c) \ + (bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6) +#define OpXbX6F2(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2) +#define OpXbX6Sf(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bSf (d)), (mOp | mXb | mX6 | mSf) + +struct ia64_opcode ia64_opcodes_f[] = + { + /* F-type instruction encodings (sorted according to major opcode) */ + + {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}}, + {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO}, + {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}}, + {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}}, + {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}}, + + {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}}, + {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO}, + {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}}, + {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}}, + {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}}, + + {"fmin.s0", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}}, + {"fmin", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO}, + {"fmin.s1", f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}}, + {"fmin.s2", f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}}, + {"fmin.s3", f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}}, + {"fmax.s0", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}}, + {"fmax", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO}, + {"fmax.s1", f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}}, + {"fmax.s2", f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}}, + {"fmax.s3", f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}}, + {"famin.s0", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}}, + {"famin", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO}, + {"famin.s1", f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}}, + {"famin.s2", f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}}, + {"famin.s3", f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}}, + {"famax.s0", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}}, + {"famax", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO}, + {"famax.s1", f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}}, + {"famax.s2", f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}}, + {"famax.s3", f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}}, + + {"mov", f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3}, + {"fabs", f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO}, + {"fmerge.s", f, OpXbX6 (0, 0, 0x10), {F1, F2, F3}}, + {"fneg", f, OpXbX6 (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3}, + {"fnegabs", f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO}, + {"fmerge.ns", f, OpXbX6 (0, 0, 0x11), {F1, F2, F3}}, + + {"fmerge.se", f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}}, + {"fmix.lr", f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}}, + {"fmix.r", f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}}, + {"fmix.l", f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}}, + {"fsxt.r", f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}}, + {"fsxt.l", f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}}, + {"fpack", f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}}, + {"fswap", f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}}, + {"fswap.nl", f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}}, + {"fswap.nr", f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}}, + {"fand", f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}}, + {"fandcm", f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}}, + {"for", f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}}, + {"fxor", f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}}, + + {"fcvt.fx.s0", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}}, + {"fcvt.fx", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO}, + {"fcvt.fx.s1", f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}}, + {"fcvt.fx.s2", f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}}, + {"fcvt.fx.s3", f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}}, + {"fcvt.fxu.s0", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}}, + {"fcvt.fxu", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO}, + {"fcvt.fxu.s1", f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}}, + {"fcvt.fxu.s2", f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}}, + {"fcvt.fxu.s3", f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}}, + {"fcvt.fx.trunc.s0", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}}, + {"fcvt.fx.trunc", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO}, + {"fcvt.fx.trunc.s1", f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}}, + {"fcvt.fx.trunc.s2", f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}}, + {"fcvt.fx.trunc.s3", f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}}, + {"fcvt.fxu.trunc.s0", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}}, + {"fcvt.fxu.trunc", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO}, + {"fcvt.fxu.trunc.s1", f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}}, + {"fcvt.fxu.trunc.s2", f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}}, + {"fcvt.fxu.trunc.s3", f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}}, + + {"fcvt.xf", f, OpXbX6 (0, 0, 0x1c), {F1, F2}}, + + {"fsetc.s0", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}}, + {"fsetc", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO}, + {"fsetc.s1", f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}}, + {"fsetc.s2", f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}}, + {"fsetc.s3", f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}}, + {"fclrf.s0", f0, OpXbX6Sf (0, 0, 0x05, 0)}, + {"fclrf", f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO}, + {"fclrf.s1", f0, OpXbX6Sf (0, 0, 0x05, 1)}, + {"fclrf.s2", f0, OpXbX6Sf (0, 0, 0x05, 2)}, + {"fclrf.s3", f0, OpXbX6Sf (0, 0, 0x05, 3)}, + {"fchkf.s0", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}}, + {"fchkf", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO}, + {"fchkf.s1", f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}}, + {"fchkf.s2", f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}}, + {"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}}, + + {"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}}, + {"nop.f", f0, OpXbX6 (0, 0, 0x01), {IMMU21}}, + + {"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}}, + {"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO}, + {"fprcpa.s1", f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}}, + {"fprcpa.s2", f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}}, + {"fprcpa.s3", f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}}, + + {"fprsqrta.s0", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}}, + {"fprsqrta", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO}, + {"fprsqrta.s1", f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}}, + {"fprsqrta.s2", f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}}, + {"fprsqrta.s3", f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}}, + + {"fpmin.s0", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}}, + {"fpmin", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO}, + {"fpmin.s1", f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}}, + {"fpmin.s2", f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}}, + {"fpmin.s3", f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}}, + {"fpmax.s0", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}}, + {"fpmax", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO}, + {"fpmax.s1", f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}}, + {"fpmax.s2", f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}}, + {"fpmax.s3", f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}}, + {"fpamin.s0", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}}, + {"fpamin", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO}, + {"fpamin.s1", f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}}, + {"fpamin.s2", f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}}, + {"fpamin.s3", f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}}, + {"fpamax.s0", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}}, + {"fpamax", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO}, + {"fpamax.s1", f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}}, + {"fpamax.s2", f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}}, + {"fpamax.s3", f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}}, + {"fpcmp.eq.s0", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}}, + {"fpcmp.eq", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.eq.s1", f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}}, + {"fpcmp.eq.s2", f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}}, + {"fpcmp.eq.s3", f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}}, + {"fpcmp.lt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}}, + {"fpcmp.lt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.lt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}}, + {"fpcmp.lt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}}, + {"fpcmp.lt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}}, + {"fpcmp.le.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}}, + {"fpcmp.le", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.le.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}}, + {"fpcmp.le.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}}, + {"fpcmp.le.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}}, + {"fpcmp.unord.s0", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}}, + {"fpcmp.unord", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.unord.s1", f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}}, + {"fpcmp.unord.s2", f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}}, + {"fpcmp.unord.s3", f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}}, + {"fpcmp.neq.s0", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}}, + {"fpcmp.neq", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.neq.s1", f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}}, + {"fpcmp.neq.s2", f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}}, + {"fpcmp.neq.s3", f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}}, + {"fpcmp.nlt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}}, + {"fpcmp.nlt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.nlt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}}, + {"fpcmp.nlt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}}, + {"fpcmp.nlt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}}, + {"fpcmp.nle.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}}, + {"fpcmp.nle", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.nle.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}}, + {"fpcmp.nle.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}}, + {"fpcmp.nle.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}}, + {"fpcmp.ord.s0", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}}, + {"fpcmp.ord", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO}, + {"fpcmp.ord.s1", f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}}, + {"fpcmp.ord.s2", f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}}, + {"fpcmp.ord.s3", f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}}, + + {"fpabs", f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO}, + {"fpmerge.s", f, OpXbX6 (1, 0, 0x10), {F1, F2, F3}}, + {"fpneg", f, OpXbX6 (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3}, + {"fpnegabs", f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO}, + {"fpmerge.ns", f, OpXbX6 (1, 0, 0x11), {F1, F2, F3}}, + {"fpmerge.se", f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}}, + + {"fpcvt.fx.s0", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}}, + {"fpcvt.fx", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO}, + {"fpcvt.fx.s1", f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}}, + {"fpcvt.fx.s2", f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}}, + {"fpcvt.fx.s3", f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}}, + {"fpcvt.fxu.s0", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}}, + {"fpcvt.fxu", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO}, + {"fpcvt.fxu.s1", f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}}, + {"fpcvt.fxu.s2", f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}}, + {"fpcvt.fxu.s3", f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}}, + {"fpcvt.fx.trunc.s0", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}}, + {"fpcvt.fx.trunc", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO}, + {"fpcvt.fx.trunc.s1", f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}}, + {"fpcvt.fx.trunc.s2", f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}}, + {"fpcvt.fx.trunc.s3", f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}}, + {"fpcvt.fxu.trunc.s0", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}}, + {"fpcvt.fxu.trunc", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO}, + {"fpcvt.fxu.trunc.s1", f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}}, + {"fpcvt.fxu.trunc.s2", f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}}, + {"fpcvt.fxu.trunc.s3", f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}}, + + {"fcmp.eq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}}, + {"fcmp.eq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.eq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}}, + {"fcmp.eq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}}, + {"fcmp.eq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}}, + {"fcmp.lt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}}, + {"fcmp.lt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.lt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}}, + {"fcmp.lt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}}, + {"fcmp.lt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}}, + {"fcmp.le.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}}, + {"fcmp.le", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.le.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}}, + {"fcmp.le.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}}, + {"fcmp.le.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}}, + {"fcmp.unord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}}, + {"fcmp.unord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.unord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}}, + {"fcmp.unord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}}, + {"fcmp.unord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}}, + {"fcmp.eq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}}, + {"fcmp.eq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.eq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3}}, + {"fcmp.eq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3}}, + {"fcmp.eq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3}}, + {"fcmp.lt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}}, + {"fcmp.lt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.lt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3}}, + {"fcmp.lt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3}}, + {"fcmp.lt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3}}, + {"fcmp.le.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}}, + {"fcmp.le.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.le.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3}}, + {"fcmp.le.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3}}, + {"fcmp.le.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3}}, + {"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}}, + {"fcmp.unord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO}, + {"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}}, + {"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}}, + {"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}}, + + /* pseudo-ops of the above */ + {"fcmp.gt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}}, + {"fcmp.gt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUDO}, + {"fcmp.gt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}}, + {"fcmp.gt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}}, + {"fcmp.gt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}}, + {"fcmp.ge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}}, + {"fcmp.ge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUDO}, + {"fcmp.ge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}}, + {"fcmp.ge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}}, + {"fcmp.ge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}}, + {"fcmp.neq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}}, + {"fcmp.neq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.neq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}}, + {"fcmp.neq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}}, + {"fcmp.neq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}}, + {"fcmp.nlt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}}, + {"fcmp.nlt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.nlt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}}, + {"fcmp.nlt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}}, + {"fcmp.nlt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}}, + {"fcmp.nle.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}}, + {"fcmp.nle", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.nle.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}}, + {"fcmp.nle.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}}, + {"fcmp.nle.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}}, + {"fcmp.ngt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}}, + {"fcmp.ngt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUDO}, + {"fcmp.ngt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}}, + {"fcmp.ngt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}}, + {"fcmp.ngt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}}, + {"fcmp.nge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}}, + {"fcmp.nge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUDO}, + {"fcmp.nge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}}, + {"fcmp.nge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}}, + {"fcmp.nge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}}, + {"fcmp.ord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}}, + {"fcmp.ord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.ord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}}, + {"fcmp.ord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}}, + {"fcmp.ord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}}, + {"fcmp.gt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}}, + {"fcmp.gt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PSEUDO}, + {"fcmp.gt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2}}, + {"fcmp.gt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2}}, + {"fcmp.gt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2}}, + {"fcmp.ge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}}, + {"fcmp.ge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PSEUDO}, + {"fcmp.ge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2}}, + {"fcmp.ge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2}}, + {"fcmp.ge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2}}, + {"fcmp.neq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}}, + {"fcmp.neq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.neq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}}, + {"fcmp.neq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}}, + {"fcmp.neq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}}, + {"fcmp.nlt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}}, + {"fcmp.nlt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.nlt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}}, + {"fcmp.nlt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}}, + {"fcmp.nlt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}}, + {"fcmp.nle.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}}, + {"fcmp.nle.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.nle.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}}, + {"fcmp.nle.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}}, + {"fcmp.nle.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}}, + {"fcmp.ngt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}}, + {"fcmp.ngt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, PSEUDO}, + {"fcmp.ngt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}}, + {"fcmp.ngt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}}, + {"fcmp.ngt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}}, + {"fcmp.nge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}}, + {"fcmp.nge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, PSEUDO}, + {"fcmp.nge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}}, + {"fcmp.nge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}}, + {"fcmp.nge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}}, + {"fcmp.ord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}}, + {"fcmp.ord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO}, + {"fcmp.ord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}}, + {"fcmp.ord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}}, + {"fcmp.ord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}}, + + {"fclass.m", f2, OpTa (5, 0), {P1, P2, F2, IMMU9}}, + {"fclass.nm", f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO}, + {"fclass.m.unc", f2, OpTa (5, 1), {P1, P2, F2, IMMU9}}, + {"fclass.nm.unc", f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO}, + + /* note: fnorm and fcvt.xuf have identical encodings! */ + {"fnorm.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fadd.s0", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s1", f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s2", f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s3", f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s.s0", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s.s1", f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s.s2", f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.s.s3", f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fmpy.s0", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s1", f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s2", f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s3", f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s.s0", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s.s1", f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s.s2", f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.s.s3", f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fma.s0", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}}, + {"fma", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fma.s1", f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}}, + {"fma.s2", f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}}, + {"fma.s3", f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}}, + {"fma.s.s0", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fma.s", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}}, + {"fma.s.s1", f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}}, + {"fma.s.s2", f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}}, + {"fma.s.s3", f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}}, + + {"fnorm.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fnorm.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO}, + {"fcvt.xuf.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO}, + {"fadd.d.s0", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.d", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.d.s1", f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.d.s2", f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fadd.d.s3", f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fmpy.d.s0", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.d", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.d.s1", f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.d.s2", f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fmpy.d.s3", f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fma.d.s0", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}}, + {"fma.d", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fma.d.s1", f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}}, + {"fma.d.s2", f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}}, + {"fma.d.s3", f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}}, + + {"fpmpy.s0", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fpmpy", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fpmpy.s1", f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fpmpy.s2", f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fpmpy.s3", f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fpma.s0", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}}, + {"fpma", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fpma.s1", f, OpXaSf (0x9, 1, 1), {F1, F3, F4, F2}}, + {"fpma.s2", f, OpXaSf (0x9, 1, 2), {F1, F3, F4, F2}}, + {"fpma.s3", f, OpXaSf (0x9, 1, 3), {F1, F3, F4, F2}}, + + {"fsub.s0", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s1", f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s2", f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s3", f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s.s0", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s.s1", f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s.s2", f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.s.s3", f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fms.s0", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}}, + {"fms", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fms.s1", f, OpXaSf (0xa, 0, 1), {F1, F3, F4, F2}}, + {"fms.s2", f, OpXaSf (0xa, 0, 2), {F1, F3, F4, F2}}, + {"fms.s3", f, OpXaSf (0xa, 0, 3), {F1, F3, F4, F2}}, + {"fms.s.s0", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}}, + {"fms.s", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fms.s.s1", f, OpXaSf (0xa, 1, 1), {F1, F3, F4, F2}}, + {"fms.s.s2", f, OpXaSf (0xa, 1, 2), {F1, F3, F4, F2}}, + {"fms.s.s3", f, OpXaSf (0xa, 1, 3), {F1, F3, F4, F2}}, + {"fsub.d.s0", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.d", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.d.s1", f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.d.s2", f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO}, + {"fsub.d.s3", f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO}, + {"fms.d.s0", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}}, + {"fms.d", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fms.d.s1", f, OpXaSf (0xb, 0, 1), {F1, F3, F4, F2}}, + {"fms.d.s2", f, OpXaSf (0xb, 0, 2), {F1, F3, F4, F2}}, + {"fms.d.s3", f, OpXaSf (0xb, 0, 3), {F1, F3, F4, F2}}, + + {"fpms.s0", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}}, + {"fpms", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fpms.s1", f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}}, + {"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}}, + {"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}}, + + {"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s2", f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s3", f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s.s0", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s.s1", f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s.s2", f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.s.s3", f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fnma.s0", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}}, + {"fnma", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fnma.s1", f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}}, + {"fnma.s2", f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}}, + {"fnma.s3", f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}}, + {"fnma.s.s0", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}}, + {"fnma.s", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fnma.s.s1", f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}}, + {"fnma.s.s2", f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}}, + {"fnma.s.s3", f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}}, + {"fnmpy.d.s0", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.d", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.d.s1", f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.d.s2", f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fnmpy.d.s3", f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fnma.d.s0", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}}, + {"fnma.d", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fnma.d.s1", f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}}, + {"fnma.d.s2", f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}}, + {"fnma.d.s3", f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}}, + + {"fpnmpy.s0", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fpnmpy", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"fpnmpy.s1", f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO}, + {"fpnmpy.s2", f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"fpnmpy.s3", f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"fpnma.s0", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}}, + {"fpnma", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"fpnma.s1", f, OpXaSf (0xd, 1, 1), {F1, F3, F4, F2}}, + {"fpnma.s2", f, OpXaSf (0xd, 1, 2), {F1, F3, F4, F2}}, + {"fpnma.s3", f, OpXaSf (0xd, 1, 3), {F1, F3, F4, F2}}, + + {"xmpy.l", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"xmpy.lu", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO}, + {"xmpy.h", f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO}, + {"xmpy.hu", f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO}, + {"xma.l", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}}, + {"xma.lu", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO}, + {"xma.h", f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}}, + {"xma.hu", f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}}, + + {"fselect", f, OpXa (0xe, 0), {F1, F3, F4, F2}}, + + {0} + }; + +#undef f0 +#undef f +#undef f2 +#undef bF2 +#undef bF4 +#undef bQ +#undef bRa +#undef bRb +#undef bSf +#undef bTa +#undef bXa +#undef bXb +#undef bX2 +#undef bX6 +#undef mF2 +#undef mF4 +#undef mQ +#undef mRa +#undef mRb +#undef mSf +#undef mTa +#undef mXa +#undef mXb +#undef mX2 +#undef mX6 +#undef OpXa +#undef OpXaSf +#undef OpXaSfF2 +#undef OpXaSfF4 +#undef OpXaSfF2F4 +#undef OpXaX2 +#undef OpRaRbTaSf +#undef OpTa +#undef OpXbQSf +#undef OpXbX6 +#undef OpXbX6F2 +#undef OpXbX6Sf diff --git a/opcodes/ia64-opc-i.c b/opcodes/ia64-opc-i.c new file mode 100644 index 0000000..2871920 --- /dev/null +++ b/opcodes/ia64-opc-i.c @@ -0,0 +1,296 @@ +/* ia64-opc-i.c -- IA-64 `I' opcode table. + Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define I0 IA64_TYPE_I, 0 +#define I IA64_TYPE_I, 1 +#define I2 IA64_TYPE_I, 2 + +/* instruction bit fields: */ +#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 23) +#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTag13(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) +#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 32) +#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33) +#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34) +#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28) +#define bX2c(x) (((ia64_insn) ((x) & 0x3)) << 30) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bYa(x) (((ia64_insn) ((x) & 0x1)) << 13) +#define bYb(x) (((ia64_insn) ((x) & 0x1)) << 26) +#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33) + +/* instruction bit masks: */ +#define mC bC (-1) +#define mIh bIh (-1) +#define mTa bTa (-1) +#define mTag13 bTag13 (-1) +#define mTb bTb (-1) +#define mVc bVc (-1) +#define mVe bVe (-1) +#define mWh bWh (-1) +#define mX bX (-1) +#define mXb bXb (-1) +#define mX2 bX2 (-1) +#define mX2a bX2a (-1) +#define mX2b bX2b (-1) +#define mX2c bX2c (-1) +#define mX3 bX3 (-1) +#define mX6 bX6 (-1) +#define mYa bYa (-1) +#define mYb bYb (-1) +#define mZa bZa (-1) +#define mZb bZb (-1) + +#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \ + (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \ + (mOp | mZa | mZb | mVe | mX2a | mX2b) +#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \ + (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \ + (mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c) +#define OpX2X(a,b,c) (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX) +#define OpX2XYa(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \ + (mOp | mX2 | mX | mYa) +#define OpX2XYb(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \ + (mOp | mX2 | mX | mYb) +#define OpX2TaTbYaC(a,b,c,d,e,f) \ + (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \ + (mOp | mX2 | mTa | mTb | mYa | mC) +#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) +#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ + (mOp | mX3 | mX6) +#define OpX3XbIhWh(a,b,c,d,e) \ + (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \ + (mOp | mX3 | mXb | mIh | mWh) +#define OpX3XbIhWhTag13(a,b,c,d,e,f) \ + (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \ + (mOp | mX3 | mXb | mIh | mWh | mTag13) + +struct ia64_opcode ia64_opcodes_i[] = + { + /* I-type instruction encodings (sorted according to major opcode) */ + + {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX}, + {"nop.i", I0, OpX3X6 (0, 0, 0x01), {IMMU21}, X_IN_MLX}, + {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}}, + + {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO}, +#define MOV(a,b,c,d) \ + I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b} + {"mov.sptk", MOV (7, 0, 0, 0)}, + {"mov.sptk.imp", MOV (7, 0, 1, 0)}, + {"mov", MOV (7, 0, 0, 1)}, + {"mov.imp", MOV (7, 0, 1, 1)}, + {"mov.dptk", MOV (7, 0, 0, 2)}, + {"mov.dptk.imp", MOV (7, 0, 1, 2)}, + {"mov.ret.sptk", MOV (7, 1, 0, 0)}, + {"mov.ret.sptk.imp", MOV (7, 1, 1, 0)}, + {"mov.ret", MOV (7, 1, 0, 1)}, + {"mov.ret.imp", MOV (7, 1, 1, 1)}, + {"mov.ret.dptk", MOV (7, 1, 0, 2)}, + {"mov.ret.dptk.imp", MOV (7, 1, 1, 2)}, +#undef MOV + {"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}}, + {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}}, + {"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}}, + {"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}}, + {"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}}, + {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}}, + {"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}}, + {"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}}, + {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}}, + {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}}, + {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}}, + {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}}, + {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}}, + {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}}, + {"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}}, + {"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}}, + {"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}}, + {"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}}, + + {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}}, + + {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}}, + + {"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6}, + PSEUDO | LEN_EQ_64MCNT}, + {"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}}, + + {"shr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6}, + PSEUDO | LEN_EQ_64MCNT}, + {"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}}, + + {"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a}, + PSEUDO | LEN_EQ_64MCNT}, + {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}}, + {"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}}, + {"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}}, +#define TBIT(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6} +#define TBITCM(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO + {"tbit.z", TBIT (0, 0, 0, 0)}, + {"tbit.nz", TBITCM (0, 0, 0, 0)}, + {"tbit.z.unc", TBIT (0, 0, 0, 1)}, + {"tbit.nz.unc", TBITCM (0, 0, 0, 1)}, + {"tbit.z.and", TBIT (0, 1, 0, 0)}, + {"tbit.nz.andcm", TBITCM (0, 1, 0, 0)}, + {"tbit.nz.and", TBIT (0, 1, 0, 1)}, + {"tbit.z.andcm", TBITCM (0, 1, 0, 1)}, + {"tbit.z.or", TBIT (1, 0, 0, 0)}, + {"tbit.nz.orcm", TBITCM (1, 0, 0, 0)}, + {"tbit.nz.or", TBIT (1, 0, 0, 1)}, + {"tbit.z.orcm", TBITCM (1, 0, 0, 1)}, + {"tbit.z.or.andcm", TBIT (1, 1, 0, 0)}, + {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)}, + {"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)}, + {"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)}, +#undef TBIT +#define TNAT(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3} +#define TNATCM(a,b,c,d) \ + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO + {"tnat.z", TNAT (0, 0, 1, 0)}, + {"tnat.nz", TNATCM (0, 0, 1, 0)}, + {"tnat.z.unc", TNAT (0, 0, 1, 1)}, + {"tnat.nz.unc", TNATCM (0, 0, 1, 1)}, + {"tnat.z.and", TNAT (0, 1, 1, 0)}, + {"tnat.nz.andcm", TNATCM (0, 1, 1, 0)}, + {"tnat.nz.and", TNAT (0, 1, 1, 1)}, + {"tnat.z.andcm", TNATCM (0, 1, 1, 1)}, + {"tnat.z.or", TNAT (1, 0, 1, 0)}, + {"tnat.nz.orcm", TNATCM (1, 0, 1, 0)}, + {"tnat.nz.or", TNAT (1, 0, 1, 1)}, + {"tnat.z.orcm", TNATCM (1, 0, 1, 1)}, + {"tnat.z.or.andcm", TNAT (1, 1, 1, 0)}, + {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)}, + {"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)}, + {"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)}, +#undef TNAT + + {"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}}, + {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}}, + {"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}}, + {"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}}, + {"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}}, + {"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}}, + {"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}}, + {"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}}, + {"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}}, + {"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}}, + {"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}}, + {"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}}, + {"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}}, + {"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}}, + {"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}}, + {"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}}, + {"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}}, + {"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}}, + {"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}}, + {"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}}, + {"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}}, + {"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}}, + {"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}}, + {"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}}, + {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}}, + {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}}, + {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}}, + {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}}, + {"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}}, + {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}}, + {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}}, + {"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}}, + {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}}, + {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}}, + {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}}, + {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}}, + {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}}, + {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}}, + {"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}}, + {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}}, + {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}}, + {"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}}, + + {0} + }; + +#undef I0 +#undef I +#undef I2 +#undef L +#undef bC +#undef bIh +#undef bTa +#undef bTag13 +#undef bTb +#undef bVc +#undef bVe +#undef bWh +#undef bX +#undef bXb +#undef bX2 +#undef bX2a +#undef bX2b +#undef bX2c +#undef bX3 +#undef bX6 +#undef bY +#undef bZa +#undef bZb +#undef mC +#undef mIh +#undef mTa +#undef mTag13 +#undef mTb +#undef mVc +#undef mVe +#undef mWh +#undef mX +#undef mXb +#undef mX2 +#undef mX2a +#undef mX2b +#undef mX2c +#undef mX3 +#undef mX6 +#undef mY +#undef mZa +#undef mZb +#undef OpZaZbVeX2aX2b +#undef OpZaZbVeX2aX2bX2c +#undef OpX2X +#undef OpX2XYa +#undef OpX2XYb +#undef OpX2TaTbYaC +#undef OpX3 +#undef OpX3X6 +#undef OpX3XbIhWh +#undef OpX3XbIhWhTag13 diff --git a/opcodes/ia64-opc-m.c b/opcodes/ia64-opc-m.c new file mode 100644 index 0000000..13a971e --- /dev/null +++ b/opcodes/ia64-opc-m.c @@ -0,0 +1,1042 @@ +/* ia64-opc-m.c -- IA-64 `M' opcode table. + Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +#define M0 IA64_TYPE_M, 0 +#define M IA64_TYPE_M, 1 +#define M2 IA64_TYPE_M, 2 + +/* instruction bit fields: */ +#define bM(x) (((ia64_insn) ((x) & 0x1)) << 36) +#define bX(x) (((ia64_insn) ((x) & 0x1)) << 27) +#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 31) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 27) +#define bX6a(x) (((ia64_insn) ((x) & 0x3f)) << 30) +#define bX6b(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bHint(x) (((ia64_insn) ((x) & 0x3)) << 28) + +#define mM bM (-1) +#define mX bX (-1) +#define mX2 bX2 (-1) +#define mX3 bX3 (-1) +#define mX4 bX4 (-1) +#define mX6a bX6a (-1) +#define mX6b bX6b (-1) +#define mHint bHint (-1) + +#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) +#define OpX3X6b(a,b,c) (bOp (a) | bX3 (b) | bX6b (c)), \ + (mOp | mX3 | mX6b) +#define OpX3X4(a,b,c) (bOp (a) | bX3 (b) | bX4 (c)), \ + (mOp | mX3 | mX4) +#define OpX3X4X2(a,b,c,d) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d)), \ + (mOp | mX3 | mX4 | mX2) +#define OpX6aHint(a,b,c) (bOp (a) | bX6a (b) | bHint (c)), \ + (mOp | mX6a | mHint) +#define OpXX6aHint(a,b,c,d) (bOp (a) | bX (b) | bX6a (c) | bHint (d)), \ + (mOp | mX | mX6a | mHint) +#define OpMXX6a(a,b,c,d) \ + (bOp (a) | bM (b) | bX (c) | bX6a (d)), (mOp | mM | mX | mX6a) +#define OpMXX6aHint(a,b,c,d,e) \ + (bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e)), \ + (mOp | mM | mX | mX6a | mHint) + +struct ia64_opcode ia64_opcodes_m[] = + { + /* M-type instruction encodings (sorted according to major opcode) */ + + {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}}, + {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}}, + {"chk.a.nc", M0, OpX3 (0, 6), {F1, TGT25c}}, + {"chk.a.clr", M0, OpX3 (0, 7), {F1, TGT25c}}, + + {"invala", M0, OpX3X4X2 (0, 0, 0, 1)}, + {"fwb", M0, OpX3X4X2 (0, 0, 0, 2)}, + {"mf", M0, OpX3X4X2 (0, 0, 2, 2)}, + {"mf.a", M0, OpX3X4X2 (0, 0, 3, 2)}, + {"srlz.d", M0, OpX3X4X2 (0, 0, 0, 3)}, + {"srlz.i", M0, OpX3X4X2 (0, 0, 1, 3)}, + {"sync.i", M0, OpX3X4X2 (0, 0, 3, 3)}, + {"flushrs", M0, OpX3X4X2 (0, 0, 0xc, 0), {0, }, FIRST | NO_PRED}, + {"loadrs", M0, OpX3X4X2 (0, 0, 0xa, 0), {0, }, FIRST | NO_PRED}, + {"invala.e", M0, OpX3X4X2 (0, 0, 2, 1), {R1}}, + {"invala.e", M0, OpX3X4X2 (0, 0, 3, 1), {F1}}, + {"mov.m", M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}}, + + {"break.m", M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}}, + {"nop.m", M0, OpX3X4X2 (0, 0, 1, 0), {IMMU21}}, + + {"sum", M0, OpX3X4 (0, 0, 4), {IMMU24}}, + {"rum", M0, OpX3X4 (0, 0, 5), {IMMU24}}, + {"ssm", M0, OpX3X4 (0, 0, 6), {IMMU24}, PRIV}, + {"rsm", M0, OpX3X4 (0, 0, 7), {IMMU24}, PRIV}, + + {"mov.m", M, OpX3X6b (1, 0, 0x2a), {AR3, R2}}, + {"mov.m", M, OpX3X6b (1, 0, 0x22), {R1, AR3}}, + {"mov", M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV}, + + {"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS}, + + {"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}}, + {"mov", M, OpX3X6b (1, 0, 0x25), {R1, PSR}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x21), {R1, PSR_UM}}, + {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}}, + {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}}, + {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}}, + {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}}, + {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}}, + {"probe.r.fault", M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}}, + {"probe.w.fault", M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}}, + {"itc.d", M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV}, + {"itc.i", M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV}, + + {"mov", M, OpX3X6b (1, 0, 0x00), {RR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x01), {DBR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x02), {IBR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x03), {PKR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x04), {PMC_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x05), {PMD_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x06), {MSR_R3, R2}, PRIV}, + {"itr.d", M, OpX3X6b (1, 0, 0x0e), {DTR_R3, R2}, PRIV}, + {"itr.i", M, OpX3X6b (1, 0, 0x0f), {ITR_R3, R2}, PRIV}, + + {"mov", M, OpX3X6b (1, 0, 0x10), {R1, RR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x11), {R1, DBR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x12), {R1, IBR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x13), {R1, PKR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x14), {R1, PMC_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x15), {R1, PMD_R3}}, + {"mov", M, OpX3X6b (1, 0, 0x16), {R1, MSR_R3}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x17), {R1, CPUID_R3}}, + + {"ptc.l", M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV}, + {"ptc.g", M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV}, + {"ptc.ga", M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV}, + {"ptr.d", M0, OpX3X6b (1, 0, 0x0c), {R3, R2}, PRIV}, + {"ptr.i", M0, OpX3X6b (1, 0, 0x0d), {R3, R2}, PRIV}, + + {"thash", M, OpX3X6b (1, 0, 0x1a), {R1, R3}}, + {"ttag", M, OpX3X6b (1, 0, 0x1b), {R1, R3}}, + {"tpa", M, OpX3X6b (1, 0, 0x1e), {R1, R3}, PRIV}, + {"tak", M, OpX3X6b (1, 0, 0x1f), {R1, R3}, PRIV}, + + {"chk.s.m", M0, OpX3 (1, 1), {R2, TGT25b}}, + {"chk.s", M0, OpX3 (1, 3), {F2, TGT25b}}, + + {"fc", M0, OpX3X6b (1, 0, 0x30), {R3}}, + {"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV}, + + /* integer load */ + {"ld1", M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}}, + {"ld1.nt1", M, OpMXX6aHint (4, 0, 0, 0x00, 1), {R1, MR3}}, + {"ld1.nta", M, OpMXX6aHint (4, 0, 0, 0x00, 3), {R1, MR3}}, + {"ld2", M, OpMXX6aHint (4, 0, 0, 0x01, 0), {R1, MR3}}, + {"ld2.nt1", M, OpMXX6aHint (4, 0, 0, 0x01, 1), {R1, MR3}}, + {"ld2.nta", M, OpMXX6aHint (4, 0, 0, 0x01, 3), {R1, MR3}}, + {"ld4", M, OpMXX6aHint (4, 0, 0, 0x02, 0), {R1, MR3}}, + {"ld4.nt1", M, OpMXX6aHint (4, 0, 0, 0x02, 1), {R1, MR3}}, + {"ld4.nta", M, OpMXX6aHint (4, 0, 0, 0x02, 3), {R1, MR3}}, + {"ld8", M, OpMXX6aHint (4, 0, 0, 0x03, 0), {R1, MR3}}, + {"ld8.nt1", M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}}, + {"ld8.nta", M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}}, + {"ld1.s", M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}}, + {"ld1.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}}, + {"ld1.s.nta", M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}}, + {"ld2.s", M, OpMXX6aHint (4, 0, 0, 0x05, 0), {R1, MR3}}, + {"ld2.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x05, 1), {R1, MR3}}, + {"ld2.s.nta", M, OpMXX6aHint (4, 0, 0, 0x05, 3), {R1, MR3}}, + {"ld4.s", M, OpMXX6aHint (4, 0, 0, 0x06, 0), {R1, MR3}}, + {"ld4.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x06, 1), {R1, MR3}}, + {"ld4.s.nta", M, OpMXX6aHint (4, 0, 0, 0x06, 3), {R1, MR3}}, + {"ld8.s", M, OpMXX6aHint (4, 0, 0, 0x07, 0), {R1, MR3}}, + {"ld8.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x07, 1), {R1, MR3}}, + {"ld8.s.nta", M, OpMXX6aHint (4, 0, 0, 0x07, 3), {R1, MR3}}, + {"ld1.a", M, OpMXX6aHint (4, 0, 0, 0x08, 0), {R1, MR3}}, + {"ld1.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x08, 1), {R1, MR3}}, + {"ld1.a.nta", M, OpMXX6aHint (4, 0, 0, 0x08, 3), {R1, MR3}}, + {"ld2.a", M, OpMXX6aHint (4, 0, 0, 0x09, 0), {R1, MR3}}, + {"ld2.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x09, 1), {R1, MR3}}, + {"ld2.a.nta", M, OpMXX6aHint (4, 0, 0, 0x09, 3), {R1, MR3}}, + {"ld4.a", M, OpMXX6aHint (4, 0, 0, 0x0a, 0), {R1, MR3}}, + {"ld4.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0a, 1), {R1, MR3}}, + {"ld4.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0a, 3), {R1, MR3}}, + {"ld8.a", M, OpMXX6aHint (4, 0, 0, 0x0b, 0), {R1, MR3}}, + {"ld8.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0b, 1), {R1, MR3}}, + {"ld8.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0b, 3), {R1, MR3}}, + {"ld1.sa", M, OpMXX6aHint (4, 0, 0, 0x0c, 0), {R1, MR3}}, + {"ld1.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0c, 1), {R1, MR3}}, + {"ld1.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0c, 3), {R1, MR3}}, + {"ld2.sa", M, OpMXX6aHint (4, 0, 0, 0x0d, 0), {R1, MR3}}, + {"ld2.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0d, 1), {R1, MR3}}, + {"ld2.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0d, 3), {R1, MR3}}, + {"ld4.sa", M, OpMXX6aHint (4, 0, 0, 0x0e, 0), {R1, MR3}}, + {"ld4.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0e, 1), {R1, MR3}}, + {"ld4.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0e, 3), {R1, MR3}}, + {"ld8.sa", M, OpMXX6aHint (4, 0, 0, 0x0f, 0), {R1, MR3}}, + {"ld8.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0f, 1), {R1, MR3}}, + {"ld8.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0f, 3), {R1, MR3}}, + {"ld1.bias", M, OpMXX6aHint (4, 0, 0, 0x10, 0), {R1, MR3}}, + {"ld1.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x10, 1), {R1, MR3}}, + {"ld1.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x10, 3), {R1, MR3}}, + {"ld2.bias", M, OpMXX6aHint (4, 0, 0, 0x11, 0), {R1, MR3}}, + {"ld2.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x11, 1), {R1, MR3}}, + {"ld2.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x11, 3), {R1, MR3}}, + {"ld4.bias", M, OpMXX6aHint (4, 0, 0, 0x12, 0), {R1, MR3}}, + {"ld4.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x12, 1), {R1, MR3}}, + {"ld4.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x12, 3), {R1, MR3}}, + {"ld8.bias", M, OpMXX6aHint (4, 0, 0, 0x13, 0), {R1, MR3}}, + {"ld8.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x13, 1), {R1, MR3}}, + {"ld8.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x13, 3), {R1, MR3}}, + {"ld1.acq", M, OpMXX6aHint (4, 0, 0, 0x14, 0), {R1, MR3}}, + {"ld1.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x14, 1), {R1, MR3}}, + {"ld1.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x14, 3), {R1, MR3}}, + {"ld2.acq", M, OpMXX6aHint (4, 0, 0, 0x15, 0), {R1, MR3}}, + {"ld2.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x15, 1), {R1, MR3}}, + {"ld2.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x15, 3), {R1, MR3}}, + {"ld4.acq", M, OpMXX6aHint (4, 0, 0, 0x16, 0), {R1, MR3}}, + {"ld4.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x16, 1), {R1, MR3}}, + {"ld4.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x16, 3), {R1, MR3}}, + {"ld8.acq", M, OpMXX6aHint (4, 0, 0, 0x17, 0), {R1, MR3}}, + {"ld8.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}}, + {"ld8.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}}, + {"ld8.fill", M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}}, + {"ld8.fill.nt1", M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}}, + {"ld8.fill.nta", M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}}, + {"ld1.c.clr", M, OpMXX6aHint (4, 0, 0, 0x20, 0), {R1, MR3}}, + {"ld1.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x20, 1), {R1, MR3}}, + {"ld1.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x20, 3), {R1, MR3}}, + {"ld2.c.clr", M, OpMXX6aHint (4, 0, 0, 0x21, 0), {R1, MR3}}, + {"ld2.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x21, 1), {R1, MR3}}, + {"ld2.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x21, 3), {R1, MR3}}, + {"ld4.c.clr", M, OpMXX6aHint (4, 0, 0, 0x22, 0), {R1, MR3}}, + {"ld4.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x22, 1), {R1, MR3}}, + {"ld4.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x22, 3), {R1, MR3}}, + {"ld8.c.clr", M, OpMXX6aHint (4, 0, 0, 0x23, 0), {R1, MR3}}, + {"ld8.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x23, 1), {R1, MR3}}, + {"ld8.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x23, 3), {R1, MR3}}, + {"ld1.c.nc", M, OpMXX6aHint (4, 0, 0, 0x24, 0), {R1, MR3}}, + {"ld1.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x24, 1), {R1, MR3}}, + {"ld1.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x24, 3), {R1, MR3}}, + {"ld2.c.nc", M, OpMXX6aHint (4, 0, 0, 0x25, 0), {R1, MR3}}, + {"ld2.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x25, 1), {R1, MR3}}, + {"ld2.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x25, 3), {R1, MR3}}, + {"ld4.c.nc", M, OpMXX6aHint (4, 0, 0, 0x26, 0), {R1, MR3}}, + {"ld4.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x26, 1), {R1, MR3}}, + {"ld4.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x26, 3), {R1, MR3}}, + {"ld8.c.nc", M, OpMXX6aHint (4, 0, 0, 0x27, 0), {R1, MR3}}, + {"ld8.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x27, 1), {R1, MR3}}, + {"ld8.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x27, 3), {R1, MR3}}, + {"ld1.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x28, 0), {R1, MR3}}, + {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x28, 1), {R1, MR3}}, + {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x28, 3), {R1, MR3}}, + {"ld2.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x29, 0), {R1, MR3}}, + {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x29, 1), {R1, MR3}}, + {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x29, 3), {R1, MR3}}, + {"ld4.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2a, 0), {R1, MR3}}, + {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2a, 1), {R1, MR3}}, + {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2a, 3), {R1, MR3}}, + {"ld8.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2b, 0), {R1, MR3}}, + {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2b, 1), {R1, MR3}}, + {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}}, + + /* integer load w/increment by register */ + {"ld1", M, OpMXX6aHint (4, 1, 0, 0x00, 0), {R1, MR3, R2}}, + {"ld1.nt1", M, OpMXX6aHint (4, 1, 0, 0x00, 1), {R1, MR3, R2}}, + {"ld1.nta", M, OpMXX6aHint (4, 1, 0, 0x00, 3), {R1, MR3, R2}}, + {"ld2", M, OpMXX6aHint (4, 1, 0, 0x01, 0), {R1, MR3, R2}}, + {"ld2.nt1", M, OpMXX6aHint (4, 1, 0, 0x01, 1), {R1, MR3, R2}}, + {"ld2.nta", M, OpMXX6aHint (4, 1, 0, 0x01, 3), {R1, MR3, R2}}, + {"ld4", M, OpMXX6aHint (4, 1, 0, 0x02, 0), {R1, MR3, R2}}, + {"ld4.nt1", M, OpMXX6aHint (4, 1, 0, 0x02, 1), {R1, MR3, R2}}, + {"ld4.nta", M, OpMXX6aHint (4, 1, 0, 0x02, 3), {R1, MR3, R2}}, + {"ld8", M, OpMXX6aHint (4, 1, 0, 0x03, 0), {R1, MR3, R2}}, + {"ld8.nt1", M, OpMXX6aHint (4, 1, 0, 0x03, 1), {R1, MR3, R2}}, + {"ld8.nta", M, OpMXX6aHint (4, 1, 0, 0x03, 3), {R1, MR3, R2}}, + {"ld1.s", M, OpMXX6aHint (4, 1, 0, 0x04, 0), {R1, MR3, R2}}, + {"ld1.s.nt1", M, OpMXX6aHint (4, 1, 0, 0x04, 1), {R1, MR3, R2}}, + {"ld1.s.nta", M, OpMXX6aHint (4, 1, 0, 0x04, 3), {R1, MR3, R2}}, + {"ld2.s", M, OpMXX6aHint (4, 1, 0, 0x05, 0), {R1, MR3, R2}}, + {"ld2.s.nt1", M, OpMXX6aHint (4, 1, 0, 0x05, 1), {R1, MR3, R2}}, + {"ld2.s.nta", M, OpMXX6aHint (4, 1, 0, 0x05, 3), {R1, MR3, R2}}, + {"ld4.s", M, OpMXX6aHint (4, 1, 0, 0x06, 0), {R1, MR3, R2}}, + {"ld4.s.nt1", M, OpMXX6aHint (4, 1, 0, 0x06, 1), {R1, MR3, R2}}, + {"ld4.s.nta", M, OpMXX6aHint (4, 1, 0, 0x06, 3), {R1, MR3, R2}}, + {"ld8.s", M, OpMXX6aHint (4, 1, 0, 0x07, 0), {R1, MR3, R2}}, + {"ld8.s.nt1", M, OpMXX6aHint (4, 1, 0, 0x07, 1), {R1, MR3, R2}}, + {"ld8.s.nta", M, OpMXX6aHint (4, 1, 0, 0x07, 3), {R1, MR3, R2}}, + {"ld1.a", M, OpMXX6aHint (4, 1, 0, 0x08, 0), {R1, MR3, R2}}, + {"ld1.a.nt1", M, OpMXX6aHint (4, 1, 0, 0x08, 1), {R1, MR3, R2}}, + {"ld1.a.nta", M, OpMXX6aHint (4, 1, 0, 0x08, 3), {R1, MR3, R2}}, + {"ld2.a", M, OpMXX6aHint (4, 1, 0, 0x09, 0), {R1, MR3, R2}}, + {"ld2.a.nt1", M, OpMXX6aHint (4, 1, 0, 0x09, 1), {R1, MR3, R2}}, + {"ld2.a.nta", M, OpMXX6aHint (4, 1, 0, 0x09, 3), {R1, MR3, R2}}, + {"ld4.a", M, OpMXX6aHint (4, 1, 0, 0x0a, 0), {R1, MR3, R2}}, + {"ld4.a.nt1", M, OpMXX6aHint (4, 1, 0, 0x0a, 1), {R1, MR3, R2}}, + {"ld4.a.nta", M, OpMXX6aHint (4, 1, 0, 0x0a, 3), {R1, MR3, R2}}, + {"ld8.a", M, OpMXX6aHint (4, 1, 0, 0x0b, 0), {R1, MR3, R2}}, + {"ld8.a.nt1", M, OpMXX6aHint (4, 1, 0, 0x0b, 1), {R1, MR3, R2}}, + {"ld8.a.nta", M, OpMXX6aHint (4, 1, 0, 0x0b, 3), {R1, MR3, R2}}, + {"ld1.sa", M, OpMXX6aHint (4, 1, 0, 0x0c, 0), {R1, MR3, R2}}, + {"ld1.sa.nt1", M, OpMXX6aHint (4, 1, 0, 0x0c, 1), {R1, MR3, R2}}, + {"ld1.sa.nta", M, OpMXX6aHint (4, 1, 0, 0x0c, 3), {R1, MR3, R2}}, + {"ld2.sa", M, OpMXX6aHint (4, 1, 0, 0x0d, 0), {R1, MR3, R2}}, + {"ld2.sa.nt1", M, OpMXX6aHint (4, 1, 0, 0x0d, 1), {R1, MR3, R2}}, + {"ld2.sa.nta", M, OpMXX6aHint (4, 1, 0, 0x0d, 3), {R1, MR3, R2}}, + {"ld4.sa", M, OpMXX6aHint (4, 1, 0, 0x0e, 0), {R1, MR3, R2}}, + {"ld4.sa.nt1", M, OpMXX6aHint (4, 1, 0, 0x0e, 1), {R1, MR3, R2}}, + {"ld4.sa.nta", M, OpMXX6aHint (4, 1, 0, 0x0e, 3), {R1, MR3, R2}}, + {"ld8.sa", M, OpMXX6aHint (4, 1, 0, 0x0f, 0), {R1, MR3, R2}}, + {"ld8.sa.nt1", M, OpMXX6aHint (4, 1, 0, 0x0f, 1), {R1, MR3, R2}}, + {"ld8.sa.nta", M, OpMXX6aHint (4, 1, 0, 0x0f, 3), {R1, MR3, R2}}, + {"ld1.bias", M, OpMXX6aHint (4, 1, 0, 0x10, 0), {R1, MR3, R2}}, + {"ld1.bias.nt1", M, OpMXX6aHint (4, 1, 0, 0x10, 1), {R1, MR3, R2}}, + {"ld1.bias.nta", M, OpMXX6aHint (4, 1, 0, 0x10, 3), {R1, MR3, R2}}, + {"ld2.bias", M, OpMXX6aHint (4, 1, 0, 0x11, 0), {R1, MR3, R2}}, + {"ld2.bias.nt1", M, OpMXX6aHint (4, 1, 0, 0x11, 1), {R1, MR3, R2}}, + {"ld2.bias.nta", M, OpMXX6aHint (4, 1, 0, 0x11, 3), {R1, MR3, R2}}, + {"ld4.bias", M, OpMXX6aHint (4, 1, 0, 0x12, 0), {R1, MR3, R2}}, + {"ld4.bias.nt1", M, OpMXX6aHint (4, 1, 0, 0x12, 1), {R1, MR3, R2}}, + {"ld4.bias.nta", M, OpMXX6aHint (4, 1, 0, 0x12, 3), {R1, MR3, R2}}, + {"ld8.bias", M, OpMXX6aHint (4, 1, 0, 0x13, 0), {R1, MR3, R2}}, + {"ld8.bias.nt1", M, OpMXX6aHint (4, 1, 0, 0x13, 1), {R1, MR3, R2}}, + {"ld8.bias.nta", M, OpMXX6aHint (4, 1, 0, 0x13, 3), {R1, MR3, R2}}, + {"ld1.acq", M, OpMXX6aHint (4, 1, 0, 0x14, 0), {R1, MR3, R2}}, + {"ld1.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x14, 1), {R1, MR3, R2}}, + {"ld1.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x14, 3), {R1, MR3, R2}}, + {"ld2.acq", M, OpMXX6aHint (4, 1, 0, 0x15, 0), {R1, MR3, R2}}, + {"ld2.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x15, 1), {R1, MR3, R2}}, + {"ld2.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x15, 3), {R1, MR3, R2}}, + {"ld4.acq", M, OpMXX6aHint (4, 1, 0, 0x16, 0), {R1, MR3, R2}}, + {"ld4.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x16, 1), {R1, MR3, R2}}, + {"ld4.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x16, 3), {R1, MR3, R2}}, + {"ld8.acq", M, OpMXX6aHint (4, 1, 0, 0x17, 0), {R1, MR3, R2}}, + {"ld8.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x17, 1), {R1, MR3, R2}}, + {"ld8.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x17, 3), {R1, MR3, R2}}, + {"ld8.fill", M, OpMXX6aHint (4, 1, 0, 0x1b, 0), {R1, MR3, R2}}, + {"ld8.fill.nt1", M, OpMXX6aHint (4, 1, 0, 0x1b, 1), {R1, MR3, R2}}, + {"ld8.fill.nta", M, OpMXX6aHint (4, 1, 0, 0x1b, 3), {R1, MR3, R2}}, + {"ld1.c.clr", M, OpMXX6aHint (4, 1, 0, 0x20, 0), {R1, MR3, R2}}, + {"ld1.c.clr.nt1", M, OpMXX6aHint (4, 1, 0, 0x20, 1), {R1, MR3, R2}}, + {"ld1.c.clr.nta", M, OpMXX6aHint (4, 1, 0, 0x20, 3), {R1, MR3, R2}}, + {"ld2.c.clr", M, OpMXX6aHint (4, 1, 0, 0x21, 0), {R1, MR3, R2}}, + {"ld2.c.clr.nt1", M, OpMXX6aHint (4, 1, 0, 0x21, 1), {R1, MR3, R2}}, + {"ld2.c.clr.nta", M, OpMXX6aHint (4, 1, 0, 0x21, 3), {R1, MR3, R2}}, + {"ld4.c.clr", M, OpMXX6aHint (4, 1, 0, 0x22, 0), {R1, MR3, R2}}, + {"ld4.c.clr.nt1", M, OpMXX6aHint (4, 1, 0, 0x22, 1), {R1, MR3, R2}}, + {"ld4.c.clr.nta", M, OpMXX6aHint (4, 1, 0, 0x22, 3), {R1, MR3, R2}}, + {"ld8.c.clr", M, OpMXX6aHint (4, 1, 0, 0x23, 0), {R1, MR3, R2}}, + {"ld8.c.clr.nt1", M, OpMXX6aHint (4, 1, 0, 0x23, 1), {R1, MR3, R2}}, + {"ld8.c.clr.nta", M, OpMXX6aHint (4, 1, 0, 0x23, 3), {R1, MR3, R2}}, + {"ld1.c.nc", M, OpMXX6aHint (4, 1, 0, 0x24, 0), {R1, MR3, R2}}, + {"ld1.c.nc.nt1", M, OpMXX6aHint (4, 1, 0, 0x24, 1), {R1, MR3, R2}}, + {"ld1.c.nc.nta", M, OpMXX6aHint (4, 1, 0, 0x24, 3), {R1, MR3, R2}}, + {"ld2.c.nc", M, OpMXX6aHint (4, 1, 0, 0x25, 0), {R1, MR3, R2}}, + {"ld2.c.nc.nt1", M, OpMXX6aHint (4, 1, 0, 0x25, 1), {R1, MR3, R2}}, + {"ld2.c.nc.nta", M, OpMXX6aHint (4, 1, 0, 0x25, 3), {R1, MR3, R2}}, + {"ld4.c.nc", M, OpMXX6aHint (4, 1, 0, 0x26, 0), {R1, MR3, R2}}, + {"ld4.c.nc.nt1", M, OpMXX6aHint (4, 1, 0, 0x26, 1), {R1, MR3, R2}}, + {"ld4.c.nc.nta", M, OpMXX6aHint (4, 1, 0, 0x26, 3), {R1, MR3, R2}}, + {"ld8.c.nc", M, OpMXX6aHint (4, 1, 0, 0x27, 0), {R1, MR3, R2}}, + {"ld8.c.nc.nt1", M, OpMXX6aHint (4, 1, 0, 0x27, 1), {R1, MR3, R2}}, + {"ld8.c.nc.nta", M, OpMXX6aHint (4, 1, 0, 0x27, 3), {R1, MR3, R2}}, + {"ld1.c.clr.acq", M, OpMXX6aHint (4, 1, 0, 0x28, 0), {R1, MR3, R2}}, + {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x28, 1), {R1, MR3, R2}}, + {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x28, 3), {R1, MR3, R2}}, + {"ld2.c.clr.acq", M, OpMXX6aHint (4, 1, 0, 0x29, 0), {R1, MR3, R2}}, + {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x29, 1), {R1, MR3, R2}}, + {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x29, 3), {R1, MR3, R2}}, + {"ld4.c.clr.acq", M, OpMXX6aHint (4, 1, 0, 0x2a, 0), {R1, MR3, R2}}, + {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x2a, 1), {R1, MR3, R2}}, + {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x2a, 3), {R1, MR3, R2}}, + {"ld8.c.clr.acq", M, OpMXX6aHint (4, 1, 0, 0x2b, 0), {R1, MR3, R2}}, + {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 1, 0, 0x2b, 1), {R1, MR3, R2}}, + {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 1, 0, 0x2b, 3), {R1, MR3, R2}}, + + {"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}}, + {"st1.nta", M, OpMXX6aHint (4, 0, 0, 0x30, 3), {MR3, R2}}, + {"st2", M, OpMXX6aHint (4, 0, 0, 0x31, 0), {MR3, R2}}, + {"st2.nta", M, OpMXX6aHint (4, 0, 0, 0x31, 3), {MR3, R2}}, + {"st4", M, OpMXX6aHint (4, 0, 0, 0x32, 0), {MR3, R2}}, + {"st4.nta", M, OpMXX6aHint (4, 0, 0, 0x32, 3), {MR3, R2}}, + {"st8", M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}}, + {"st8.nta", M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}}, + {"st1.rel", M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}}, + {"st1.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}}, + {"st2.rel", M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}}, + {"st2.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x35, 3), {MR3, R2}}, + {"st4.rel", M, OpMXX6aHint (4, 0, 0, 0x36, 0), {MR3, R2}}, + {"st4.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x36, 3), {MR3, R2}}, + {"st8.rel", M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}}, + {"st8.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}}, + {"st8.spill", M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}}, + {"st8.spill.nta", M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}}, + +#define CMPXCHG(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV} + {"cmpxchg1.acq", CMPXCHG (0x00, 0)}, + {"cmpxchg1.acq.nt1", CMPXCHG (0x00, 1)}, + {"cmpxchg1.acq.nta", CMPXCHG (0x00, 3)}, + {"cmpxchg2.acq", CMPXCHG (0x01, 0)}, + {"cmpxchg2.acq.nt1", CMPXCHG (0x01, 1)}, + {"cmpxchg2.acq.nta", CMPXCHG (0x01, 3)}, + {"cmpxchg4.acq", CMPXCHG (0x02, 0)}, + {"cmpxchg4.acq.nt1", CMPXCHG (0x02, 1)}, + {"cmpxchg4.acq.nta", CMPXCHG (0x02, 3)}, + {"cmpxchg8.acq", CMPXCHG (0x03, 0)}, + {"cmpxchg8.acq.nt1", CMPXCHG (0x03, 1)}, + {"cmpxchg8.acq.nta", CMPXCHG (0x03, 3)}, + {"cmpxchg1.rel", CMPXCHG (0x04, 0)}, + {"cmpxchg1.rel.nt1", CMPXCHG (0x04, 1)}, + {"cmpxchg1.rel.nta", CMPXCHG (0x04, 3)}, + {"cmpxchg2.rel", CMPXCHG (0x05, 0)}, + {"cmpxchg2.rel.nt1", CMPXCHG (0x05, 1)}, + {"cmpxchg2.rel.nta", CMPXCHG (0x05, 3)}, + {"cmpxchg4.rel", CMPXCHG (0x06, 0)}, + {"cmpxchg4.rel.nt1", CMPXCHG (0x06, 1)}, + {"cmpxchg4.rel.nta", CMPXCHG (0x06, 3)}, + {"cmpxchg8.rel", CMPXCHG (0x07, 0)}, + {"cmpxchg8.rel.nt1", CMPXCHG (0x07, 1)}, + {"cmpxchg8.rel.nta", CMPXCHG (0x07, 3)}, +#undef CMPXCHG + {"xchg1", M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}}, + {"xchg1.nt1", M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}}, + {"xchg1.nta", M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}}, + {"xchg2", M, OpMXX6aHint (4, 0, 1, 0x09, 0), {R1, MR3, R2}}, + {"xchg2.nt1", M, OpMXX6aHint (4, 0, 1, 0x09, 1), {R1, MR3, R2}}, + {"xchg2.nta", M, OpMXX6aHint (4, 0, 1, 0x09, 3), {R1, MR3, R2}}, + {"xchg4", M, OpMXX6aHint (4, 0, 1, 0x0a, 0), {R1, MR3, R2}}, + {"xchg4.nt1", M, OpMXX6aHint (4, 0, 1, 0x0a, 1), {R1, MR3, R2}}, + {"xchg4.nta", M, OpMXX6aHint (4, 0, 1, 0x0a, 3), {R1, MR3, R2}}, + {"xchg8", M, OpMXX6aHint (4, 0, 1, 0x0b, 0), {R1, MR3, R2}}, + {"xchg8.nt1", M, OpMXX6aHint (4, 0, 1, 0x0b, 1), {R1, MR3, R2}}, + {"xchg8.nta", M, OpMXX6aHint (4, 0, 1, 0x0b, 3), {R1, MR3, R2}}, + + {"fetchadd4.acq", M, OpMXX6aHint (4, 0, 1, 0x12, 0), {R1, MR3, INC3}}, + {"fetchadd4.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x12, 1), {R1, MR3, INC3}}, + {"fetchadd4.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x12, 3), {R1, MR3, INC3}}, + {"fetchadd8.acq", M, OpMXX6aHint (4, 0, 1, 0x13, 0), {R1, MR3, INC3}}, + {"fetchadd8.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x13, 1), {R1, MR3, INC3}}, + {"fetchadd8.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x13, 3), {R1, MR3, INC3}}, + {"fetchadd4.rel", M, OpMXX6aHint (4, 0, 1, 0x16, 0), {R1, MR3, INC3}}, + {"fetchadd4.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x16, 1), {R1, MR3, INC3}}, + {"fetchadd4.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x16, 3), {R1, MR3, INC3}}, + {"fetchadd8.rel", M, OpMXX6aHint (4, 0, 1, 0x17, 0), {R1, MR3, INC3}}, + {"fetchadd8.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x17, 1), {R1, MR3, INC3}}, + {"fetchadd8.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x17, 3), {R1, MR3, INC3}}, + + {"getf.sig", M, OpMXX6a (4, 0, 1, 0x1c), {R1, F2}}, + {"getf.exp", M, OpMXX6a (4, 0, 1, 0x1d), {R1, F2}}, + {"getf.s", M, OpMXX6a (4, 0, 1, 0x1e), {R1, F2}}, + {"getf.d", M, OpMXX6a (4, 0, 1, 0x1f), {R1, F2}}, + + /* integer load w/increment by immediate */ + {"ld1", M, OpX6aHint (5, 0x00, 0), {R1, MR3, IMM9b}}, + {"ld1.nt1", M, OpX6aHint (5, 0x00, 1), {R1, MR3, IMM9b}}, + {"ld1.nta", M, OpX6aHint (5, 0x00, 3), {R1, MR3, IMM9b}}, + {"ld2", M, OpX6aHint (5, 0x01, 0), {R1, MR3, IMM9b}}, + {"ld2.nt1", M, OpX6aHint (5, 0x01, 1), {R1, MR3, IMM9b}}, + {"ld2.nta", M, OpX6aHint (5, 0x01, 3), {R1, MR3, IMM9b}}, + {"ld4", M, OpX6aHint (5, 0x02, 0), {R1, MR3, IMM9b}}, + {"ld4.nt1", M, OpX6aHint (5, 0x02, 1), {R1, MR3, IMM9b}}, + {"ld4.nta", M, OpX6aHint (5, 0x02, 3), {R1, MR3, IMM9b}}, + {"ld8", M, OpX6aHint (5, 0x03, 0), {R1, MR3, IMM9b}}, + {"ld8.nt1", M, OpX6aHint (5, 0x03, 1), {R1, MR3, IMM9b}}, + {"ld8.nta", M, OpX6aHint (5, 0x03, 3), {R1, MR3, IMM9b}}, + {"ld1.s", M, OpX6aHint (5, 0x04, 0), {R1, MR3, IMM9b}}, + {"ld1.s.nt1", M, OpX6aHint (5, 0x04, 1), {R1, MR3, IMM9b}}, + {"ld1.s.nta", M, OpX6aHint (5, 0x04, 3), {R1, MR3, IMM9b}}, + {"ld2.s", M, OpX6aHint (5, 0x05, 0), {R1, MR3, IMM9b}}, + {"ld2.s.nt1", M, OpX6aHint (5, 0x05, 1), {R1, MR3, IMM9b}}, + {"ld2.s.nta", M, OpX6aHint (5, 0x05, 3), {R1, MR3, IMM9b}}, + {"ld4.s", M, OpX6aHint (5, 0x06, 0), {R1, MR3, IMM9b}}, + {"ld4.s.nt1", M, OpX6aHint (5, 0x06, 1), {R1, MR3, IMM9b}}, + {"ld4.s.nta", M, OpX6aHint (5, 0x06, 3), {R1, MR3, IMM9b}}, + {"ld8.s", M, OpX6aHint (5, 0x07, 0), {R1, MR3, IMM9b}}, + {"ld8.s.nt1", M, OpX6aHint (5, 0x07, 1), {R1, MR3, IMM9b}}, + {"ld8.s.nta", M, OpX6aHint (5, 0x07, 3), {R1, MR3, IMM9b}}, + {"ld1.a", M, OpX6aHint (5, 0x08, 0), {R1, MR3, IMM9b}}, + {"ld1.a.nt1", M, OpX6aHint (5, 0x08, 1), {R1, MR3, IMM9b}}, + {"ld1.a.nta", M, OpX6aHint (5, 0x08, 3), {R1, MR3, IMM9b}}, + {"ld2.a", M, OpX6aHint (5, 0x09, 0), {R1, MR3, IMM9b}}, + {"ld2.a.nt1", M, OpX6aHint (5, 0x09, 1), {R1, MR3, IMM9b}}, + {"ld2.a.nta", M, OpX6aHint (5, 0x09, 3), {R1, MR3, IMM9b}}, + {"ld4.a", M, OpX6aHint (5, 0x0a, 0), {R1, MR3, IMM9b}}, + {"ld4.a.nt1", M, OpX6aHint (5, 0x0a, 1), {R1, MR3, IMM9b}}, + {"ld4.a.nta", M, OpX6aHint (5, 0x0a, 3), {R1, MR3, IMM9b}}, + {"ld8.a", M, OpX6aHint (5, 0x0b, 0), {R1, MR3, IMM9b}}, + {"ld8.a.nt1", M, OpX6aHint (5, 0x0b, 1), {R1, MR3, IMM9b}}, + {"ld8.a.nta", M, OpX6aHint (5, 0x0b, 3), {R1, MR3, IMM9b}}, + {"ld1.sa", M, OpX6aHint (5, 0x0c, 0), {R1, MR3, IMM9b}}, + {"ld1.sa.nt1", M, OpX6aHint (5, 0x0c, 1), {R1, MR3, IMM9b}}, + {"ld1.sa.nta", M, OpX6aHint (5, 0x0c, 3), {R1, MR3, IMM9b}}, + {"ld2.sa", M, OpX6aHint (5, 0x0d, 0), {R1, MR3, IMM9b}}, + {"ld2.sa.nt1", M, OpX6aHint (5, 0x0d, 1), {R1, MR3, IMM9b}}, + {"ld2.sa.nta", M, OpX6aHint (5, 0x0d, 3), {R1, MR3, IMM9b}}, + {"ld4.sa", M, OpX6aHint (5, 0x0e, 0), {R1, MR3, IMM9b}}, + {"ld4.sa.nt1", M, OpX6aHint (5, 0x0e, 1), {R1, MR3, IMM9b}}, + {"ld4.sa.nta", M, OpX6aHint (5, 0x0e, 3), {R1, MR3, IMM9b}}, + {"ld8.sa", M, OpX6aHint (5, 0x0f, 0), {R1, MR3, IMM9b}}, + {"ld8.sa.nt1", M, OpX6aHint (5, 0x0f, 1), {R1, MR3, IMM9b}}, + {"ld8.sa.nta", M, OpX6aHint (5, 0x0f, 3), {R1, MR3, IMM9b}}, + {"ld1.bias", M, OpX6aHint (5, 0x10, 0), {R1, MR3, IMM9b}}, + {"ld1.bias.nt1", M, OpX6aHint (5, 0x10, 1), {R1, MR3, IMM9b}}, + {"ld1.bias.nta", M, OpX6aHint (5, 0x10, 3), {R1, MR3, IMM9b}}, + {"ld2.bias", M, OpX6aHint (5, 0x11, 0), {R1, MR3, IMM9b}}, + {"ld2.bias.nt1", M, OpX6aHint (5, 0x11, 1), {R1, MR3, IMM9b}}, + {"ld2.bias.nta", M, OpX6aHint (5, 0x11, 3), {R1, MR3, IMM9b}}, + {"ld4.bias", M, OpX6aHint (5, 0x12, 0), {R1, MR3, IMM9b}}, + {"ld4.bias.nt1", M, OpX6aHint (5, 0x12, 1), {R1, MR3, IMM9b}}, + {"ld4.bias.nta", M, OpX6aHint (5, 0x12, 3), {R1, MR3, IMM9b}}, + {"ld8.bias", M, OpX6aHint (5, 0x13, 0), {R1, MR3, IMM9b}}, + {"ld8.bias.nt1", M, OpX6aHint (5, 0x13, 1), {R1, MR3, IMM9b}}, + {"ld8.bias.nta", M, OpX6aHint (5, 0x13, 3), {R1, MR3, IMM9b}}, + {"ld1.acq", M, OpX6aHint (5, 0x14, 0), {R1, MR3, IMM9b}}, + {"ld1.acq.nt1", M, OpX6aHint (5, 0x14, 1), {R1, MR3, IMM9b}}, + {"ld1.acq.nta", M, OpX6aHint (5, 0x14, 3), {R1, MR3, IMM9b}}, + {"ld2.acq", M, OpX6aHint (5, 0x15, 0), {R1, MR3, IMM9b}}, + {"ld2.acq.nt1", M, OpX6aHint (5, 0x15, 1), {R1, MR3, IMM9b}}, + {"ld2.acq.nta", M, OpX6aHint (5, 0x15, 3), {R1, MR3, IMM9b}}, + {"ld4.acq", M, OpX6aHint (5, 0x16, 0), {R1, MR3, IMM9b}}, + {"ld4.acq.nt1", M, OpX6aHint (5, 0x16, 1), {R1, MR3, IMM9b}}, + {"ld4.acq.nta", M, OpX6aHint (5, 0x16, 3), {R1, MR3, IMM9b}}, + {"ld8.acq", M, OpX6aHint (5, 0x17, 0), {R1, MR3, IMM9b}}, + {"ld8.acq.nt1", M, OpX6aHint (5, 0x17, 1), {R1, MR3, IMM9b}}, + {"ld8.acq.nta", M, OpX6aHint (5, 0x17, 3), {R1, MR3, IMM9b}}, + {"ld8.fill", M, OpX6aHint (5, 0x1b, 0), {R1, MR3, IMM9b}}, + {"ld8.fill.nt1", M, OpX6aHint (5, 0x1b, 1), {R1, MR3, IMM9b}}, + {"ld8.fill.nta", M, OpX6aHint (5, 0x1b, 3), {R1, MR3, IMM9b}}, + {"ld1.c.clr", M, OpX6aHint (5, 0x20, 0), {R1, MR3, IMM9b}}, + {"ld1.c.clr.nt1", M, OpX6aHint (5, 0x20, 1), {R1, MR3, IMM9b}}, + {"ld1.c.clr.nta", M, OpX6aHint (5, 0x20, 3), {R1, MR3, IMM9b}}, + {"ld2.c.clr", M, OpX6aHint (5, 0x21, 0), {R1, MR3, IMM9b}}, + {"ld2.c.clr.nt1", M, OpX6aHint (5, 0x21, 1), {R1, MR3, IMM9b}}, + {"ld2.c.clr.nta", M, OpX6aHint (5, 0x21, 3), {R1, MR3, IMM9b}}, + {"ld4.c.clr", M, OpX6aHint (5, 0x22, 0), {R1, MR3, IMM9b}}, + {"ld4.c.clr.nt1", M, OpX6aHint (5, 0x22, 1), {R1, MR3, IMM9b}}, + {"ld4.c.clr.nta", M, OpX6aHint (5, 0x22, 3), {R1, MR3, IMM9b}}, + {"ld8.c.clr", M, OpX6aHint (5, 0x23, 0), {R1, MR3, IMM9b}}, + {"ld8.c.clr.nt1", M, OpX6aHint (5, 0x23, 1), {R1, MR3, IMM9b}}, + {"ld8.c.clr.nta", M, OpX6aHint (5, 0x23, 3), {R1, MR3, IMM9b}}, + {"ld1.c.nc", M, OpX6aHint (5, 0x24, 0), {R1, MR3, IMM9b}}, + {"ld1.c.nc.nt1", M, OpX6aHint (5, 0x24, 1), {R1, MR3, IMM9b}}, + {"ld1.c.nc.nta", M, OpX6aHint (5, 0x24, 3), {R1, MR3, IMM9b}}, + {"ld2.c.nc", M, OpX6aHint (5, 0x25, 0), {R1, MR3, IMM9b}}, + {"ld2.c.nc.nt1", M, OpX6aHint (5, 0x25, 1), {R1, MR3, IMM9b}}, + {"ld2.c.nc.nta", M, OpX6aHint (5, 0x25, 3), {R1, MR3, IMM9b}}, + {"ld4.c.nc", M, OpX6aHint (5, 0x26, 0), {R1, MR3, IMM9b}}, + {"ld4.c.nc.nt1", M, OpX6aHint (5, 0x26, 1), {R1, MR3, IMM9b}}, + {"ld4.c.nc.nta", M, OpX6aHint (5, 0x26, 3), {R1, MR3, IMM9b}}, + {"ld8.c.nc", M, OpX6aHint (5, 0x27, 0), {R1, MR3, IMM9b}}, + {"ld8.c.nc.nt1", M, OpX6aHint (5, 0x27, 1), {R1, MR3, IMM9b}}, + {"ld8.c.nc.nta", M, OpX6aHint (5, 0x27, 3), {R1, MR3, IMM9b}}, + {"ld1.c.clr.acq", M, OpX6aHint (5, 0x28, 0), {R1, MR3, IMM9b}}, + {"ld1.c.clr.acq.nt1", M, OpX6aHint (5, 0x28, 1), {R1, MR3, IMM9b}}, + {"ld1.c.clr.acq.nta", M, OpX6aHint (5, 0x28, 3), {R1, MR3, IMM9b}}, + {"ld2.c.clr.acq", M, OpX6aHint (5, 0x29, 0), {R1, MR3, IMM9b}}, + {"ld2.c.clr.acq.nt1", M, OpX6aHint (5, 0x29, 1), {R1, MR3, IMM9b}}, + {"ld2.c.clr.acq.nta", M, OpX6aHint (5, 0x29, 3), {R1, MR3, IMM9b}}, + {"ld4.c.clr.acq", M, OpX6aHint (5, 0x2a, 0), {R1, MR3, IMM9b}}, + {"ld4.c.clr.acq.nt1", M, OpX6aHint (5, 0x2a, 1), {R1, MR3, IMM9b}}, + {"ld4.c.clr.acq.nta", M, OpX6aHint (5, 0x2a, 3), {R1, MR3, IMM9b}}, + {"ld8.c.clr.acq", M, OpX6aHint (5, 0x2b, 0), {R1, MR3, IMM9b}}, + {"ld8.c.clr.acq.nt1", M, OpX6aHint (5, 0x2b, 1), {R1, MR3, IMM9b}}, + {"ld8.c.clr.acq.nta", M, OpX6aHint (5, 0x2b, 3), {R1, MR3, IMM9b}}, + + /* store w/increment by immediate */ + {"st1", M, OpX6aHint (5, 0x30, 0), {MR3, R2, IMM9a}}, + {"st1.nta", M, OpX6aHint (5, 0x30, 3), {MR3, R2, IMM9a}}, + {"st2", M, OpX6aHint (5, 0x31, 0), {MR3, R2, IMM9a}}, + {"st2.nta", M, OpX6aHint (5, 0x31, 3), {MR3, R2, IMM9a}}, + {"st4", M, OpX6aHint (5, 0x32, 0), {MR3, R2, IMM9a}}, + {"st4.nta", M, OpX6aHint (5, 0x32, 3), {MR3, R2, IMM9a}}, + {"st8", M, OpX6aHint (5, 0x33, 0), {MR3, R2, IMM9a}}, + {"st8.nta", M, OpX6aHint (5, 0x33, 3), {MR3, R2, IMM9a}}, + {"st1.rel", M, OpX6aHint (5, 0x34, 0), {MR3, R2, IMM9a}}, + {"st1.rel.nta", M, OpX6aHint (5, 0x34, 3), {MR3, R2, IMM9a}}, + {"st2.rel", M, OpX6aHint (5, 0x35, 0), {MR3, R2, IMM9a}}, + {"st2.rel.nta", M, OpX6aHint (5, 0x35, 3), {MR3, R2, IMM9a}}, + {"st4.rel", M, OpX6aHint (5, 0x36, 0), {MR3, R2, IMM9a}}, + {"st4.rel.nta", M, OpX6aHint (5, 0x36, 3), {MR3, R2, IMM9a}}, + {"st8.rel", M, OpX6aHint (5, 0x37, 0), {MR3, R2, IMM9a}}, + {"st8.rel.nta", M, OpX6aHint (5, 0x37, 3), {MR3, R2, IMM9a}}, + {"st8.spill", M, OpX6aHint (5, 0x3b, 0), {MR3, R2, IMM9a}}, + {"st8.spill.nta", M, OpX6aHint (5, 0x3b, 3), {MR3, R2, IMM9a}}, + + /* floating-point load */ + {"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}}, + {"ldfs.nt1", M, OpMXX6aHint (6, 0, 0, 0x02, 1), {F1, MR3}}, + {"ldfs.nta", M, OpMXX6aHint (6, 0, 0, 0x02, 3), {F1, MR3}}, + {"ldfd", M, OpMXX6aHint (6, 0, 0, 0x03, 0), {F1, MR3}}, + {"ldfd.nt1", M, OpMXX6aHint (6, 0, 0, 0x03, 1), {F1, MR3}}, + {"ldfd.nta", M, OpMXX6aHint (6, 0, 0, 0x03, 3), {F1, MR3}}, + {"ldf8", M, OpMXX6aHint (6, 0, 0, 0x01, 0), {F1, MR3}}, + {"ldf8.nt1", M, OpMXX6aHint (6, 0, 0, 0x01, 1), {F1, MR3}}, + {"ldf8.nta", M, OpMXX6aHint (6, 0, 0, 0x01, 3), {F1, MR3}}, + {"ldfe", M, OpMXX6aHint (6, 0, 0, 0x00, 0), {F1, MR3}}, + {"ldfe.nt1", M, OpMXX6aHint (6, 0, 0, 0x00, 1), {F1, MR3}}, + {"ldfe.nta", M, OpMXX6aHint (6, 0, 0, 0x00, 3), {F1, MR3}}, + {"ldfs.s", M, OpMXX6aHint (6, 0, 0, 0x06, 0), {F1, MR3}}, + {"ldfs.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x06, 1), {F1, MR3}}, + {"ldfs.s.nta", M, OpMXX6aHint (6, 0, 0, 0x06, 3), {F1, MR3}}, + {"ldfd.s", M, OpMXX6aHint (6, 0, 0, 0x07, 0), {F1, MR3}}, + {"ldfd.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x07, 1), {F1, MR3}}, + {"ldfd.s.nta", M, OpMXX6aHint (6, 0, 0, 0x07, 3), {F1, MR3}}, + {"ldf8.s", M, OpMXX6aHint (6, 0, 0, 0x05, 0), {F1, MR3}}, + {"ldf8.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x05, 1), {F1, MR3}}, + {"ldf8.s.nta", M, OpMXX6aHint (6, 0, 0, 0x05, 3), {F1, MR3}}, + {"ldfe.s", M, OpMXX6aHint (6, 0, 0, 0x04, 0), {F1, MR3}}, + {"ldfe.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x04, 1), {F1, MR3}}, + {"ldfe.s.nta", M, OpMXX6aHint (6, 0, 0, 0x04, 3), {F1, MR3}}, + {"ldfs.a", M, OpMXX6aHint (6, 0, 0, 0x0a, 0), {F1, MR3}}, + {"ldfs.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0a, 1), {F1, MR3}}, + {"ldfs.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0a, 3), {F1, MR3}}, + {"ldfd.a", M, OpMXX6aHint (6, 0, 0, 0x0b, 0), {F1, MR3}}, + {"ldfd.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0b, 1), {F1, MR3}}, + {"ldfd.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0b, 3), {F1, MR3}}, + {"ldf8.a", M, OpMXX6aHint (6, 0, 0, 0x09, 0), {F1, MR3}}, + {"ldf8.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x09, 1), {F1, MR3}}, + {"ldf8.a.nta", M, OpMXX6aHint (6, 0, 0, 0x09, 3), {F1, MR3}}, + {"ldfe.a", M, OpMXX6aHint (6, 0, 0, 0x08, 0), {F1, MR3}}, + {"ldfe.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x08, 1), {F1, MR3}}, + {"ldfe.a.nta", M, OpMXX6aHint (6, 0, 0, 0x08, 3), {F1, MR3}}, + {"ldfs.sa", M, OpMXX6aHint (6, 0, 0, 0x0e, 0), {F1, MR3}}, + {"ldfs.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0e, 1), {F1, MR3}}, + {"ldfs.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0e, 3), {F1, MR3}}, + {"ldfd.sa", M, OpMXX6aHint (6, 0, 0, 0x0f, 0), {F1, MR3}}, + {"ldfd.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0f, 1), {F1, MR3}}, + {"ldfd.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0f, 3), {F1, MR3}}, + {"ldf8.sa", M, OpMXX6aHint (6, 0, 0, 0x0d, 0), {F1, MR3}}, + {"ldf8.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0d, 1), {F1, MR3}}, + {"ldf8.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0d, 3), {F1, MR3}}, + {"ldfe.sa", M, OpMXX6aHint (6, 0, 0, 0x0c, 0), {F1, MR3}}, + {"ldfe.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0c, 1), {F1, MR3}}, + {"ldfe.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0c, 3), {F1, MR3}}, + {"ldf.fill", M, OpMXX6aHint (6, 0, 0, 0x1b, 0), {F1, MR3}}, + {"ldf.fill.nt1", M, OpMXX6aHint (6, 0, 0, 0x1b, 1), {F1, MR3}}, + {"ldf.fill.nta", M, OpMXX6aHint (6, 0, 0, 0x1b, 3), {F1, MR3}}, + {"ldfs.c.clr", M, OpMXX6aHint (6, 0, 0, 0x22, 0), {F1, MR3}}, + {"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x22, 1), {F1, MR3}}, + {"ldfs.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x22, 3), {F1, MR3}}, + {"ldfd.c.clr", M, OpMXX6aHint (6, 0, 0, 0x23, 0), {F1, MR3}}, + {"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x23, 1), {F1, MR3}}, + {"ldfd.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x23, 3), {F1, MR3}}, + {"ldf8.c.clr", M, OpMXX6aHint (6, 0, 0, 0x21, 0), {F1, MR3}}, + {"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x21, 1), {F1, MR3}}, + {"ldf8.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x21, 3), {F1, MR3}}, + {"ldfe.c.clr", M, OpMXX6aHint (6, 0, 0, 0x20, 0), {F1, MR3}}, + {"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x20, 1), {F1, MR3}}, + {"ldfe.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x20, 3), {F1, MR3}}, + {"ldfs.c.nc", M, OpMXX6aHint (6, 0, 0, 0x26, 0), {F1, MR3}}, + {"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x26, 1), {F1, MR3}}, + {"ldfs.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x26, 3), {F1, MR3}}, + {"ldfd.c.nc", M, OpMXX6aHint (6, 0, 0, 0x27, 0), {F1, MR3}}, + {"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x27, 1), {F1, MR3}}, + {"ldfd.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x27, 3), {F1, MR3}}, + {"ldf8.c.nc", M, OpMXX6aHint (6, 0, 0, 0x25, 0), {F1, MR3}}, + {"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x25, 1), {F1, MR3}}, + {"ldf8.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x25, 3), {F1, MR3}}, + {"ldfe.c.nc", M, OpMXX6aHint (6, 0, 0, 0x24, 0), {F1, MR3}}, + {"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x24, 1), {F1, MR3}}, + {"ldfe.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x24, 3), {F1, MR3}}, + + {"ldfs", M, OpMXX6aHint (6, 1, 0, 0x02, 0), {F1, MR3, R2}}, + {"ldfs.nt1", M, OpMXX6aHint (6, 1, 0, 0x02, 1), {F1, MR3, R2}}, + {"ldfs.nta", M, OpMXX6aHint (6, 1, 0, 0x02, 3), {F1, MR3, R2}}, + {"ldfd", M, OpMXX6aHint (6, 1, 0, 0x03, 0), {F1, MR3, R2}}, + {"ldfd.nt1", M, OpMXX6aHint (6, 1, 0, 0x03, 1), {F1, MR3, R2}}, + {"ldfd.nta", M, OpMXX6aHint (6, 1, 0, 0x03, 3), {F1, MR3, R2}}, + {"ldf8", M, OpMXX6aHint (6, 1, 0, 0x01, 0), {F1, MR3, R2}}, + {"ldf8.nt1", M, OpMXX6aHint (6, 1, 0, 0x01, 1), {F1, MR3, R2}}, + {"ldf8.nta", M, OpMXX6aHint (6, 1, 0, 0x01, 3), {F1, MR3, R2}}, + {"ldfe", M, OpMXX6aHint (6, 1, 0, 0x00, 0), {F1, MR3, R2}}, + {"ldfe.nt1", M, OpMXX6aHint (6, 1, 0, 0x00, 1), {F1, MR3, R2}}, + {"ldfe.nta", M, OpMXX6aHint (6, 1, 0, 0x00, 3), {F1, MR3, R2}}, + {"ldfs.s", M, OpMXX6aHint (6, 1, 0, 0x06, 0), {F1, MR3, R2}}, + {"ldfs.s.nt1", M, OpMXX6aHint (6, 1, 0, 0x06, 1), {F1, MR3, R2}}, + {"ldfs.s.nta", M, OpMXX6aHint (6, 1, 0, 0x06, 3), {F1, MR3, R2}}, + {"ldfd.s", M, OpMXX6aHint (6, 1, 0, 0x07, 0), {F1, MR3, R2}}, + {"ldfd.s.nt1", M, OpMXX6aHint (6, 1, 0, 0x07, 1), {F1, MR3, R2}}, + {"ldfd.s.nta", M, OpMXX6aHint (6, 1, 0, 0x07, 3), {F1, MR3, R2}}, + {"ldf8.s", M, OpMXX6aHint (6, 1, 0, 0x05, 0), {F1, MR3, R2}}, + {"ldf8.s.nt1", M, OpMXX6aHint (6, 1, 0, 0x05, 1), {F1, MR3, R2}}, + {"ldf8.s.nta", M, OpMXX6aHint (6, 1, 0, 0x05, 3), {F1, MR3, R2}}, + {"ldfe.s", M, OpMXX6aHint (6, 1, 0, 0x04, 0), {F1, MR3, R2}}, + {"ldfe.s.nt1", M, OpMXX6aHint (6, 1, 0, 0x04, 1), {F1, MR3, R2}}, + {"ldfe.s.nta", M, OpMXX6aHint (6, 1, 0, 0x04, 3), {F1, MR3, R2}}, + {"ldfs.a", M, OpMXX6aHint (6, 1, 0, 0x0a, 0), {F1, MR3, R2}}, + {"ldfs.a.nt1", M, OpMXX6aHint (6, 1, 0, 0x0a, 1), {F1, MR3, R2}}, + {"ldfs.a.nta", M, OpMXX6aHint (6, 1, 0, 0x0a, 3), {F1, MR3, R2}}, + {"ldfd.a", M, OpMXX6aHint (6, 1, 0, 0x0b, 0), {F1, MR3, R2}}, + {"ldfd.a.nt1", M, OpMXX6aHint (6, 1, 0, 0x0b, 1), {F1, MR3, R2}}, + {"ldfd.a.nta", M, OpMXX6aHint (6, 1, 0, 0x0b, 3), {F1, MR3, R2}}, + {"ldf8.a", M, OpMXX6aHint (6, 1, 0, 0x09, 0), {F1, MR3, R2}}, + {"ldf8.a.nt1", M, OpMXX6aHint (6, 1, 0, 0x09, 1), {F1, MR3, R2}}, + {"ldf8.a.nta", M, OpMXX6aHint (6, 1, 0, 0x09, 3), {F1, MR3, R2}}, + {"ldfe.a", M, OpMXX6aHint (6, 1, 0, 0x08, 0), {F1, MR3, R2}}, + {"ldfe.a.nt1", M, OpMXX6aHint (6, 1, 0, 0x08, 1), {F1, MR3, R2}}, + {"ldfe.a.nta", M, OpMXX6aHint (6, 1, 0, 0x08, 3), {F1, MR3, R2}}, + {"ldfs.sa", M, OpMXX6aHint (6, 1, 0, 0x0e, 0), {F1, MR3, R2}}, + {"ldfs.sa.nt1", M, OpMXX6aHint (6, 1, 0, 0x0e, 1), {F1, MR3, R2}}, + {"ldfs.sa.nta", M, OpMXX6aHint (6, 1, 0, 0x0e, 3), {F1, MR3, R2}}, + {"ldfd.sa", M, OpMXX6aHint (6, 1, 0, 0x0f, 0), {F1, MR3, R2}}, + {"ldfd.sa.nt1", M, OpMXX6aHint (6, 1, 0, 0x0f, 1), {F1, MR3, R2}}, + {"ldfd.sa.nta", M, OpMXX6aHint (6, 1, 0, 0x0f, 3), {F1, MR3, R2}}, + {"ldf8.sa", M, OpMXX6aHint (6, 1, 0, 0x0d, 0), {F1, MR3, R2}}, + {"ldf8.sa.nt1", M, OpMXX6aHint (6, 1, 0, 0x0d, 1), {F1, MR3, R2}}, + {"ldf8.sa.nta", M, OpMXX6aHint (6, 1, 0, 0x0d, 3), {F1, MR3, R2}}, + {"ldfe.sa", M, OpMXX6aHint (6, 1, 0, 0x0c, 0), {F1, MR3, R2}}, + {"ldfe.sa.nt1", M, OpMXX6aHint (6, 1, 0, 0x0c, 1), {F1, MR3, R2}}, + {"ldfe.sa.nta", M, OpMXX6aHint (6, 1, 0, 0x0c, 3), {F1, MR3, R2}}, + {"ldf.fill", M, OpMXX6aHint (6, 1, 0, 0x1b, 0), {F1, MR3, R2}}, + {"ldf.fill.nt1", M, OpMXX6aHint (6, 1, 0, 0x1b, 1), {F1, MR3, R2}}, + {"ldf.fill.nta", M, OpMXX6aHint (6, 1, 0, 0x1b, 3), {F1, MR3, R2}}, + {"ldfs.c.clr", M, OpMXX6aHint (6, 1, 0, 0x22, 0), {F1, MR3, R2}}, + {"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 1, 0, 0x22, 1), {F1, MR3, R2}}, + {"ldfs.c.clr.nta", M, OpMXX6aHint (6, 1, 0, 0x22, 3), {F1, MR3, R2}}, + {"ldfd.c.clr", M, OpMXX6aHint (6, 1, 0, 0x23, 0), {F1, MR3, R2}}, + {"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 1, 0, 0x23, 1), {F1, MR3, R2}}, + {"ldfd.c.clr.nta", M, OpMXX6aHint (6, 1, 0, 0x23, 3), {F1, MR3, R2}}, + {"ldf8.c.clr", M, OpMXX6aHint (6, 1, 0, 0x21, 0), {F1, MR3, R2}}, + {"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 1, 0, 0x21, 1), {F1, MR3, R2}}, + {"ldf8.c.clr.nta", M, OpMXX6aHint (6, 1, 0, 0x21, 3), {F1, MR3, R2}}, + {"ldfe.c.clr", M, OpMXX6aHint (6, 1, 0, 0x20, 0), {F1, MR3, R2}}, + {"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 1, 0, 0x20, 1), {F1, MR3, R2}}, + {"ldfe.c.clr.nta", M, OpMXX6aHint (6, 1, 0, 0x20, 3), {F1, MR3, R2}}, + {"ldfs.c.nc", M, OpMXX6aHint (6, 1, 0, 0x26, 0), {F1, MR3, R2}}, + {"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 1, 0, 0x26, 1), {F1, MR3, R2}}, + {"ldfs.c.nc.nta", M, OpMXX6aHint (6, 1, 0, 0x26, 3), {F1, MR3, R2}}, + {"ldfd.c.nc", M, OpMXX6aHint (6, 1, 0, 0x27, 0), {F1, MR3, R2}}, + {"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 1, 0, 0x27, 1), {F1, MR3, R2}}, + {"ldfd.c.nc.nta", M, OpMXX6aHint (6, 1, 0, 0x27, 3), {F1, MR3, R2}}, + {"ldf8.c.nc", M, OpMXX6aHint (6, 1, 0, 0x25, 0), {F1, MR3, R2}}, + {"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 1, 0, 0x25, 1), {F1, MR3, R2}}, + {"ldf8.c.nc.nta", M, OpMXX6aHint (6, 1, 0, 0x25, 3), {F1, MR3, R2}}, + {"ldfe.c.nc", M, OpMXX6aHint (6, 1, 0, 0x24, 0), {F1, MR3, R2}}, + {"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 1, 0, 0x24, 1), {F1, MR3, R2}}, + {"ldfe.c.nc.nta", M, OpMXX6aHint (6, 1, 0, 0x24, 3), {F1, MR3, R2}}, + + /* floating-point store */ + {"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}}, + {"stfs.nta", M, OpMXX6aHint (6, 0, 0, 0x32, 3), {MR3, F2}}, + {"stfd", M, OpMXX6aHint (6, 0, 0, 0x33, 0), {MR3, F2}}, + {"stfd.nta", M, OpMXX6aHint (6, 0, 0, 0x33, 3), {MR3, F2}}, + {"stf8", M, OpMXX6aHint (6, 0, 0, 0x31, 0), {MR3, F2}}, + {"stf8.nta", M, OpMXX6aHint (6, 0, 0, 0x31, 3), {MR3, F2}}, + {"stfe", M, OpMXX6aHint (6, 0, 0, 0x30, 0), {MR3, F2}}, + {"stfe.nta", M, OpMXX6aHint (6, 0, 0, 0x30, 3), {MR3, F2}}, + {"stf.spill", M, OpMXX6aHint (6, 0, 0, 0x3b, 0), {MR3, F2}}, + {"stf.spill.nta", M, OpMXX6aHint (6, 0, 0, 0x3b, 3), {MR3, F2}}, + + /* floating-point load pair */ + {"ldfps", M2, OpMXX6aHint (6, 0, 1, 0x02, 0), {F1, F2, MR3}}, + {"ldfps.nt1", M2, OpMXX6aHint (6, 0, 1, 0x02, 1), {F1, F2, MR3}}, + {"ldfps.nta", M2, OpMXX6aHint (6, 0, 1, 0x02, 3), {F1, F2, MR3}}, + {"ldfpd", M2, OpMXX6aHint (6, 0, 1, 0x03, 0), {F1, F2, MR3}}, + {"ldfpd.nt1", M2, OpMXX6aHint (6, 0, 1, 0x03, 1), {F1, F2, MR3}}, + {"ldfpd.nta", M2, OpMXX6aHint (6, 0, 1, 0x03, 3), {F1, F2, MR3}}, + {"ldfp8", M2, OpMXX6aHint (6, 0, 1, 0x01, 0), {F1, F2, MR3}}, + {"ldfp8.nt1", M2, OpMXX6aHint (6, 0, 1, 0x01, 1), {F1, F2, MR3}}, + {"ldfp8.nta", M2, OpMXX6aHint (6, 0, 1, 0x01, 3), {F1, F2, MR3}}, + {"ldfps.s", M2, OpMXX6aHint (6, 0, 1, 0x06, 0), {F1, F2, MR3}}, + {"ldfps.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x06, 1), {F1, F2, MR3}}, + {"ldfps.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x06, 3), {F1, F2, MR3}}, + {"ldfpd.s", M2, OpMXX6aHint (6, 0, 1, 0x07, 0), {F1, F2, MR3}}, + {"ldfpd.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x07, 1), {F1, F2, MR3}}, + {"ldfpd.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x07, 3), {F1, F2, MR3}}, + {"ldfp8.s", M2, OpMXX6aHint (6, 0, 1, 0x05, 0), {F1, F2, MR3}}, + {"ldfp8.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x05, 1), {F1, F2, MR3}}, + {"ldfp8.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x05, 3), {F1, F2, MR3}}, + {"ldfps.a", M2, OpMXX6aHint (6, 0, 1, 0x0a, 0), {F1, F2, MR3}}, + {"ldfps.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0a, 1), {F1, F2, MR3}}, + {"ldfps.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0a, 3), {F1, F2, MR3}}, + {"ldfpd.a", M2, OpMXX6aHint (6, 0, 1, 0x0b, 0), {F1, F2, MR3}}, + {"ldfpd.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0b, 1), {F1, F2, MR3}}, + {"ldfpd.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0b, 3), {F1, F2, MR3}}, + {"ldfp8.a", M2, OpMXX6aHint (6, 0, 1, 0x09, 0), {F1, F2, MR3}}, + {"ldfp8.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x09, 1), {F1, F2, MR3}}, + {"ldfp8.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x09, 3), {F1, F2, MR3}}, + {"ldfps.sa", M2, OpMXX6aHint (6, 0, 1, 0x0e, 0), {F1, F2, MR3}}, + {"ldfps.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0e, 1), {F1, F2, MR3}}, + {"ldfps.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0e, 3), {F1, F2, MR3}}, + {"ldfpd.sa", M2, OpMXX6aHint (6, 0, 1, 0x0f, 0), {F1, F2, MR3}}, + {"ldfpd.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0f, 1), {F1, F2, MR3}}, + {"ldfpd.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0f, 3), {F1, F2, MR3}}, + {"ldfp8.sa", M2, OpMXX6aHint (6, 0, 1, 0x0d, 0), {F1, F2, MR3}}, + {"ldfp8.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0d, 1), {F1, F2, MR3}}, + {"ldfp8.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0d, 3), {F1, F2, MR3}}, + {"ldfps.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x22, 0), {F1, F2, MR3}}, + {"ldfps.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x22, 1), {F1, F2, MR3}}, + {"ldfps.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x22, 3), {F1, F2, MR3}}, + {"ldfpd.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x23, 0), {F1, F2, MR3}}, + {"ldfpd.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x23, 1), {F1, F2, MR3}}, + {"ldfpd.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x23, 3), {F1, F2, MR3}}, + {"ldfp8.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x21, 0), {F1, F2, MR3}}, + {"ldfp8.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x21, 1), {F1, F2, MR3}}, + {"ldfp8.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x21, 3), {F1, F2, MR3}}, + {"ldfps.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x26, 0), {F1, F2, MR3}}, + {"ldfps.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x26, 1), {F1, F2, MR3}}, + {"ldfps.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x26, 3), {F1, F2, MR3}}, + {"ldfpd.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x27, 0), {F1, F2, MR3}}, + {"ldfpd.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x27, 1), {F1, F2, MR3}}, + {"ldfpd.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x27, 3), {F1, F2, MR3}}, + {"ldfp8.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x25, 0), {F1, F2, MR3}}, + {"ldfp8.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x25, 1), {F1, F2, MR3}}, + {"ldfp8.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x25, 3), {F1, F2, MR3}}, + + /* floating-point load pair w/increment by immediate */ +#define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c} + {"ldfps", LD (0x02, 0, C8)}, + {"ldfps.nt1", LD (0x02, 1, C8)}, + {"ldfps.nta", LD (0x02, 3, C8)}, + {"ldfpd", LD (0x03, 0, C16)}, + {"ldfpd.nt1", LD (0x03, 1, C16)}, + {"ldfpd.nta", LD (0x03, 3, C16)}, + {"ldfp8", LD (0x01, 0, C16)}, + {"ldfp8.nt1", LD (0x01, 1, C16)}, + {"ldfp8.nta", LD (0x01, 3, C16)}, + {"ldfps.s", LD (0x06, 0, C8)}, + {"ldfps.s.nt1", LD (0x06, 1, C8)}, + {"ldfps.s.nta", LD (0x06, 3, C8)}, + {"ldfpd.s", LD (0x07, 0, C16)}, + {"ldfpd.s.nt1", LD (0x07, 1, C16)}, + {"ldfpd.s.nta", LD (0x07, 3, C16)}, + {"ldfp8.s", LD (0x05, 0, C16)}, + {"ldfp8.s.nt1", LD (0x05, 1, C16)}, + {"ldfp8.s.nta", LD (0x05, 3, C16)}, + {"ldfps.a", LD (0x0a, 0, C8)}, + {"ldfps.a.nt1", LD (0x0a, 1, C8)}, + {"ldfps.a.nta", LD (0x0a, 3, C8)}, + {"ldfpd.a", LD (0x0b, 0, C16)}, + {"ldfpd.a.nt1", LD (0x0b, 1, C16)}, + {"ldfpd.a.nta", LD (0x0b, 3, C16)}, + {"ldfp8.a", LD (0x09, 0, C16)}, + {"ldfp8.a.nt1", LD (0x09, 1, C16)}, + {"ldfp8.a.nta", LD (0x09, 3, C16)}, + {"ldfps.sa", LD (0x0e, 0, C8)}, + {"ldfps.sa.nt1", LD (0x0e, 1, C8)}, + {"ldfps.sa.nta", LD (0x0e, 3, C8)}, + {"ldfpd.sa", LD (0x0f, 0, C16)}, + {"ldfpd.sa.nt1", LD (0x0f, 1, C16)}, + {"ldfpd.sa.nta", LD (0x0f, 3, C16)}, + {"ldfp8.sa", LD (0x0d, 0, C16)}, + {"ldfp8.sa.nt1", LD (0x0d, 1, C16)}, + {"ldfp8.sa.nta", LD (0x0d, 3, C16)}, + {"ldfps.c.clr", LD (0x22, 0, C8)}, + {"ldfps.c.clr.nt1", LD (0x22, 1, C8)}, + {"ldfps.c.clr.nta", LD (0x22, 3, C8)}, + {"ldfpd.c.clr", LD (0x23, 0, C16)}, + {"ldfpd.c.clr.nt1", LD (0x23, 1, C16)}, + {"ldfpd.c.clr.nta", LD (0x23, 3, C16)}, + {"ldfp8.c.clr", LD (0x21, 0, C16)}, + {"ldfp8.c.clr.nt1", LD (0x21, 1, C16)}, + {"ldfp8.c.clr.nta", LD (0x21, 3, C16)}, + {"ldfps.c.nc", LD (0x26, 0, C8)}, + {"ldfps.c.nc.nt1", LD (0x26, 1, C8)}, + {"ldfps.c.nc.nta", LD (0x26, 3, C8)}, + {"ldfpd.c.nc", LD (0x27, 0, C16)}, + {"ldfpd.c.nc.nt1", LD (0x27, 1, C16)}, + {"ldfpd.c.nc.nta", LD (0x27, 3, C16)}, + {"ldfp8.c.nc", LD (0x25, 0, C16)}, + {"ldfp8.c.nc.nt1", LD (0x25, 1, C16)}, + {"ldfp8.c.nc.nta", LD (0x25, 3, C16)}, +#undef LD + + /* line prefetch */ + {"lfetch", M0, OpMXX6aHint (6, 0, 0, 0x2c, 0), {MR3}}, + {"lfetch.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2c, 1), {MR3}}, + {"lfetch.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2c, 2), {MR3}}, + {"lfetch.nta", M0, OpMXX6aHint (6, 0, 0, 0x2c, 3), {MR3}}, + {"lfetch.excl", M0, OpMXX6aHint (6, 0, 0, 0x2d, 0), {MR3}}, + {"lfetch.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2d, 1), {MR3}}, + {"lfetch.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2d, 2), {MR3}}, + {"lfetch.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2d, 3), {MR3}}, + {"lfetch.fault", M0, OpMXX6aHint (6, 0, 0, 0x2e, 0), {MR3}}, + {"lfetch.fault.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2e, 1), {MR3}}, + {"lfetch.fault.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2e, 2), {MR3}}, + {"lfetch.fault.nta", M0, OpMXX6aHint (6, 0, 0, 0x2e, 3), {MR3}}, + {"lfetch.fault.excl", M0, OpMXX6aHint (6, 0, 0, 0x2f, 0), {MR3}}, + {"lfetch.fault.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2f, 1), {MR3}}, + {"lfetch.fault.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2f, 2), {MR3}}, + {"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2f, 3), {MR3}}, + + /* line prefetch w/increment by register */ + {"lfetch", M0, OpMXX6aHint (6, 1, 0, 0x2c, 0), {MR3, R2}}, + {"lfetch.nt1", M0, OpMXX6aHint (6, 1, 0, 0x2c, 1), {MR3, R2}}, + {"lfetch.nt2", M0, OpMXX6aHint (6, 1, 0, 0x2c, 2), {MR3, R2}}, + {"lfetch.nta", M0, OpMXX6aHint (6, 1, 0, 0x2c, 3), {MR3, R2}}, + {"lfetch.excl", M0, OpMXX6aHint (6, 1, 0, 0x2d, 0), {MR3, R2}}, + {"lfetch.excl.nt1", M0, OpMXX6aHint (6, 1, 0, 0x2d, 1), {MR3, R2}}, + {"lfetch.excl.nt2", M0, OpMXX6aHint (6, 1, 0, 0x2d, 2), {MR3, R2}}, + {"lfetch.excl.nta", M0, OpMXX6aHint (6, 1, 0, 0x2d, 3), {MR3, R2}}, + {"lfetch.fault", M0, OpMXX6aHint (6, 1, 0, 0x2e, 0), {MR3, R2}}, + {"lfetch.fault.nt1", M0, OpMXX6aHint (6, 1, 0, 0x2e, 1), {MR3, R2}}, + {"lfetch.fault.nt2", M0, OpMXX6aHint (6, 1, 0, 0x2e, 2), {MR3, R2}}, + {"lfetch.fault.nta", M0, OpMXX6aHint (6, 1, 0, 0x2e, 3), {MR3, R2}}, + {"lfetch.fault.excl", M0, OpMXX6aHint (6, 1, 0, 0x2f, 0), {MR3, R2}}, + {"lfetch.fault.excl.nt1", M0, OpMXX6aHint (6, 1, 0, 0x2f, 1), {MR3, R2}}, + {"lfetch.fault.excl.nt2", M0, OpMXX6aHint (6, 1, 0, 0x2f, 2), {MR3, R2}}, + {"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 1, 0, 0x2f, 3), {MR3, R2}}, + + /* semaphore operations */ + {"setf.sig", M, OpMXX6a (6, 0, 1, 0x1c), {F1, R2}}, + {"setf.exp", M, OpMXX6a (6, 0, 1, 0x1d), {F1, R2}}, + {"setf.s", M, OpMXX6a (6, 0, 1, 0x1e), {F1, R2}}, + {"setf.d", M, OpMXX6a (6, 0, 1, 0x1f), {F1, R2}}, + + {"ldfs", M, OpX6aHint (7, 0x02, 0), {F1, MR3, IMM9b}}, + {"ldfs.nt1", M, OpX6aHint (7, 0x02, 1), {F1, MR3, IMM9b}}, + {"ldfs.nta", M, OpX6aHint (7, 0x02, 3), {F1, MR3, IMM9b}}, + {"ldfd", M, OpX6aHint (7, 0x03, 0), {F1, MR3, IMM9b}}, + {"ldfd.nt1", M, OpX6aHint (7, 0x03, 1), {F1, MR3, IMM9b}}, + {"ldfd.nta", M, OpX6aHint (7, 0x03, 3), {F1, MR3, IMM9b}}, + {"ldf8", M, OpX6aHint (7, 0x01, 0), {F1, MR3, IMM9b}}, + {"ldf8.nt1", M, OpX6aHint (7, 0x01, 1), {F1, MR3, IMM9b}}, + {"ldf8.nta", M, OpX6aHint (7, 0x01, 3), {F1, MR3, IMM9b}}, + {"ldfe", M, OpX6aHint (7, 0x00, 0), {F1, MR3, IMM9b}}, + {"ldfe.nt1", M, OpX6aHint (7, 0x00, 1), {F1, MR3, IMM9b}}, + {"ldfe.nta", M, OpX6aHint (7, 0x00, 3), {F1, MR3, IMM9b}}, + {"ldfs.s", M, OpX6aHint (7, 0x06, 0), {F1, MR3, IMM9b}}, + {"ldfs.s.nt1", M, OpX6aHint (7, 0x06, 1), {F1, MR3, IMM9b}}, + {"ldfs.s.nta", M, OpX6aHint (7, 0x06, 3), {F1, MR3, IMM9b}}, + {"ldfd.s", M, OpX6aHint (7, 0x07, 0), {F1, MR3, IMM9b}}, + {"ldfd.s.nt1", M, OpX6aHint (7, 0x07, 1), {F1, MR3, IMM9b}}, + {"ldfd.s.nta", M, OpX6aHint (7, 0x07, 3), {F1, MR3, IMM9b}}, + {"ldf8.s", M, OpX6aHint (7, 0x05, 0), {F1, MR3, IMM9b}}, + {"ldf8.s.nt1", M, OpX6aHint (7, 0x05, 1), {F1, MR3, IMM9b}}, + {"ldf8.s.nta", M, OpX6aHint (7, 0x05, 3), {F1, MR3, IMM9b}}, + {"ldfe.s", M, OpX6aHint (7, 0x04, 0), {F1, MR3, IMM9b}}, + {"ldfe.s.nt1", M, OpX6aHint (7, 0x04, 1), {F1, MR3, IMM9b}}, + {"ldfe.s.nta", M, OpX6aHint (7, 0x04, 3), {F1, MR3, IMM9b}}, + {"ldfs.a", M, OpX6aHint (7, 0x0a, 0), {F1, MR3, IMM9b}}, + {"ldfs.a.nt1", M, OpX6aHint (7, 0x0a, 1), {F1, MR3, IMM9b}}, + {"ldfs.a.nta", M, OpX6aHint (7, 0x0a, 3), {F1, MR3, IMM9b}}, + {"ldfd.a", M, OpX6aHint (7, 0x0b, 0), {F1, MR3, IMM9b}}, + {"ldfd.a.nt1", M, OpX6aHint (7, 0x0b, 1), {F1, MR3, IMM9b}}, + {"ldfd.a.nta", M, OpX6aHint (7, 0x0b, 3), {F1, MR3, IMM9b}}, + {"ldf8.a", M, OpX6aHint (7, 0x09, 0), {F1, MR3, IMM9b}}, + {"ldf8.a.nt1", M, OpX6aHint (7, 0x09, 1), {F1, MR3, IMM9b}}, + {"ldf8.a.nta", M, OpX6aHint (7, 0x09, 3), {F1, MR3, IMM9b}}, + {"ldfe.a", M, OpX6aHint (7, 0x08, 0), {F1, MR3, IMM9b}}, + {"ldfe.a.nt1", M, OpX6aHint (7, 0x08, 1), {F1, MR3, IMM9b}}, + {"ldfe.a.nta", M, OpX6aHint (7, 0x08, 3), {F1, MR3, IMM9b}}, + {"ldfs.sa", M, OpX6aHint (7, 0x0e, 0), {F1, MR3, IMM9b}}, + {"ldfs.sa.nt1", M, OpX6aHint (7, 0x0e, 1), {F1, MR3, IMM9b}}, + {"ldfs.sa.nta", M, OpX6aHint (7, 0x0e, 3), {F1, MR3, IMM9b}}, + {"ldfd.sa", M, OpX6aHint (7, 0x0f, 0), {F1, MR3, IMM9b}}, + {"ldfd.sa.nt1", M, OpX6aHint (7, 0x0f, 1), {F1, MR3, IMM9b}}, + {"ldfd.sa.nta", M, OpX6aHint (7, 0x0f, 3), {F1, MR3, IMM9b}}, + {"ldf8.sa", M, OpX6aHint (7, 0x0d, 0), {F1, MR3, IMM9b}}, + {"ldf8.sa.nt1", M, OpX6aHint (7, 0x0d, 1), {F1, MR3, IMM9b}}, + {"ldf8.sa.nta", M, OpX6aHint (7, 0x0d, 3), {F1, MR3, IMM9b}}, + {"ldfe.sa", M, OpX6aHint (7, 0x0c, 0), {F1, MR3, IMM9b}}, + {"ldfe.sa.nt1", M, OpX6aHint (7, 0x0c, 1), {F1, MR3, IMM9b}}, + {"ldfe.sa.nta", M, OpX6aHint (7, 0x0c, 3), {F1, MR3, IMM9b}}, + {"ldf.fill", M, OpX6aHint (7, 0x1b, 0), {F1, MR3, IMM9b}}, + {"ldf.fill.nt1", M, OpX6aHint (7, 0x1b, 1), {F1, MR3, IMM9b}}, + {"ldf.fill.nta", M, OpX6aHint (7, 0x1b, 3), {F1, MR3, IMM9b}}, + {"ldfs.c.clr", M, OpX6aHint (7, 0x22, 0), {F1, MR3, IMM9b}}, + {"ldfs.c.clr.nt1", M, OpX6aHint (7, 0x22, 1), {F1, MR3, IMM9b}}, + {"ldfs.c.clr.nta", M, OpX6aHint (7, 0x22, 3), {F1, MR3, IMM9b}}, + {"ldfd.c.clr", M, OpX6aHint (7, 0x23, 0), {F1, MR3, IMM9b}}, + {"ldfd.c.clr.nt1", M, OpX6aHint (7, 0x23, 1), {F1, MR3, IMM9b}}, + {"ldfd.c.clr.nta", M, OpX6aHint (7, 0x23, 3), {F1, MR3, IMM9b}}, + {"ldf8.c.clr", M, OpX6aHint (7, 0x21, 0), {F1, MR3, IMM9b}}, + {"ldf8.c.clr.nt1", M, OpX6aHint (7, 0x21, 1), {F1, MR3, IMM9b}}, + {"ldf8.c.clr.nta", M, OpX6aHint (7, 0x21, 3), {F1, MR3, IMM9b}}, + {"ldfe.c.clr", M, OpX6aHint (7, 0x20, 0), {F1, MR3, IMM9b}}, + {"ldfe.c.clr.nt1", M, OpX6aHint (7, 0x20, 1), {F1, MR3, IMM9b}}, + {"ldfe.c.clr.nta", M, OpX6aHint (7, 0x20, 3), {F1, MR3, IMM9b}}, + {"ldfs.c.nc", M, OpX6aHint (7, 0x26, 0), {F1, MR3, IMM9b}}, + {"ldfs.c.nc.nt1", M, OpX6aHint (7, 0x26, 1), {F1, MR3, IMM9b}}, + {"ldfs.c.nc.nta", M, OpX6aHint (7, 0x26, 3), {F1, MR3, IMM9b}}, + {"ldfd.c.nc", M, OpX6aHint (7, 0x27, 0), {F1, MR3, IMM9b}}, + {"ldfd.c.nc.nt1", M, OpX6aHint (7, 0x27, 1), {F1, MR3, IMM9b}}, + {"ldfd.c.nc.nta", M, OpX6aHint (7, 0x27, 3), {F1, MR3, IMM9b}}, + {"ldf8.c.nc", M, OpX6aHint (7, 0x25, 0), {F1, MR3, IMM9b}}, + {"ldf8.c.nc.nt1", M, OpX6aHint (7, 0x25, 1), {F1, MR3, IMM9b}}, + {"ldf8.c.nc.nta", M, OpX6aHint (7, 0x25, 3), {F1, MR3, IMM9b}}, + {"ldfe.c.nc", M, OpX6aHint (7, 0x24, 0), {F1, MR3, IMM9b}}, + {"ldfe.c.nc.nt1", M, OpX6aHint (7, 0x24, 1), {F1, MR3, IMM9b}}, + {"ldfe.c.nc.nta", M, OpX6aHint (7, 0x24, 3), {F1, MR3, IMM9b}}, + + /* floating-point store w/increment by immediate */ + {"stfs", M, OpX6aHint (7, 0x32, 0), {MR3, F2, IMM9a}}, + {"stfs.nta", M, OpX6aHint (7, 0x32, 3), {MR3, F2, IMM9a}}, + {"stfd", M, OpX6aHint (7, 0x33, 0), {MR3, F2, IMM9a}}, + {"stfd.nta", M, OpX6aHint (7, 0x33, 3), {MR3, F2, IMM9a}}, + {"stf8", M, OpX6aHint (7, 0x31, 0), {MR3, F2, IMM9a}}, + {"stf8.nta", M, OpX6aHint (7, 0x31, 3), {MR3, F2, IMM9a}}, + {"stfe", M, OpX6aHint (7, 0x30, 0), {MR3, F2, IMM9a}}, + {"stfe.nta", M, OpX6aHint (7, 0x30, 3), {MR3, F2, IMM9a}}, + {"stf.spill", M, OpX6aHint (7, 0x3b, 0), {MR3, F2, IMM9a}}, + {"stf.spill.nta", M, OpX6aHint (7, 0x3b, 3), {MR3, F2, IMM9a}}, + + /* line prefetch w/increment by immediate */ + {"lfetch", M0, OpX6aHint (7, 0x2c, 0), {MR3, IMM9b}}, + {"lfetch.nt1", M0, OpX6aHint (7, 0x2c, 1), {MR3, IMM9b}}, + {"lfetch.nt2", M0, OpX6aHint (7, 0x2c, 2), {MR3, IMM9b}}, + {"lfetch.nta", M0, OpX6aHint (7, 0x2c, 3), {MR3, IMM9b}}, + {"lfetch.excl", M0, OpX6aHint (7, 0x2d, 0), {MR3, IMM9b}}, + {"lfetch.excl.nt1", M0, OpX6aHint (7, 0x2d, 1), {MR3, IMM9b}}, + {"lfetch.excl.nt2", M0, OpX6aHint (7, 0x2d, 2), {MR3, IMM9b}}, + {"lfetch.excl.nta", M0, OpX6aHint (7, 0x2d, 3), {MR3, IMM9b}}, + {"lfetch.fault", M0, OpX6aHint (7, 0x2e, 0), {MR3, IMM9b}}, + {"lfetch.fault.nt1", M0, OpX6aHint (7, 0x2e, 1), {MR3, IMM9b}}, + {"lfetch.fault.nt2", M0, OpX6aHint (7, 0x2e, 2), {MR3, IMM9b}}, + {"lfetch.fault.nta", M0, OpX6aHint (7, 0x2e, 3), {MR3, IMM9b}}, + {"lfetch.fault.excl", M0, OpX6aHint (7, 0x2f, 0), {MR3, IMM9b}}, + {"lfetch.fault.excl.nt1", M0, OpX6aHint (7, 0x2f, 1), {MR3, IMM9b}}, + {"lfetch.fault.excl.nt2", M0, OpX6aHint (7, 0x2f, 2), {MR3, IMM9b}}, + {"lfetch.fault.excl.nta", M0, OpX6aHint (7, 0x2f, 3), {MR3, IMM9b}}, + + {0} + }; + +#undef M0 +#undef M +#undef M2 +#undef bM +#undef bX +#undef bX2 +#undef bX3 +#undef bX4 +#undef bX6a +#undef bX6b +#undef bHint +#undef mM +#undef mX +#undef mX2 +#undef mX3 +#undef mX4 +#undef mX6a +#undef mX6b +#undef mHint +#undef OpX3 +#undef OpX3X6b +#undef OpX3X4 +#undef OpX3X4X2 +#undef OpX6aHint +#undef OpXX6aHint +#undef OpMXX6a +#undef OpMXX6aHint diff --git a/opcodes/ia64-opc-x.c b/opcodes/ia64-opc-x.c new file mode 100644 index 0000000..8432d68 --- /dev/null +++ b/opcodes/ia64-opc-x.c @@ -0,0 +1,178 @@ +/* ia64-opc-x.c -- IA-64 `X' opcode table. + Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Contributed by Timothy Wall + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ia64-opc.h" + +/* identify the specific X-unit type */ +#define X0 IA64_TYPE_X, 0 +#define X IA64_TYPE_X, 1 + +/* instruction bit fields: */ +#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) +#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) +#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) +#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0) +#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20) +#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) +#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) +#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) + +#define mBtype bBtype (-1) +#define mD bD (-1) +#define mPa bPa (-1) +#define mPr bPr (-1) +#define mVc bVc (-1) +#define mWha bWha (-1) +#define mX3 bX3 (-1) +#define mX6 bX6 (-1) + +#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ + (mOp | mX3 | mX6) +#define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc) +#define OpPaWhaD(a,b,c,d) \ + (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) +#define OpBtypePaWhaD(a,b,c,d,e) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \ + (mOp | mBtype | mPa | mWha | mD) +#define OpBtypePaWhaDPr(a,b,c,d,e,f) \ + (bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \ + (mOp | mBtype | mPa | mWha | mD | mPr) + +struct ia64_opcode ia64_opcodes_x[] = + { + {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}}, + {"nop.x", X0, OpX3X6 (0, 0, 0x01), {IMMU62}}, + {"movl", X, OpVc (6, 0), {R1, IMMU64}}, +#define BRL(a,b) \ + X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, 0 + {"brl.few", BRL (0, 0) | PSEUDO}, + {"brl", BRL (0, 0) | PSEUDO}, + {"brl.few.clr", BRL (0, 1) | PSEUDO}, + {"brl.clr", BRL (0, 1) | PSEUDO}, + {"brl.many", BRL (1, 0) | PSEUDO}, + {"brl.many.clr", BRL (1, 1) | PSEUDO}, +#undef BRL +#define BRL(a,b,c) \ + X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0 + {"brl.cond.sptk.few", BRL (0, 0, 0)}, + {"brl.cond.sptk", BRL (0, 0, 0) | PSEUDO}, + {"brl.cond.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.cond.sptk.clr", BRL (0, 0, 1) | PSEUDO}, + {"brl.cond.spnt.few", BRL (0, 1, 0)}, + {"brl.cond.spnt", BRL (0, 1, 0) | PSEUDO}, + {"brl.cond.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.cond.spnt.clr", BRL (0, 1, 1) | PSEUDO}, + {"brl.cond.dptk.few", BRL (0, 2, 0)}, + {"brl.cond.dptk", BRL (0, 2, 0) | PSEUDO}, + {"brl.cond.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.cond.dptk.clr", BRL (0, 2, 1) | PSEUDO}, + {"brl.cond.dpnt.few", BRL (0, 3, 0)}, + {"brl.cond.dpnt", BRL (0, 3, 0) | PSEUDO}, + {"brl.cond.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.cond.dpnt.clr", BRL (0, 3, 1) | PSEUDO}, + {"brl.cond.sptk.many", BRL (1, 0, 0)}, + {"brl.cond.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.cond.spnt.many", BRL (1, 1, 0)}, + {"brl.cond.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.cond.dptk.many", BRL (1, 2, 0)}, + {"brl.cond.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.cond.dpnt.many", BRL (1, 3, 0)}, + {"brl.cond.dpnt.many.clr", BRL (1, 3, 1)}, + {"brl.sptk.few", BRL (0, 0, 0)}, + {"brl.sptk", BRL (0, 0, 0) | PSEUDO}, + {"brl.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.sptk.clr", BRL (0, 0, 1) | PSEUDO}, + {"brl.spnt.few", BRL (0, 1, 0)}, + {"brl.spnt", BRL (0, 1, 0) | PSEUDO}, + {"brl.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.spnt.clr", BRL (0, 1, 1) | PSEUDO}, + {"brl.dptk.few", BRL (0, 2, 0)}, + {"brl.dptk", BRL (0, 2, 0) | PSEUDO}, + {"brl.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.dptk.clr", BRL (0, 2, 1) | PSEUDO}, + {"brl.dpnt.few", BRL (0, 3, 0)}, + {"brl.dpnt", BRL (0, 3, 0) | PSEUDO}, + {"brl.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.dpnt.clr", BRL (0, 3, 1) | PSEUDO}, + {"brl.sptk.many", BRL (1, 0, 0)}, + {"brl.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.spnt.many", BRL (1, 1, 0)}, + {"brl.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.dptk.many", BRL (1, 2, 0)}, + {"brl.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.dpnt.many", BRL (1, 3, 0)}, + {"brl.dpnt.many.clr", BRL (1, 3, 1)}, +#undef BRL +#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0 + {"brl.call.sptk.few", BRL (0, 0, 0)}, + {"brl.call.sptk", BRL (0, 0, 0) | PSEUDO}, + {"brl.call.sptk.few.clr", BRL (0, 0, 1)}, + {"brl.call.sptk.clr", BRL (0, 0, 1) | PSEUDO}, + {"brl.call.spnt.few", BRL (0, 1, 0)}, + {"brl.call.spnt", BRL (0, 1, 0) | PSEUDO}, + {"brl.call.spnt.few.clr", BRL (0, 1, 1)}, + {"brl.call.spnt.clr", BRL (0, 1, 1) | PSEUDO}, + {"brl.call.dptk.few", BRL (0, 2, 0)}, + {"brl.call.dptk", BRL (0, 2, 0) | PSEUDO}, + {"brl.call.dptk.few.clr", BRL (0, 2, 1)}, + {"brl.call.dptk.clr", BRL (0, 2, 1) | PSEUDO}, + {"brl.call.dpnt.few", BRL (0, 3, 0)}, + {"brl.call.dpnt", BRL (0, 3, 0) | PSEUDO}, + {"brl.call.dpnt.few.clr", BRL (0, 3, 1)}, + {"brl.call.dpnt.clr", BRL (0, 3, 1) | PSEUDO}, + {"brl.call.sptk.many", BRL (1, 0, 0)}, + {"brl.call.sptk.many.clr", BRL (1, 0, 1)}, + {"brl.call.spnt.many", BRL (1, 1, 0)}, + {"brl.call.spnt.many.clr", BRL (1, 1, 1)}, + {"brl.call.dptk.many", BRL (1, 2, 0)}, + {"brl.call.dptk.many.clr", BRL (1, 2, 1)}, + {"brl.call.dpnt.many", BRL (1, 3, 0)}, + {"brl.call.dpnt.many.clr", BRL (1, 3, 1)}, +#undef BRL + {0} + }; + +#undef X0 +#undef X + +#undef bBtype +#undef bD +#undef bPa +#undef bPr +#undef bVc +#undef bWha +#undef bX3 +#undef bX6 + +#undef mBtype +#undef mD +#undef mPa +#undef mPr +#undef mVc +#undef mWha +#undef mX3 +#undef mX6 + +#undef OpX3X6 +#undef OpVc +#undef OpPaWhaD +#undef OpBtypePaWhaD +#undef OpBtypePaWhaDPr diff --git a/opcodes/ia64-opc.c b/opcodes/ia64-opc.c new file mode 100644 index 0000000..a25dd66 --- /dev/null +++ b/opcodes/ia64-opc.c @@ -0,0 +1,741 @@ +/* ia64-opc.c -- Functions to access the compacted opcode table + Copyright (C) 1999 Free Software Foundation, Inc. + Written by Bob Manson of Cygnus Solutions, + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "ansidecl.h" +#include "libiberty.h" +#include "sysdep.h" +#include "ia64-asmtab.h" +#include "ia64-asmtab.c" + +const struct ia64_templ_desc ia64_templ_desc[16] = + { + { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */ + { 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, + { 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" }, + { 0, { 0, }, "-3-" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, /* 4 */ + { 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, + { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" }, + { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" }, /* 8 */ + { 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" }, + { 0, { 0, }, "-a-" }, + { 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" }, + { 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" }, /* c */ + { 0, { 0, }, "-d-" }, + { 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" }, + { 0, { 0, }, "-f-" }, + }; + + +/* Copy the prefix contained in *PTR (up to a '.' or a NUL) to DEST. + PTR will be adjusted to point to the start of the next portion + of the opcode, or at the NUL character. */ + +static void +get_opc_prefix (ptr, dest) + const char **ptr; + char *dest; +{ + char *c = strchr (*ptr, '.'); + if (c != NULL) + { + memcpy (dest, *ptr, c - *ptr); + dest[c - *ptr] = '\0'; + *ptr = c + 1; + } + else + { + int l = strlen (*ptr); + memcpy (dest, *ptr, l); + dest[l] = '\0'; + *ptr += l; + } +} + +/* Find the index of the entry in the string table corresponding to + STR; return -1 if one does not exist. */ + +static short +find_string_ent (str) + const char *str; +{ + short start = 0; + short end = sizeof (ia64_strings) / sizeof (const char *); + short i = (start + end) / 2; + + if (strcmp (str, ia64_strings[end - 1]) > 0) + { + return -1; + } + while (start <= end) + { + int c = strcmp (str, ia64_strings[i]); + if (c < 0) + { + end = i - 1; + } + else if (c == 0) + { + return i; + } + else + { + start = i + 1; + } + i = (start + end) / 2; + } + return -1; +} + +/* Find the opcode in the main opcode table whose name is STRINGINDEX, or + return -1 if one does not exist. */ + +static short +find_main_ent (nameindex) + short nameindex; +{ + short start = 0; + short end = sizeof (main_table) / sizeof (struct ia64_main_table); + short i = (start + end) / 2; + + if (nameindex < main_table[0].name_index + || nameindex > main_table[end - 1].name_index) + { + return -1; + } + while (start <= end) + { + if (nameindex < main_table[i].name_index) + { + end = i - 1; + } + else if (nameindex == main_table[i].name_index) + { + while (i > 0 && main_table[i - 1].name_index == nameindex) + { + i--; + } + return i; + } + else + { + start = i + 1; + } + i = (start + end) / 2; + } + return -1; +} + +/* Find the index of the entry in the completer table that is part of + MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or + return -1 if one does not exist. */ + +static short +find_completer (main_ent, prev_completer, name) + short main_ent; + short prev_completer; + const char *name; +{ + short name_index = find_string_ent (name); + + if (name_index < 0) + { + return -1; + } + + if (prev_completer == -1) + { + prev_completer = main_table[main_ent].completers; + } + else + { + prev_completer = completer_table[prev_completer].subentries; + } + + while (prev_completer != -1) + { + if (completer_table[prev_completer].name_index == name_index) + { + return prev_completer; + } + prev_completer = completer_table[prev_completer].alternative; + } + return -1; +} + +/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and + return the result. */ + +static ia64_insn +apply_completer (opcode, completer_index) + ia64_insn opcode; + int completer_index; +{ + ia64_insn mask = completer_table[completer_index].mask; + ia64_insn bits = completer_table[completer_index].bits; + int shiftamt = (completer_table[completer_index].offset & 63); + + mask = mask << shiftamt; + bits = bits << shiftamt; + opcode = (opcode & ~mask) | bits; + return opcode; +} + +/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in + the dis_table array, and return its value. (BITOFFSET is numbered + starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the + first byte in OP_POINTER.) */ + +static int +extract_op_bits (op_pointer, bitoffset, bits) + int op_pointer; + int bitoffset; + int bits; +{ + int res = 0; + + op_pointer += (bitoffset / 8); + + if (bitoffset % 8) + { + unsigned int op = dis_table[op_pointer++]; + int numb = 8 - (bitoffset % 8); + int mask = (1 << numb) - 1; + int bata = (bits < numb) ? bits : numb; + int delta = numb - bata; + + res = (res << bata) | ((op & mask) >> delta); + bitoffset += bata; + bits -= bata; + } + while (bits >= 8) + { + res = (res << 8) | (dis_table[op_pointer++] & 255); + bits -= 8; + } + if (bits > 0) + { + unsigned int op = (dis_table[op_pointer++] & 255); + res = (res << bits) | (op >> (8 - bits)); + } + return res; +} + +/* Examine the state machine entry at OP_POINTER in the dis_table + array, and extract its values into OPVAL and OP. The length of the + state entry in bits is returned. */ + +static int +extract_op (op_pointer, opval, op) + int op_pointer; + int *opval; + unsigned int *op; +{ + int oplen = 5; + + *op = dis_table[op_pointer]; + + if ((*op) & 0x40) + { + opval[0] = extract_op_bits (op_pointer, oplen, 5); + oplen += 5; + } + switch ((*op) & 0x30) + { + case 0x10: + { + opval[1] = extract_op_bits (op_pointer, oplen, 8); + oplen += 8; + opval[1] += op_pointer; + break; + } + case 0x20: + { + opval[1] = extract_op_bits (op_pointer, oplen, 16); + if (! (opval[1] & 32768)) + { + opval[1] += op_pointer; + } + oplen += 16; + break; + } + case 0x30: + { + oplen--; + opval[2] = extract_op_bits (op_pointer, oplen, 12); + oplen += 12; + opval[2] |= 32768; + break; + } + } + if (((*op) & 0x08) && (((*op) & 0x30) != 0x30)) + { + opval[2] = extract_op_bits (op_pointer, oplen, 16); + oplen += 16; + if (! (opval[2] & 32768)) + { + opval[2] += op_pointer; + } + } + return oplen; +} + +/* Returns a non-zero value if the opcode in the main_table list at + PLACE matches OPCODE and is of type TYPE. */ + +static int +opcode_verify (opcode, place, type) + ia64_insn opcode; + int place; + enum ia64_insn_type type; +{ + if (main_table[place].opcode_type != type) + { + return 0; + } + if (main_table[place].flags + & (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT)) + { + const struct ia64_operand *o1, *o2; + ia64_insn f2, f3; + + if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3) + { + o1 = elf64_ia64_operands + IA64_OPND_F2; + o2 = elf64_ia64_operands + IA64_OPND_F3; + (*o1->extract) (o1, opcode, &f2); + (*o2->extract) (o2, opcode, &f3); + if (f2 != f3) + return 0; + } + else + { + ia64_insn len, count; + + /* length must equal 64-count: */ + o1 = elf64_ia64_operands + IA64_OPND_LEN6; + o2 = elf64_ia64_operands + main_table[place].operands[2]; + (*o1->extract) (o1, opcode, &len); + (*o2->extract) (o2, opcode, &count); + if (len != 64 - count) + return 0; + } + } + return 1; +} + +/* Find an instruction entry in the ia64_dis_names array that matches + opcode OPCODE and is of type TYPE. Returns either a positive index + into the array, or a negative value if an entry for OPCODE could + not be found. */ + +static int +locate_opcode_ent (opcode, type) + ia64_insn opcode; + enum ia64_insn_type type; +{ + int currtest[41]; + int bitpos[41]; + int op_ptr[41]; + int currstatenum = 0; + + currtest[currstatenum] = 0; + op_ptr[currstatenum] = 0; + bitpos[currstatenum] = 40; + + while (1) + { + int op_pointer = op_ptr[currstatenum]; + unsigned int op; + int currbitnum = bitpos[currstatenum]; + int oplen; + int opval[3]; + int next_op; + int currbit; + + oplen = extract_op (op_pointer, opval, &op); + + bitpos[currstatenum] = currbitnum; + + /* Skip opval[0] bits in the instruction. */ + if (op & 0x40) + { + currbitnum -= opval[0]; + } + + /* The value of the current bit being tested. */ + currbit = opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0; + next_op = -1; + + /* We always perform the tests specified in the current state in + a particular order, falling through to the next test if the + previous one failed. */ + switch (currtest[currstatenum]) + { + case 0: + currtest[currstatenum]++; + if (currbit == 0 && (op & 0x80)) + { + /* Check for a zero bit. If this test solely checks for + a zero bit, we can check for up to 8 consecutive zero + bits (the number to check is specified by the lower 3 + bits in the state code.) + + If the state instruction matches, we go to the very + next state instruction; otherwise, try the next test. */ + + if ((op & 0xf8) == 0x80) + { + int count = op & 0x7; + int x; + + for (x = 0; x <= count; x++) + { + int i = + opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0; + if (i) + { + break; + } + } + if (x > count) + { + next_op = op_pointer + ((oplen + 7) / 8); + currbitnum -= count; + break; + } + } + else if (! currbit) + { + next_op = op_pointer + ((oplen + 7) / 8); + break; + } + } + /* FALLTHROUGH */ + case 1: + /* If the bit in the instruction is one, go to the state + instruction specified by opval[1]. */ + currtest[currstatenum]++; + if (currbit && (op & 0x30) != 0 && ((op & 0x30) != 0x30)) + { + next_op = opval[1]; + break; + } + /* FALLTHROUGH */ + case 2: + /* Don't care. Skip the current bit and go to the state + instruction specified by opval[2]. + + An encoding of 0x30 is special; this means that a 12-bit + offset into the ia64_dis_names[] array is specified. */ + currtest[currstatenum]++; + if ((op & 0x08) || ((op & 0x30) == 0x30)) + { + next_op = opval[2]; + break; + } + } + + /* If bit 15 is set in the address of the next state, an offset + in the ia64_dis_names array was specified instead. We then + check to see if an entry in the list of opcodes matches the + opcode we were given; if so, we have succeeded. */ + + if ((next_op >= 0) && (next_op & 32768)) + { + short disent = next_op & 32767; + + if (next_op > 65535) + { + abort (); + } + + /* Run through the list of opcodes to check, trying to find + one that matches. */ + while (disent >= 0) + { + int place = ia64_dis_names[disent].insn_index; + + if (opcode_verify (opcode, place, type)) + { + break; + } + if (ia64_dis_names[disent].next_flag) + { + disent++; + } + else + { + disent = -1; + } + } + + if (disent >= 0) + { + return disent; + } + else + { + /* Failed to match; try the next test in this state. */ + next_op = -2; + } + } + + /* next_op == -1 is "back up to the previous state". + next_op == -2 is "stay in this state and try the next test". + Otherwise, transition to the state indicated by next_op. */ + + if (next_op == -1) + { + currstatenum--; + if (currstatenum < 0) + { + return -1; + } + } + else if (next_op >= 0) + { + currstatenum++; + bitpos[currstatenum] = currbitnum - 1; + op_ptr[currstatenum] = next_op; + currtest[currstatenum] = 0; + } + } +} + +/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */ + +static struct ia64_opcode * +make_ia64_opcode (opcode, name, place, depind) + ia64_insn opcode; + const char *name; + int place; + int depind; +{ + struct ia64_opcode *res = + (struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode)); + res->name = xstrdup (name); + res->type = main_table[place].opcode_type; + res->num_outputs = main_table[place].num_outputs; + res->opcode = opcode; + res->mask = main_table[place].mask; + res->operands[0] = main_table[place].operands[0]; + res->operands[1] = main_table[place].operands[1]; + res->operands[2] = main_table[place].operands[2]; + res->operands[3] = main_table[place].operands[3]; + res->operands[4] = main_table[place].operands[4]; + res->flags = main_table[place].flags; + res->ent_index = place; + res->dependencies = &op_dependencies[depind]; + return res; +} + +/* Determine the ia64_opcode entry for the opcode specified by INSN + and TYPE. If a valid entry is not found, return NULL. */ +struct ia64_opcode * +ia64_dis_opcode (insn, type) + ia64_insn insn; + enum ia64_insn_type type; +{ + int disent = locate_opcode_ent (insn, type); + + if (disent < 0) + { + return NULL; + } + else + { + unsigned int cb = ia64_dis_names[disent].completer_index; + static char name[128]; + int place = ia64_dis_names[disent].insn_index; + int ci = main_table[place].completers; + ia64_insn tinsn = main_table[place].opcode; + + strcpy (name, ia64_strings [main_table[place].name_index]); + + while (cb) + { + if (cb & 1) + { + int cname = completer_table[ci].name_index; + + tinsn = apply_completer (tinsn, ci); + + if (ia64_strings[cname][0] != '\0') + { + strcat (name, "."); + strcat (name, ia64_strings[cname]); + } + if (cb != 1) + { + ci = completer_table[ci].subentries; + } + } + else + { + ci = completer_table[ci].alternative; + } + if (ci < 0) + { + abort (); + } + cb = cb >> 1; + } + if (tinsn != (insn & main_table[place].mask)) + { + abort (); + } + return make_ia64_opcode (insn, name, place, + completer_table[ci].dependencies); + } +} + +/* Search the main_opcode table starting from PLACE for an opcode that + matches NAME. Return NULL if one is not found. */ + +static struct ia64_opcode * +ia64_find_matching_opcode (name, place) + const char *name; + short place; +{ + char op[129]; + const char *suffix; + short name_index; + + if (strlen (name) > 128) + { + return NULL; + } + suffix = name; + get_opc_prefix (&suffix, op); + name_index = find_string_ent (op); + if (name_index < 0) + { + return NULL; + } + + while (main_table[place].name_index == name_index) + { + const char *curr_suffix = suffix; + ia64_insn curr_insn = main_table[place].opcode; + short completer = -1; + + do { + if (suffix[0] == '\0') + { + completer = find_completer (place, completer, suffix); + } + else + { + get_opc_prefix (&curr_suffix, op); + completer = find_completer (place, completer, op); + } + if (completer != -1) + { + curr_insn = apply_completer (curr_insn, completer); + } + } while (completer != -1 && curr_suffix[0] != '\0'); + + if (completer != -1 && curr_suffix[0] == '\0' + && completer_table[completer].terminal_completer) + { + int depind = completer_table[completer].dependencies; + return make_ia64_opcode (curr_insn, name, place, depind); + } + else + { + place++; + } + } + return NULL; +} + +/* Find the next opcode after PREV_ENT that matches PREV_ENT, or return NULL + if one does not exist. + + It is the caller's responsibility to invoke ia64_free_opcode () to + release any resources used by the returned entry. */ + +struct ia64_opcode * +ia64_find_next_opcode (prev_ent) + struct ia64_opcode *prev_ent; +{ + return ia64_find_matching_opcode (prev_ent->name, + prev_ent->ent_index + 1); +} + +/* Find the first opcode that matches NAME, or return NULL if it does + not exist. + + It is the caller's responsibility to invoke ia64_free_opcode () to + release any resources used by the returned entry. */ + +struct ia64_opcode * +ia64_find_opcode (name) + const char *name; +{ + char op[129]; + const char *suffix; + short place; + short name_index; + + if (strlen (name) > 128) + { + return NULL; + } + suffix = name; + get_opc_prefix (&suffix, op); + name_index = find_string_ent (op); + if (name_index < 0) + { + return NULL; + } + + place = find_main_ent (name_index); + + if (place < 0) + { + return NULL; + } + return ia64_find_matching_opcode (name, place); +} + +/* Free any resources used by ENT. */ +void +ia64_free_opcode (ent) + struct ia64_opcode *ent; +{ + free ((void *)ent->name); + free (ent); +} + +const struct ia64_dependency * +ia64_find_dependency (index) + int index; +{ + index = DEP(index); + + if (index < 0 || index >= sizeof(dependencies) / sizeof(dependencies[0])) + return NULL; + + return &dependencies[index]; +} diff --git a/opcodes/ia64-opc.h b/opcodes/ia64-opc.h new file mode 100644 index 0000000..8a208fd --- /dev/null +++ b/opcodes/ia64-opc.h @@ -0,0 +1,129 @@ +/* ia64-opc.h -- IA-64 opcode table. + Copyright (C) 1998, 1999 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#ifndef IA64_OPC_H +#define IA64_OPC_H + +#include "opcode/ia64.h" + +/* define a couple of abbreviations: */ + +#define bOp(x) (((ia64_insn) ((x) & 0xf)) << 37) +#define mOp bOp (-1) +#define Op(x) bOp (x), mOp + +#define FIRST IA64_OPCODE_FIRST +#define X_IN_MLX IA64_OPCODE_X_IN_MLX +#define LAST IA64_OPCODE_LAST +#define PRIV IA64_OPCODE_PRIV +#define NO_PRED IA64_OPCODE_NO_PRED +#define SLOT2 IA64_OPCODE_SLOT2 +#define PSEUDO IA64_OPCODE_PSEUDO +#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3 +#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT +#define MOD_RRBS IA64_OPCODE_MOD_RRBS + +#define AR_CCV IA64_OPND_AR_CCV +#define AR_PFS IA64_OPND_AR_PFS +#define C1 IA64_OPND_C1 +#define C8 IA64_OPND_C8 +#define C16 IA64_OPND_C16 +#define GR0 IA64_OPND_GR0 +#define IP IA64_OPND_IP +#define PR IA64_OPND_PR +#define PR_ROT IA64_OPND_PR_ROT +#define PSR IA64_OPND_PSR +#define PSR_L IA64_OPND_PSR_L +#define PSR_UM IA64_OPND_PSR_UM + +#define AR3 IA64_OPND_AR3 +#define B1 IA64_OPND_B1 +#define B2 IA64_OPND_B2 +#define CR3 IA64_OPND_CR3 +#define F1 IA64_OPND_F1 +#define F2 IA64_OPND_F2 +#define F3 IA64_OPND_F3 +#define F4 IA64_OPND_F4 +#define P1 IA64_OPND_P1 +#define P2 IA64_OPND_P2 +#define R1 IA64_OPND_R1 +#define R2 IA64_OPND_R2 +#define R3 IA64_OPND_R3 +#define R3_2 IA64_OPND_R3_2 + +#define CPUID_R3 IA64_OPND_CPUID_R3 +#define DBR_R3 IA64_OPND_DBR_R3 +#define DTR_R3 IA64_OPND_DTR_R3 +#define ITR_R3 IA64_OPND_ITR_R3 +#define IBR_R3 IA64_OPND_IBR_R3 +#define MR3 IA64_OPND_MR3 +#define MSR_R3 IA64_OPND_MSR_R3 +#define PKR_R3 IA64_OPND_PKR_R3 +#define PMC_R3 IA64_OPND_PMC_R3 +#define PMD_R3 IA64_OPND_PMD_R3 +#define RR_R3 IA64_OPND_RR_R3 + +#define CCNT5 IA64_OPND_CCNT5 +#define CNT2a IA64_OPND_CNT2a +#define CNT2b IA64_OPND_CNT2b +#define CNT2c IA64_OPND_CNT2c +#define CNT5 IA64_OPND_CNT5 +#define CNT6 IA64_OPND_CNT6 +#define CPOS6a IA64_OPND_CPOS6a +#define CPOS6b IA64_OPND_CPOS6b +#define CPOS6c IA64_OPND_CPOS6c +#define IMM1 IA64_OPND_IMM1 +#define IMM14 IA64_OPND_IMM14 +#define IMM17 IA64_OPND_IMM17 +#define IMM22 IA64_OPND_IMM22 +#define IMM44 IA64_OPND_IMM44 +#define SOF IA64_OPND_SOF +#define SOL IA64_OPND_SOL +#define SOR IA64_OPND_SOR +#define IMM8 IA64_OPND_IMM8 +#define IMM8U4 IA64_OPND_IMM8U4 +#define IMM8M1 IA64_OPND_IMM8M1 +#define IMM8M1U4 IA64_OPND_IMM8M1U4 +#define IMM8M1U8 IA64_OPND_IMM8M1U8 +#define IMM9a IA64_OPND_IMM9a +#define IMM9b IA64_OPND_IMM9b +#define IMMU2 IA64_OPND_IMMU2 +#define IMMU21 IA64_OPND_IMMU21 +#define IMMU24 IA64_OPND_IMMU24 +#define IMMU62 IA64_OPND_IMMU62 +#define IMMU64 IA64_OPND_IMMU64 +#define IMMU7a IA64_OPND_IMMU7a +#define IMMU7b IA64_OPND_IMMU7b +#define IMMU9 IA64_OPND_IMMU9 +#define INC3 IA64_OPND_INC3 +#define LEN4 IA64_OPND_LEN4 +#define LEN6 IA64_OPND_LEN6 +#define MBTYPE4 IA64_OPND_MBTYPE4 +#define MHTYPE8 IA64_OPND_MHTYPE8 +#define POS6 IA64_OPND_POS6 +#define TAG13 IA64_OPND_TAG13 +#define TAG13b IA64_OPND_TAG13b +#define TGT25 IA64_OPND_TGT25 +#define TGT25b IA64_OPND_TGT25b +#define TGT25c IA64_OPND_TGT25c +#define TGT64 IA64_OPND_TGT64 + +#endif diff --git a/opcodes/ia64-raw.tbl b/opcodes/ia64-raw.tbl new file mode 100644 index 0000000..3b39e73 --- /dev/null +++ b/opcodes/ia64-raw.tbl @@ -0,0 +1,171 @@ +Resource Name; Writers; Readers; Semantics of Dependency +ALAT; chk.a.clr, IC:mem-readers-alat, IC:mem-writers, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, IC:chk-a, invala.e; none +AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br.ret, cover, flushrs, loadrs, IC:mov-from-AR-BSP, rfi; impliedF +AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, IC:mov-from-AR-BSPSTORE; impliedF +AR[CCV]; IC:mov-to-AR-CCV; br.ia, IC:cmpxchg, IC:mov-from-AR-CCV; impliedF +AR[EC]; IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC; br.call, brl.call, br.ia, IC:mod-sched-brs, IC:mov-from-AR-EC; impliedF +AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; br.ia, IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0, fsetc, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; br.ia, IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; br.ia, IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; br.ia, IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf0.flags; IC:fp-arith-s0, fclrf.s0, IC:fcmp-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; br.ia, fchkf, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf1.flags; IC:fp-arith-s1, fclrf.s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; br.ia, fchkf.s1, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf2.flags; IC:fp-arith-s2, fclrf.s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; br.ia, fchkf.s2, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].sf3.flags; IC:fp-arith-s3, fclrf.s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; br.ia, fchkf.s3, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].traps; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF +AR[FPSR].rv; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF +AR[ITC]; IC:mov-to-AR-ITC; br.ia, IC:mov-from-AR-ITC; impliedF +AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; br.ia, IC:mov-from-AR-K+1; impliedF +AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; br.ia, IC:mod-sched-brs-counted, IC:mov-from-AR-LC; impliedF +AR[PFS]; br.call, brl.call; alloc, br.ia, br.ret, epc, IC:mov-from-AR-PFS; impliedF +AR[PFS]; IC:mov-to-AR-PFS; alloc, br.ia, epc, IC:mov-from-AR-PFS; impliedF +AR[PFS]; IC:mov-to-AR-PFS; br.ret; none +AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RNAT; impliedF +AR[RSC]; IC:mov-to-AR-RSC; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RSC, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-RNAT, IC:mov-from-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF +AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; br.ia, ld8.fill, IC:mov-from-AR-UNAT; impliedF +AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; br.ia, IC:mov-from-AR-rv+1; none +AR%, % in 48-63, 112-127; IC:mov-to-AR-ig+1; br.ia, IC:mov-from-AR-ig+1; impliedF +BR%, % in 0 - 7; br.call+1, brl.call+1; IC:indirect-brs+1, IC:indirect-brp+1, IC:mov-from-BR+1; impliedF +BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brs+1; none +BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brp+1, IC:mov-from-BR+1; impliedF +CFM; IC:mod-sched-brs; IC:mod-sched-brs; impliedF +CFM; IC:mod-sched-brs; cover, alloc, rfi, loadrs, br.ret, br.call, brl.call; impliedF +CFM; IC:mod-sched-brs; IC:cfm-readers+2; impliedF +CFM; br.call, brl.call, br.ret, clrrrb, cover, rfi; IC:cfm-readers; impliedF +CFM; alloc; IC:cfm-readers; none +CPUID#; IC:none; IC:mov-from-IND-CPUID+3; specific +CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-from-CR-CMCV; data +CR[DCR]; IC:mov-to-CR-DCR; IC:mov-from-CR-DCR, IC:mem-readers-spec; data +CR[EOI]; IC:mov-to-CR-EOI; IC:none; SC Section 10.8.3.4 +CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-from-CR-GPTA, thash; data +CR[IFA]; IC:mov-to-CR-IFA; itc.i, itc.d, itr.i, itr.d; implied +CR[IFA]; IC:mov-to-CR-IFA; IC:mov-from-CR-IFA; data +CR[IFS]; IC:mov-to-CR-IFS; IC:mov-from-CR-IFS; data +CR[IFS]; IC:mov-to-CR-IFS; rfi; implied +CR[IFS]; cover; rfi, IC:mov-from-CR-IFS; implied +CR[IHA]; IC:mov-to-CR-IHA; IC:mov-from-CR-IHA; data +CR[IIM]; IC:mov-to-CR-IIM; IC:mov-from-CR-IIM; data +CR[IIP]; IC:mov-to-CR-IIP; IC:mov-from-CR-IIP; data +CR[IIP]; IC:mov-to-CR-IIP; rfi; implied +CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-from-CR-IIPA; data +CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-from-CR-IPSR; data +CR[IPSR]; IC:mov-to-CR-IPSR; rfi; implied +CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IRR+1; data +CR[ISR]; IC:mov-to-CR-ISR; IC:mov-from-CR-ISR; data +CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-from-CR-ITIR; data +CR[ITIR]; IC:mov-to-CR-ITIR; itc.i, itc.d, itr.i, itc.d; implied +CR[ITM]; IC:mov-to-CR-ITM; IC:mov-from-CR-ITM; data +CR[ITV]; IC:mov-to-CR-ITV; IC:mov-from-CR-ITV; data +CR[IVA]; IC:mov-to-CR-IVA; IC:mov-from-CR-IVA; instr +CR[IVR]; IC:none; IC:mov-from-CR-IVR; SC Section 10.8.3.2 +CR[LID]; IC:mov-to-CR-LID; IC:mov-from-CR-LID; SC Section 10.8.3.1 +CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-from-CR-LRR+1; data +CR[PMV]; IC:mov-to-CR-PMV; IC:mov-from-CR-PMV; data +CR[PTA]; IC:mov-to-CR-PTA; IC:mov-from-CR-PTA, thash; data +CR[TPR]; IC:mov-to-CR-TPR; IC:mov-from-CR-TPR, IC:mov-from-CR-IVR; data +CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-PSR-l, rfi, rsm, ssm; SC Section 10.8.3.3 +CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:mov-from-CR-rv+1; none +DBR#; IC:mov-to-IND-DBR+3; IC:mov-from-IND-DBR+3; impliedF +DBR#; IC:mov-to-IND-DBR+3; IC:probe-all, IC:lfetch-all, IC:mem-readers, IC:mem-writers; data +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data +DTC; itc.i, itc.d, itr.i, itr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; impliedF +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF +DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF +DTR; itr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data +DTR; itr.d; ptc.g, ptc.ga, ptc.l, ptr.d, itr.d; impliedF +DTR; ptr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data +DTR; ptr.d; ptc.g, ptc.ga, ptc.l, ptr.d; none +DTR; ptr.d; itr.d, itc.d; impliedF +FR%, % in 0 - 1; IC:none; IC:fr-readers+1; none +FR%, % in 2 - 127; IC:fr-writers+1\IC:ldf-c+1\IC:ldfp-c+1; IC:fr-readers+1; impliedF +FR%, % in 2 - 127; IC:ldf-c+1, IC:ldfp-c+1; IC:fr-readers+1; none +GR0; IC:none; IC:gr-readers+1, IC:mov-immediate; none +GR%, % in 1 - 127; IC:ld-c+1+13; IC:gr-readers+1; none +GR%, % in 1 - 127; IC:gr-writers+1\IC:ld-c+1+13; IC:gr-readers+1; impliedF +IBR#; IC:mov-to-IND-IBR+3; IC:mov-from-IND-IBR+3; impliedF +InService*; IC:mov-to-CR-EOI; IC:mov-from-CR-IVR; data +InService*; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF +InService*; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; impliedF +IP; IC:all; IC:all; none +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; epc; instr +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptr.i, ptr.d, ptc.e, ptc.g, ptc.ga, ptc.l; none +ITC; itc.i, itc.d, itr.i, itr.d; epc; instr +ITC; itc.i, itc.d, itr.i, itr.d; itc.d, itc.i, itr.d, itr.i, ptr.d, ptr.i, ptc.g, ptc.ga, ptc.l; impliedF +ITC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF +ITR; itr.i; itr.i, itc.i, ptc.g, ptc.ga, ptc.l, ptr.i; impliedF +ITR; itr.i; epc; instr +ITR; ptr.i; itc.i, itr.i; impliedF +ITR; ptr.i; ptc.g, ptc.ga, ptc.l, ptr.i; none +ITR; ptr.i; epc; instr +memory; IC:mem-writers; IC:mem-readers; none +MSR#; IC:mov-to-IND-MSR+5; IC:mov-from-IND-MSR+5; specific +PKR#; IC:mov-to-IND-PKR+3; IC:mem-readers, IC:mem-writers, IC:mov-from-IND-PKR+4, IC:probe-all; data +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none +PKR#; IC:mov-to-IND-PKR+3; IC:mov-from-IND-PKR+3; impliedF +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF +PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMC+3; impliedF +PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMD+3; SC+3 Section 12.1.1 +PMD#; IC:mov-to-IND-PMD+3; IC:mov-from-IND-PMD+3; impliedF +PR0; IC:pr-writers+1; IC:pr-readers-br+1, IC:pr-readers-nobr-nomovpr+1 , IC:mov-from-PR+12, IC:mov-to-PR+12; none +PR%, % in 1 - 62; IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1 , IC:mov-from-PR, IC:mov-to-PR+12; impliedF +PR%, % in 1 - 62; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF +PR%, % in 1 - 62; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none +PR63; IC:mod-sched-brs, IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1 , IC:mov-from-PR, IC:mov-to-PR+12; impliedF +PR63; IC:pr-writers-fp+1, IC:mod-sched-brs; IC:pr-readers-br+1; impliedF +PR63; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none +PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied +PSR.ac; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data +PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF +PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied +PSR.be; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data +PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF +PSR.bn; bsw, rfi; IC:gr-readers+10, IC:gr-writers+10; impliedF +PSR.cpl; epc, br.ret, rfi; IC:priv-ops, br.call, brl.call, epc, IC:mov-from-AR-ITC, IC:mov-to-AR-ITC, IC:mov-to-AR-RSC, IC:mov-to-AR-K, IC:mov-from-IND-PMD, IC:probe-all, IC:mem-readers, IC:mem-writers, IC:lfetch-all; implied +PSR.da; rfi; IC:mem-readers, IC:lfetch-fault, IC:mem-writers, IC:probe-fault; data +PSR.db; IC:mov-to-PSR-l; IC:mem-readers, IC:mem-writers, IC:probe-fault; data +PSR.db; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.db; rfi; IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:probe-fault; data +PSR.dd; rfi; IC:mem-readers, IC:probe-fault, IC:mem-writers, IC:lfetch-fault; data +PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:fr-readers+8, IC:fr-writers+8; data +PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:fr-writers+8, IC:fr-readers+8; data +PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; br.ia; data +PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data +PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.ed; rfi; IC:lfetch-all, IC:mem-readers-spec; data +PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.i; rfi; IC:mov-from-PSR; data +PSR.ia; rfi; IC:none; none +PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; cover, itc.i, itc.d, itr.i, itr.d, IC:mov-from-CR-ITIR, IC:mov-from-CR-IFS, IC:mov-from-CR-IIM, IC:mov-from-CR-IIP, IC:mov-from-CR-IPSR, IC:mov-from-CR-ISR, IC:mov-from-CR-IFA, IC:mov-from-CR-IHA, IC:mov-from-CR-IIPA, IC:mov-to-CR-ITIR, IC:mov-to-CR-IFS, IC:mov-to-CR-IIM, IC:mov-to-CR-IIP, IC:mov-to-CR-IPSR, IC:mov-to-CR-ISR, IC:mov-to-CR-IFA, IC:mov-to-CR-IHA, IC:mov-to-CR-IIPA; data +PSR.id; rfi; IC:none; none +PSR.is; br.ia, rfi; IC:none; none +PSR.it; rfi; IC:branches, IC:mov-from-PSR, chk, epc, fchkf; data +PSR.lp; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.lp; IC:mov-to-PSR-l; br.ret; data +PSR.lp; rfi; IC:mov-from-PSR, br.ret; data +PSR.mc; rfi; IC:mov-from-PSR; none +PSR.mfh; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF +PSR.mfl; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF +PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers, IC:probe-all; data +PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.ri; rfi; IC:none; none +PSR.rt; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF +PSR.rt; IC:mov-to-PSR-l; alloc, flushrs, loadrs; data +PSR.rt; rfi; IC:mov-from-PSR, alloc, flushrs, loadrs; data +PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-AR-ITC; data +PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-IND-PMD, IC:mov-to-PSR-um, rum, sum; data +PSR.ss; rfi; IC:all; data +PSR.tb; IC:mov-to-PSR-l, rfi; IC:branches, chk, fchkf; data +PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF +PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF +RR#; IC:mov-to-IND-RR+6; IC:mem-readers, IC:mem-writers, itc.i, itc.d, itr.i, itr.d, IC:probe-all, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, tak, thash, tpa, ttag; data +RR#; IC:mov-to-IND-RR+6; IC:mov-from-IND-RR+6; impliedF +RSE; IC:rse-writers+14; IC:rse-readers+14; impliedF diff --git a/opcodes/ia64-war.tbl b/opcodes/ia64-war.tbl new file mode 100644 index 0000000..aa49e08 --- /dev/null +++ b/opcodes/ia64-war.tbl @@ -0,0 +1,2 @@ +Resource Name; Readers; Writers; Results of Dependency +PR63; IC:pr-readers-br+1; IC:mod-sched-brs; impliedF diff --git a/opcodes/ia64-waw.tbl b/opcodes/ia64-waw.tbl new file mode 100644 index 0000000..0fa743e --- /dev/null +++ b/opcodes/ia64-waw.tbl @@ -0,0 +1,125 @@ +Resource Name; Writers; Writers; Semantics of Dependency +ALAT; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; none +AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; impliedF +AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; impliedF +AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF +AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; impliedF +AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; IC:mov-to-AR-FPSR, fsetc.s0; impliedF +AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; IC:mov-to-AR-FPSR, fsetc.s1; impliedF +AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; IC:mov-to-AR-FPSR, fsetc.s2; impliedF +AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; IC:mov-to-AR-FPSR, fsetc.s3; impliedF +AR[FPSR].sf0.flags; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; none +AR[FPSR].sf0.flags; fclrf.s0, IC:fcmp-s0, IC:fp-arith-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; fclrf.s0, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].sf1.flags; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; none +AR[FPSR].sf1.flags; fclrf.s1, IC:fcmp-s1, IC:fp-arith-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; fclrf.s1, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].sf2.flags; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; none +AR[FPSR].sf2.flags; fclrf.s2, IC:fcmp-s2, IC:fp-arith-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; fclrf.s2, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].sf3.flags; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; none +AR[FPSR].sf3.flags; fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; fclrf.s3, IC:mov-to-AR-FPSR; impliedF +AR[FPSR].rv; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF +AR[FPSR].traps; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF +AR[ITC]; IC:mov-to-AR-ITC; IC:mov-to-AR-ITC; impliedF +AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; IC:mov-to-AR-K+1; impliedF +AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; impliedF +AR[PFS]; br.call, brl.call; br.call, brl.call; none +AR[PFS]; br.call, brl.call; IC:mov-to-AR-PFS; impliedF +AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF +AR[RSC]; IC:mov-to-AR-RSC; IC:mov-to-AR-RSC; impliedF +AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; IC:mov-to-AR-UNAT, st8.spill; impliedF +AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; IC:none; none +AR%, % in 48 - 63, 112-127; IC:mov-to-AR-ig+1; IC:mov-to-AR-ig+1; impliedF +BR%, % in 0 - 7; br.call+1, brl.call+1; IC:mov-to-BR+1; impliedF +BR%, % in 0 - 7; IC:mov-to-BR+1; IC:mov-to-BR+1; impliedF +BR%, % in 0 - 7; br.call+1, brl.call+1; br.call+1, brl.call+1; none +CFM; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; impliedF +CPUID#; IC:none; IC:none; none +CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-to-CR-CMCV; impliedF +CR[DCR]; IC:mov-to-CR-DCR; IC:mov-to-CR-DCR; impliedF +CR[EOI]; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; SC Section 10.8.3.4 +CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-to-CR-GPTA; impliedF +CR[IFA]; IC:mov-to-CR-IFA; IC:mov-to-CR-IFA; impliedF +CR[IFS]; IC:mov-to-CR-IFS, cover; IC:mov-to-CR-IFS, cover; impliedF +CR[IHA]; IC:mov-to-CR-IHA; IC:mov-to-CR-IHA; impliedF +CR[IIM]; IC:mov-to-CR-IIM; IC:mov-to-CR-IIM; impliedF +CR[IIP]; IC:mov-to-CR-IIP; IC:mov-to-CR-IIP; impliedF +CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-to-CR-IIPA; impliedF +CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-to-CR-IPSR; impliedF +CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF +CR[ISR]; IC:mov-to-CR-ISR; IC:mov-to-CR-ISR; impliedF +CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-to-CR-ITIR; impliedF +CR[ITM]; IC:mov-to-CR-ITM; IC:mov-to-CR-ITM; impliedF +CR[ITV]; IC:mov-to-CR-ITV; IC:mov-to-CR-ITV; impliedF +CR[IVA]; IC:mov-to-CR-IVA; IC:mov-to-CR-IVA; impliedF +CR[IVR]; IC:none; IC:none; SC +CR[LID]; IC:mov-to-CR-LID; IC:mov-to-CR-LID; SC +CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-to-CR-LRR+1; impliedF +CR[PMV]; IC:mov-to-CR-PMV; IC:mov-to-CR-PMV; impliedF +CR[PTA]; IC:mov-to-CR-PTA; IC:mov-to-CR-PTA; impliedF +CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-CR-TPR; impliedF +CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:none; none +DBR#; IC:mov-to-IND-DBR+3; IC:mov-to-IND-DBR+3; impliedF +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none +DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF +DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF +DTR; itr.d; itr.d; impliedF +DTR; itr.d; ptr.d; impliedF +DTR; ptr.d; ptr.d; none +FR%, % in 0 - 1; IC:none; IC:none; none +FR%, % in 2 - 127; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; impliedF +GR0; IC:none; IC:none; none +GR%, % in 1 - 127; IC:ld-c+1, IC:gr-writers+1; IC:ld-c+1, IC:gr-writers+1; impliedF +IBR#; IC:mov-to-IND-IBR+3; IC:mov-to-IND-IBR+3; impliedF +InService*; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; SC +IP; IC:all; IC:all; none +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none +ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF +ITR; itr.i; itr.i, ptr.i; impliedF +ITR; ptr.i; ptr.i; none +memory; IC:mem-writers; IC:mem-writers; none +MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none +PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF +PMC#; IC:mov-to-IND-PMC+3; IC:mov-to-IND-PMC+3; impliedF +PMD#; IC:mov-to-IND-PMD+3; IC:mov-to-IND-PMD+3; impliedF +PR0; IC:pr-writers+1; IC:pr-writers+1; none +PR%, % in 1 - 62; IC:pr-and-writers+1; IC:pr-and-writers+1; none +PR%, % in 1 - 62; IC:pr-or-writers+1; IC:pr-or-writers+1; none +PR%, % in 1 - 62; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR+7; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR+7; impliedF +PR63; IC:pr-and-writers+1; IC:pr-and-writers+1; none +PR63; IC:pr-or-writers+1; IC:pr-or-writers+1; none +PR63; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR+7; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR+7; impliedF +PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.bn; bsw, rfi; bsw, rfi; impliedF +PSR.cpl; epc, br.ret, rfi; epc, br.ret, rfi; impliedF +PSR.da; rfi; rfi; impliedF +PSR.db; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.dd; rfi; rfi; impliedF +PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ed; rfi; rfi; impliedF +PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ia; rfi; rfi; impliedF +PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.id; rfi; rfi; impliedF +PSR.is; br.ia, rfi; br.ia, rfi; impliedF +PSR.it; rfi; rfi; impliedF +PSR.lp; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.mc; rfi; rfi; impliedF +PSR.mfh; IC:fr-writers+9; IC:fr-writers+9; none +PSR.mfh; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.mfl; IC:fr-writers+9; IC:fr-writers+9; none +PSR.mfl; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ri; rfi; rfi; impliedF +PSR.rt; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +PSR.ss; rfi; rfi; impliedF +PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF +PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF +RR#; IC:mov-to-IND-RR+6; IC:mov-to-IND-RR+6; impliedF +RSE; IC:rse-writers+14; IC:rse-writers+14; impliedF -- cgit v1.1