From 5a9f5403c75c8ae1f4935a9a0904949f52d9e3aa Mon Sep 17 00:00:00 2001 From: Nelson Chu Date: Tue, 26 Jan 2021 18:02:38 +0800 Subject: RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. * Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros. --- opcodes/ChangeLog | 15 +++++++++++++++ opcodes/riscv-dis.c | 37 +++++++++++++++++-------------------- opcodes/riscv-opc.c | 34 ++++++++++++++++++++++------------ 3 files changed, 54 insertions(+), 32 deletions(-) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 162aafcb..086dd33 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,18 @@ +2021-02-19 Nelson Chu + + PR 27158 + * riscv-dis.c (print_insn_args): Updated encoding macros. + * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. + (match_c_addi16sp): Updated encoding macros. + (match_c_lui): Likewise. + (match_c_lui_with_hint): Likewise. + (match_c_addi4spn): Likewise. + (match_c_slli): Likewise. + (match_slli_as_c_slli): Likewise. + (match_c_slli64): Likewise. + (match_srxi_as_c_srxi): Likewise. + (riscv_insn_types): Added .insn css/cl/cs. + 2021-02-18 Nelson Chu * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 667dbd8..cc80d90 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -204,54 +204,51 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) print (info->stream, "%s", riscv_gpr_names[EXTRACT_OPERAND (CRS2, l)]); break; - case 'i': - print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l)); - break; case 'o': case 'j': - print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_CITYPE_IMM (l)); break; case 'k': - print (info->stream, "%d", (int)EXTRACT_RVC_LW_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_CLTYPE_LW_IMM (l)); break; case 'l': - print (info->stream, "%d", (int)EXTRACT_RVC_LD_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_CLTYPE_LD_IMM (l)); break; case 'm': - print (info->stream, "%d", (int)EXTRACT_RVC_LWSP_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_CITYPE_LWSP_IMM (l)); break; case 'n': - print (info->stream, "%d", (int)EXTRACT_RVC_LDSP_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_CITYPE_LDSP_IMM (l)); break; case 'K': - print (info->stream, "%d", (int)EXTRACT_RVC_ADDI4SPN_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_CIWTYPE_ADDI4SPN_IMM (l)); break; case 'L': - print (info->stream, "%d", (int)EXTRACT_RVC_ADDI16SP_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_CITYPE_ADDI16SP_IMM (l)); break; case 'M': - print (info->stream, "%d", (int)EXTRACT_RVC_SWSP_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_CSSTYPE_SWSP_IMM (l)); break; case 'N': - print (info->stream, "%d", (int)EXTRACT_RVC_SDSP_IMM (l)); + print (info->stream, "%d", (int)EXTRACT_CSSTYPE_SDSP_IMM (l)); break; case 'p': - info->target = EXTRACT_RVC_B_IMM (l) + pc; + info->target = EXTRACT_CBTYPE_IMM (l) + pc; (*info->print_address_func) (info->target, info); break; case 'a': - info->target = EXTRACT_RVC_J_IMM (l) + pc; + info->target = EXTRACT_CJTYPE_IMM (l) + pc; (*info->print_address_func) (info->target, info); break; case 'u': print (info->stream, "0x%x", - (int)(EXTRACT_RVC_IMM (l) & (RISCV_BIGIMM_REACH-1))); + (int)(EXTRACT_CITYPE_IMM (l) & (RISCV_BIGIMM_REACH-1))); break; case '>': - print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x3f); + print (info->stream, "0x%x", (int)EXTRACT_CITYPE_IMM (l) & 0x3f); break; case '<': - print (info->stream, "0x%x", (int)EXTRACT_RVC_IMM (l) & 0x1f); + print (info->stream, "0x%x", (int)EXTRACT_CITYPE_IMM (l) & 0x1f); break; case 'T': /* Floating-point RS2. */ print (info->stream, "%s", @@ -326,12 +323,12 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) break; case 'a': - info->target = EXTRACT_UJTYPE_IMM (l) + pc; + info->target = EXTRACT_JTYPE_IMM (l) + pc; (*info->print_address_func) (info->target, info); break; case 'p': - info->target = EXTRACT_SBTYPE_IMM (l) + pc; + info->target = EXTRACT_BTYPE_IMM (l) + pc; (*info->print_address_func) (info->target, info); break; @@ -341,7 +338,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) else if ((l & MASK_LUI) == MATCH_LUI) pd->hi_addr[rd] = EXTRACT_UTYPE_IMM (l); else if ((l & MASK_C_LUI) == MATCH_C_LUI) - pd->hi_addr[rd] = EXTRACT_RVC_LUI_IMM (l); + pd->hi_addr[rd] = EXTRACT_CITYPE_LUI_IMM (l); print (info->stream, "%s", riscv_gpr_names[rd]); break; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 50a3f30..e0552db 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -73,7 +73,7 @@ const char * const riscv_fpr_names_abi[NFPR] = #define MASK_RD (OP_MASK_RD << OP_SH_RD) #define MASK_CRS2 (OP_MASK_CRS2 << OP_SH_CRS2) #define MASK_IMM ENCODE_ITYPE_IMM (-1U) -#define MASK_RVC_IMM ENCODE_RVC_IMM (-1U) +#define MASK_RVC_IMM ENCODE_CITYPE_IMM (-1U) #define MASK_UIMM ENCODE_UTYPE_IMM (-1U) #define MASK_RM (OP_MASK_RM << OP_SH_RM) #define MASK_PRED (OP_MASK_PRED << OP_SH_PRED) @@ -135,8 +135,7 @@ static int match_c_addi16sp (const struct riscv_opcode *op, insn_t insn) { return (match_opcode (op, insn) - && (((insn & MASK_RD) >> OP_SH_RD) == 2) - && EXTRACT_RVC_ADDI16SP_IMM (insn) != 0); + && (((insn & MASK_RD) >> OP_SH_RD) == 2)); } static int @@ -144,7 +143,7 @@ match_c_lui (const struct riscv_opcode *op, insn_t insn) { return (match_rd_nonzero (op, insn) && (((insn & MASK_RD) >> OP_SH_RD) != 2) - && EXTRACT_RVC_LUI_IMM (insn) != 0); + && EXTRACT_CITYPE_LUI_IMM (insn) != 0); } /* We don't allow lui zero,X to become a c.lui hint, so we need a separate @@ -155,13 +154,13 @@ match_c_lui_with_hint (const struct riscv_opcode *op, insn_t insn) { return (match_opcode (op, insn) && (((insn & MASK_RD) >> OP_SH_RD) != 2) - && EXTRACT_RVC_LUI_IMM (insn) != 0); + && EXTRACT_CITYPE_LUI_IMM (insn) != 0); } static int match_c_addi4spn (const struct riscv_opcode *op, insn_t insn) { - return match_opcode (op, insn) && EXTRACT_RVC_ADDI4SPN_IMM (insn) != 0; + return match_opcode (op, insn) && EXTRACT_CIWTYPE_ADDI4SPN_IMM (insn) != 0; } /* This requires a non-zero shift. A zero rd is a hint, so is allowed. */ @@ -169,7 +168,7 @@ match_c_addi4spn (const struct riscv_opcode *op, insn_t insn) static int match_c_slli (const struct riscv_opcode *op, insn_t insn) { - return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0; + return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0; } /* This requires a non-zero rd, and a non-zero shift. */ @@ -177,7 +176,7 @@ match_c_slli (const struct riscv_opcode *op, insn_t insn) static int match_slli_as_c_slli (const struct riscv_opcode *op, insn_t insn) { - return match_rd_nonzero (op, insn) && EXTRACT_RVC_IMM (insn) != 0; + return match_rd_nonzero (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0; } /* This requires a zero shift. A zero rd is a hint, so is allowed. */ @@ -185,7 +184,7 @@ match_slli_as_c_slli (const struct riscv_opcode *op, insn_t insn) static int match_c_slli64 (const struct riscv_opcode *op, insn_t insn) { - return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) == 0; + return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) == 0; } /* This is used for both srli and srai. This requires a non-zero shift. @@ -194,7 +193,7 @@ match_c_slli64 (const struct riscv_opcode *op, insn_t insn) static int match_srxi_as_c_srxi (const struct riscv_opcode *op, insn_t insn) { - return match_opcode (op, insn) && EXTRACT_RVC_IMM (insn) != 0; + return match_opcode (op, insn) && EXTRACT_CITYPE_IMM (insn) != 0; } const struct riscv_opcode riscv_opcodes[] = @@ -847,7 +846,6 @@ const struct riscv_opcode riscv_insn_types[] = {"sb", 0, INSN_CLASS_F, "O4,F3,S,t,p", 0, 0, match_opcode, 0 }, {"sb", 0, INSN_CLASS_F, "O4,F3,s,T,p", 0, 0, match_opcode, 0 }, {"sb", 0, INSN_CLASS_F, "O4,F3,S,T,p", 0, 0, match_opcode, 0 }, - {"b", 0, INSN_CLASS_I, "O4,F3,s,t,p", 0, 0, match_opcode, 0 }, {"b", 0, INSN_CLASS_F, "O4,F3,S,t,p", 0, 0, match_opcode, 0 }, {"b", 0, INSN_CLASS_F, "O4,F3,s,T,p", 0, 0, match_opcode, 0 }, @@ -858,7 +856,6 @@ const struct riscv_opcode riscv_insn_types[] = {"uj", 0, INSN_CLASS_I, "O4,d,a", 0, 0, match_opcode, 0 }, {"uj", 0, INSN_CLASS_F, "O4,D,a", 0, 0, match_opcode, 0 }, - {"j", 0, INSN_CLASS_I, "O4,d,a", 0, 0, match_opcode, 0 }, {"j", 0, INSN_CLASS_F, "O4,D,a", 0, 0, match_opcode, 0 }, @@ -873,6 +870,19 @@ const struct riscv_opcode riscv_insn_types[] = {"ciw", 0, INSN_CLASS_C, "O2,CF3,Ct,C8", 0, 0, match_opcode, 0 }, {"ciw", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C8", 0, 0, match_opcode, 0 }, +{"css", 0, INSN_CLASS_C, "O2,CF3,CV,C6", 0, 0, match_opcode, 0 }, +{"css", 0, INSN_CLASS_F_AND_C, "O2,CF3,CT,C6", 0, 0, match_opcode, 0 }, + +{"cl", 0, INSN_CLASS_C, "O2,CF3,Ct,C5(Cs)", 0, 0, match_opcode, 0 }, +{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(Cs)", 0, 0, match_opcode, 0 }, +{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,Ct,C5(CS)", 0, 0, match_opcode, 0 }, +{"cl", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(CS)", 0, 0, match_opcode, 0 }, + +{"cs", 0, INSN_CLASS_C, "O2,CF3,Ct,C5(Cs)", 0, 0, match_opcode, 0 }, +{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(Cs)", 0, 0, match_opcode, 0 }, +{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,Ct,C5(CS)", 0, 0, match_opcode, 0 }, +{"cs", 0, INSN_CLASS_F_AND_C, "O2,CF3,CD,C5(CS)", 0, 0, match_opcode, 0 }, + {"ca", 0, INSN_CLASS_C, "O2,CF6,CF2,Cs,Ct", 0, 0, match_opcode, 0 }, {"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,CS,Ct", 0, 0, match_opcode, 0 }, {"ca", 0, INSN_CLASS_F_AND_C, "O2,CF6,CF2,Cs,CD", 0, 0, match_opcode, 0 }, -- cgit v1.1