From 437e2ff1ad8a1d5f20ebd27af2f04e1a1bcb48a7 Mon Sep 17 00:00:00 2001
From: Nelson Chu <nelson.chu@sifive.com>
Date: Wed, 27 Oct 2021 18:54:41 +0800
Subject: RISC-V: Tidy riscv assembler and disassembler.

Tidy the gas/config/tc-riscv.c and opcodes/riscv-dis.c, to prepare for
moving the released extensions (including released vendor extensions)
from integration branch back to mainline.

* Added parts of missing comments.

* Updated md_show_usage.

* For validate_riscv_insn, riscv_ip and print_insn_args, unify the
  following pointer names,
  - oparg: pointed to the parsed operand defined in the riscv_opcodes.
  - asarg: pointed to the parsed operand from assembly.
  - opargStart: recorded the parsed operand name from riscv_opcodes.
  - asargStart: recorded the parsed operand name from assembly.

gas/
	* config/tc-riscv.c: Added parts of missind comments and updated
	the md_show_usage.
	(riscv_multi_subset_supports): Tidy codes.
	(validate_riscv_insn): Unify the pointer names, oparg, asarg,
	opargStart and asargStart, to prepare for moving the released
	extensions from integration branch back to mainline.
	(riscv_ip): Likewise.
	(macro_build): Added fmtStart, also used to prepare for moving
	released extensions.
	(md_show_usage): Added missing descriptions for new options.
opcodes/
	* riscv-dis.c (print_insn_args): Unify the pointer names,
	oparg and opargStart, to prepare for moving the released
	extensions from integration branch back to mainline.
---
 opcodes/riscv-dis.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

(limited to 'opcodes')

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 2e28ba7..1a09440 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -177,22 +177,24 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
 /* Print insn arguments for 32/64-bit code.  */
 
 static void
-print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
+print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info)
 {
   struct riscv_private_data *pd = info->private_data;
   int rs1 = (l >> OP_SH_RS1) & OP_MASK_RS1;
   int rd = (l >> OP_SH_RD) & OP_MASK_RD;
   fprintf_ftype print = info->fprintf_func;
+  const char *opargStart;
 
-  if (*d != '\0')
+  if (*oparg != '\0')
     print (info->stream, "\t");
 
-  for (; *d != '\0'; d++)
+  for (; *oparg != '\0'; oparg++)
     {
-      switch (*d)
+      opargStart = oparg;
+      switch (*oparg)
 	{
 	case 'C': /* RVC */
-	  switch (*++d)
+	  switch (*++oparg)
 	    {
 	    case 's': /* RS1 x8-x15.  */
 	    case 'w': /* RS1 x8-x15.  */
@@ -281,12 +283,12 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 	case ')':
 	case '[':
 	case ']':
-	  print (info->stream, "%c", *d);
+	  print (info->stream, "%c", *oparg);
 	  break;
 
 	case '0':
 	  /* Only print constant 0 if it is the last argument.  */
-	  if (!d[1])
+	  if (!oparg[1])
 	    print (info->stream, "0");
 	  break;
 
@@ -432,7 +434,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 	default:
 	  /* xgettext:c-format */
 	  print (info->stream, _("# internal error, undefined modifier (%c)"),
-		 *d);
+		 *opargStart);
 	  return;
 	}
     }
-- 
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