From 3086ed9a458f9bc3a52633fc2a10ffc3f21753f4 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Fri, 17 Nov 2023 11:23:20 +0100 Subject: x86: CPU-qualify {disp16} / {disp32} {disp16} is invalid to use in 64-bit mode, while {disp32} is invalid to use on pre-386 CPUs. The latter, also affecting other (real) prefixes, further requires that like for insns we fully check the CPU flags; till now only Cpu64/CpuNo64 were taken into consideration. --- opcodes/i386-opc.tbl | 2 +- opcodes/i386-tbl.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'opcodes') diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index c31bf20..167c0a0 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -892,7 +892,7 @@ rex.wrxb, 0x4f, x64, NoSuf|IsPrefix, {} // Pseudo prefixes (base_opcode == PSEUDO_PREFIX) - diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 527793c..e662a50 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -5164,7 +5164,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, @@ -5172,7 +5172,7 @@ static const insn_template i386_optab[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, -- cgit v1.1