From 28215275a6bbb7c4b4c2d683a1d94fead7dacc35 Mon Sep 17 00:00:00 2001 From: Graham Markall Date: Mon, 13 Jun 2016 09:03:05 +0100 Subject: [ARC] Add ldbit for nps This commit adds the ldbit instruction for the NPS-400. The ldbit instruction uses the same encoding as the ld instruction, but sets the ZZ field to 11 (which is a reserved setting), and sets the AA field to 1 or 2 for the x2 and x4 flags respectively. --- opcodes/ChangeLog | 5 +++++ opcodes/arc-nps400-tbl.h | 21 +++++++++++++++++++++ opcodes/arc-opc.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0c39a6d..9fb6d88 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2016-06-13 Graham Markall + * arc-nps400-tbl.h: Add ldbit instruction. + * arc-opc.c: Add flag classes required for ldbit. + +2016-06-13 Graham Markall + * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf * arc-opc.c: Add flag classes, insert/extract functions, and operands to support the above instructions. diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h index 233e441..b8ec0af 100644 --- a/opcodes/arc-nps400-tbl.h +++ b/opcodes/arc-nps400-tbl.h @@ -503,6 +503,27 @@ HASH_P(3, 0xC) /* addf<.f> 0,limm,u6 0011111001100011F111uuuuuu111110 */ { "addf", 0x3e63703e, 0xffff703f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }}, +/* ldbit<.x2|.x4>.di<.cl> a,[b] 00010bbb00000000SBBB10011XAAAAAA */ +{ "ldbit", 0x10000980, 0xf8ff8980, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, RB, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }}, + +/* ldbit<.x2|.x4>.di<.cl> a,[b,s9] 00010bbbssssssssSBBB10011XAAAAAA */ +{ "ldbit", 0x10000980, 0xf8000980, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }}, + +/* ldbit<.x2|.x4>.di<.cl> a,[limm] 0001011000000000011110011XAAAAAA */ +{ "ldbit", 0x16007980, 0xfffff980, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, LIMM, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }}, + +/* ldbit<.x2|.x4>.di<.cl> a,[limm,s9] 00010110ssssssssS11110011XAAAAAA */ +{ "ldbit", 0x16007980, 0xff007980, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }}, + +/* ldbit<.x2|.x4>.di<.cl> a,[b,c] 00100bbb0011011X1BBBCCCCCCAAAAAA */ +{ "ldbit", 0x20368000, 0xf83e8000, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, RB, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }}, + +/* ldbit<.x2|.x4>.di<.cl> a,[b,limm] 00100bbb0011011X1BBB111110AAAAAA */ +{ "ldbit", 0x20368f80, 0xf83e8fc0, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, RB, LIMM, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }}, + +/* ldbit<.x2|.x4>.di<.cl> a,[limm,c] 001001100011011X1111CCCCCCAAAAAA */ +{ "ldbit", 0x2636f000, 0xff3ef000, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, LIMM, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }}, + /**** Pipeline Control Instructions ****/ /* schd<.rw|.rd> */ diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index f706ffa..433fdcc 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -1387,6 +1387,27 @@ const struct arc_flag_operand arc_flag_operands[] = #define F_NPS_P3 (F_NPS_P2 + 1) { "p3", 0, 0, 0, 1 }, + +#define F_NPS_LDBIT_DI (F_NPS_P3 + 1) + { "di", 0, 0, 0, 1 }, + +#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1) + { "cl", 1, 1, 6, 1 }, + +#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1) + { "cl", 1, 1, 16, 1 }, + +#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1) + { "x2", 1, 2, 9, 1 }, + +#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1) + { "x2", 1, 2, 22, 1 }, + +#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1) + { "x4", 2, 2, 9, 1 }, + +#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1) + { "x4", 2, 2, 22, 1 }, }; const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); @@ -1511,6 +1532,21 @@ const struct arc_flag_class arc_flag_classes[] = #define C_NPS_P3 (C_NPS_P2 + 1) { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }}, + +#define C_NPS_LDBIT_DI (C_NPS_P3 + 1) + { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }}, + +#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1) + { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }}, + +#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1) + { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }}, + +#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1) + { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }}, + +#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1) + { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }}, }; const unsigned char flags_none[] = { 0 }; -- cgit v1.1