From 077b8428ab2abe6e4c66216151c518c03467323c Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Sat, 25 Nov 2000 00:21:40 +0000 Subject: Add ARM v5t, v5te and XScale support --- opcodes/ChangeLog | 10 ++++++++ opcodes/arm-dis.c | 26 ++++++++++++++++++++ opcodes/arm-opc.h | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 105 insertions(+), 4 deletions(-) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 7c3ba0e..b323984 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2000-11-24 Nick Clifton + + * arm-opc.h: Add new opcode formatting parameter 'B'. + (arm_opcodes): Add XScale, v5, and v5te instructions. + (thumb_opcodes): Add v5t instructions. + + * arm-dis.c (print_insn_arm): Handle new 'B' format + parameter. + (print_insn_thumb): Decode BLX(1) instruction. + 2000-11-21 Chris Demetriou * mips-opc.c: Fix file header comment. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 0ddcffa..262406b 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -421,6 +421,29 @@ print_insn_arm (pc, info, given) } break; + case 'B': + /* Print ARM V5 BLX(1) address: pc+25 bits. */ + { + bfd_vma address; + bfd_vma offset = 0; + + if (given & 0x00800000) + /* Is signed, hi bits should be ones. */ + offset = (-1) ^ 0x00ffffff; + + /* Offset is (SignExtend(offset field)<<2). */ + offset += given & 0x00ffffff; + offset <<= 2; + address = offset + pc + 8; + + if (given & 0x01000000) + /* H bit allows addressing to 2-byte boundaries. */ + address += 2; + + info->print_address_func (address, info); + } + break; + case 'C': func (stream, "_"); if (given & 0x80000) @@ -648,6 +671,9 @@ print_insn_thumb (pc, info, given) info->bytes_per_chunk = 4; info->bytes_per_line = 4; + if ((given & 0x10000000) == 0) + func (stream, "blx\t"); + else func (stream, "bl\t"); info->print_address_func (BDISP23 (given) * 2 + pc + 4, info); diff --git a/opcodes/arm-opc.h b/opcodes/arm-opc.h index 5ecde4b..42ab954 100644 --- a/opcodes/arm-opc.h +++ b/opcodes/arm-opc.h @@ -51,6 +51,7 @@ struct thumb_opcode %a print address for ldr/str instruction %s print address for ldr/str halfword/signextend instruction %b print branch destination + %B print arm BLX(1) destination %A print address for ldc/stc/ldf/stf instruction %m print register mask for ldm/stm instruction %C print the PSR sub type. @@ -75,7 +76,7 @@ Thumb specific format options: static struct arm_opcode arm_opcodes[] = { - /* ARM instructions */ + /* ARM instructions. */ {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, @@ -83,6 +84,59 @@ static struct arm_opcode arm_opcodes[] = {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, + + /* XScale instructions. */ + {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, + {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, + {0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, + {0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, + {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, + {0xf450f000, 0xfc70f000, "pld\t%a"}, + + /* V5 Instructions. */ + {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, + {0xfa000000, 0xfe000000, "blx\t%B"}, + {0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"}, + {0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, + {0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"}, + {0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"}, + {0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, + {0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + {0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, + + /* V5E "El Segundo" Instructions. */ + {0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"}, + {0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"}, + {0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + + {0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + + {0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + + {0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"}, + {0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"}, + {0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"}, + {0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"}, + + {0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"}, + {0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"}, + + {0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"}, + {0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"}, + {0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"}, + {0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, + + {0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + + /* ARM Instructions. */ {0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"}, {0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"}, {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, @@ -174,10 +228,21 @@ static struct arm_opcode arm_opcodes[] = static struct thumb_opcode thumb_opcodes[] = { - /* Thumb instructions */ - {0x46C0, 0xFFFF, "nop\t\t\t(mov r8,r8)"}, /* format 5 instructions do not update the PSR */ + /* Thumb instructions. */ + + /* ARM V5 ISA extends Thumb. */ + {0xbe00, 0xff00, "bkpt\t%0-7x"}, + {0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */ + /* Note: this is BLX(2). BLX(1) is done in arm-dis.c/print_insn_thumb() + as an extension of the special processing there for Thumb BL. + BL and BLX(1) involve 2 successive 16-bit instructions, which must + always appear together in the correct order. So, the empty + string is put in this table, and the string interpreter takes + to mean it has a pair of BL-ish instructions. */ + {0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"}, + /* Format 5 instructions do not update the PSR. */ {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"}, - /* format 4 */ + /* Format 4. */ {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"}, {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"}, {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"}, -- cgit v1.1