From a4ddc54ec1cd187c844ca631fe0315bf1d78e96f Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Tue, 2 May 2017 11:53:30 +0100 Subject: MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassembly Correct the disassembly of the PC-relative immediate argument of the MIPS16 synthetic LA, LW, DLA and LD instructions and do not mask the LSB, which in this case is a part of the data address rather than the ISA bit and has to be fully presented. opcodes/ * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps and branches and not synthetic data instructions. binutils/ * testsuite/binutils-all/mips/mips16-undecoded.d: Adjust the disassembly of PC-relative LA and LW synthetic instructions. --- opcodes/mips-dis.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'opcodes/mips-dis.c') diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 4a08d8a..289f501 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -1281,9 +1281,10 @@ print_insn_arg (struct disassemble_info *info, pcrel_op = (const struct mips_pcrel_operand *) operand; info->target = mips_decode_pcrel_operand (pcrel_op, base_pc, uval); - /* Preserve the ISA bit for the GDB disassembler, - otherwise clear it. */ - if (info->flavour != bfd_target_unknown_flavour) + /* For jumps and branches clear the ISA bit except for + the GDB disassembler. */ + if (pcrel_op->include_isa_bit + && info->flavour != bfd_target_unknown_flavour) info->target &= -2; (*info->print_address_func) (info->target, info); -- cgit v1.1