From a1a280bb84485d80f95e2efc1d02e962e0529652 Mon Sep 17 00:00:00 2001 From: DJ Delorie Date: Sat, 22 Oct 2005 00:03:13 +0000 Subject: [cpu] * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing. (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl, indexld, indexls): .w variants have `1' bit. (rot32.b): QI, not SI. (rot32.w): HI, not SI. (xchg16): HI for .w variant. [opcodes] * m32c-asm.c: Regenerate. * m32c-desc.c: Regenerate. * m32c-desc.h: Regenerate. * m32c-dis.c: Regenerate. * m32c-ibld.c: Regenerate. * m32c-opc.c: Regenerate. * m32c-opc.h: Regenerate. --- opcodes/m32c-asm.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'opcodes/m32c-asm.c') diff --git a/opcodes/m32c-asm.c b/opcodes/m32c-asm.c index 1bfa926..fdd1514 100644 --- a/opcodes/m32c-asm.c +++ b/opcodes/m32c-asm.c @@ -879,6 +879,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_A1 : errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_a1, & junk); break; + case M32C_OPERAND_A1A0 : + errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_SI, & junk); + break; case M32C_OPERAND_AN16_PUSH_S : errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_4_1); break; -- cgit v1.1