From 971eda734150ea9cdea47be259486c3a8d087037 Mon Sep 17 00:00:00 2001
From: Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
Date: Wed, 17 Nov 2021 19:21:33 +0000
Subject: aarch64: [SME] Add SME instructions

Patch is adding new SME matrix instructions. Please note additional
instructions will be added in following patches.

gas/ChangeLog:

	* config/tc-aarch64.c (parse_sme_zada_operand):
	New parser.
	* config/tc-aarch64.c (parse_reg_with_qual):
	New reg parser.
	* config/tc-aarch64.c (R_ZA): New egister type.
	(parse_operands): New parser.
	* testsuite/gas/aarch64/sme-illegal.d: New test.
	* testsuite/gas/aarch64/sme-illegal.l: New test.
	* testsuite/gas/aarch64/sme-illegal.s: New test.
	* testsuite/gas/aarch64/sme.d: New test.
	* testsuite/gas/aarch64/sme.s: New test.
	* testsuite/gas/aarch64/sme-f64.d: New test.
	* testsuite/gas/aarch64/sme-f64.s: New test.
	* testsuite/gas/aarch64/sme-i64.d: New test.
	* testsuite/gas/aarch64/sme-i64.s: New test.

include/ChangeLog:

	* opcode/aarch64.h (enum aarch64_opnd): New operands
	AARCH64_OPND_SME_ZAda_2b, AARCH64_OPND_SME_ZAda_3b and
	AARCH64_OPND_SME_Pm.
	(enum aarch64_insn_class): New instruction class sme_misc.

opcodes/ChangeLog:

	* aarch64-opc.c (aarch64_print_operand):
	Print OPND_SME_ZAda_2b and OPND_SME_ZAda_3b operands.
	(verify_constraints): Handle OPND_SME_Pm.
	* aarch64-opc.h (enum aarch64_field_kind):
	New bit fields FLD_SME_ZAda_2b, FLD_SME_ZAda_3b and FLD_SME_Pm.
	* aarch64-tbl.h (OP_SME_ZADA_PN_PM_ZN_S): New qualifier set.
	(OP_SME_ZADA_PN_PM_ZN_D): New qualifier.
	(OP_SME_ZADA_PN_PM_ZN_ZM): New qualifier.
	(OP_SME_ZADA_S_PM_PM_S_S): New qualifier.
	(OP_SME_ZADA_D_PM_PM_D_D): New qualifier.
	(OP_SME_ZADA_S_PM_PM_H_H): New qualifier.
	(OP_SME_ZADA_S_PM_PM_B_B): New qualifier.
	(OP_SME_ZADA_D_PM_PM_H_H): New qualifier.
	(SME_INSN): New instruction macro.
	(SME_F64_INSN): New instruction macro.
	(SME_I64_INSN): New instruction macro.
	(SME_INSNC): New instruction macro.
	(struct aarch64_opcode): New SME instructions.
	aarch64-asm-2.c: Regenerate.
	aarch64-dis-2.c: Regenerate.
	aarch64-opc-2.c: Regenerate.
---
 include/opcode/aarch64.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'include')

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index e361920..cc5a5f3 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -445,6 +445,9 @@ enum aarch64_opnd
   AARCH64_OPND_SVE_ZnxN,	/* SVE vector register list in Zn.  */
   AARCH64_OPND_SVE_Zt,		/* SVE vector register in Zt.  */
   AARCH64_OPND_SVE_ZtxN,	/* SVE vector register list in Zt.  */
+  AARCH64_OPND_SME_ZAda_2b,	/* SME <ZAda>.S, 2-bits.  */
+  AARCH64_OPND_SME_ZAda_3b,	/* SME <ZAda>.D, 3-bits.  */
+  AARCH64_OPND_SME_Pm,		/* SME scalable predicate register, bits [15:13].  */
   AARCH64_OPND_TME_UIMM16,	/* TME unsigned 16-bit immediate.  */
   AARCH64_OPND_SM3_IMM2,	/* SM3 encodes lane in bits [13, 14].  */
 };
@@ -609,6 +612,7 @@ enum aarch64_insn_class
   movewide,
   pcreladdr,
   ic_system,
+  sme_misc,
   sve_cpy,
   sve_index,
   sve_limm,
-- 
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